KR100214526B1 - Process for forming interconnector of semiconductor device - Google Patents

Process for forming interconnector of semiconductor device Download PDF

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Publication number
KR100214526B1
KR100214526B1 KR1019960060309A KR19960060309A KR100214526B1 KR 100214526 B1 KR100214526 B1 KR 100214526B1 KR 1019960060309 A KR1019960060309 A KR 1019960060309A KR 19960060309 A KR19960060309 A KR 19960060309A KR 100214526 B1 KR100214526 B1 KR 100214526B1
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deposition
barrier layer
film
precursor
deposited
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KR19980041043A (en
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김도형
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구본준
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 배선 형성방법에 관한 것으로, 종래에는 기판상에 절연막을 형성하고, 이 절연막을 부분 식각하여 콘택트 홀(contact hole)을 형성하고, 이 절연막과 콘택트 홀에 금속제의 배리어 층(barrier layer)을 증착시킨 후 이 배리어 층위에 화학 기상 증착법(Chemical Vapor Deposition, CVD)을 이용하여 알루미늄 또는 구리를 증착시키는 방법을 사용했으나, 배리어 층을 형성하고 나서 그 위에 증착막을 형성하기 전 배리어 층이 대기에 노출되어 배리어층 상에 자연 산화막(native oxide)이 형성됨으로써, 알루미늄막을 증착시킬 때 알루미늄의 균일한 핵 형성을 방해하고, 결국 알루미늄 증착막이 콘택트 홀 내부를 균일한 밀도로 채우지 못하여 진공을 형성하게 되고, 알루미늄 증착막의 표면을 거칠게 하는 문제점이 있었다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor wiring, and conventionally, an insulating film is formed on a substrate, the insulating film is partially etched to form a contact hole, and a metal barrier layer is formed on the insulating film and the contact hole. After deposition, aluminum or copper was deposited on the barrier layer using Chemical Vapor Deposition (CVD), but the barrier layer was formed after forming the barrier layer and before forming the deposited film thereon. Exposure to the formation of a native oxide on the barrier layer prevents the uniform nucleation of aluminum when the aluminum film is deposited, which eventually causes the aluminum deposition film to not fill the contact hole inside at a uniform density to form a vacuum. This causes a problem of roughening the surface of the aluminum vapor deposition film.

본 발명은 배리어층 상에 기판 의존성이 없는 전구체를 이용하여 대기에 노출된 배리어 층에 제1증착막을 형성하고, 그 위에 증착속도가 빠른 전구체를 이용하여 제2증착막을 형성함으로써, 화학 기상 증착법에 의한 증착공정시 콘택트 홀 내부에 균일한 밀도를 갖게 하여 진공이 발생하지 않도록 하고 증착막 표면의 평탄화를 이룰 수 있는 반도체 배선 형성 방법을 제공하고자 한다.The present invention provides a chemical vapor deposition method by forming a first deposition film on a barrier layer exposed to the atmosphere using a precursor having no substrate dependency on the barrier layer, and forming a second deposition film using a precursor having a high deposition rate thereon. By providing a uniform density in the contact hole during the deposition process by a vacuum to prevent the generation of a semiconductor wiring forming method that can achieve a planarization of the surface of the deposition film.

Description

반도체 배선 형성방법Semiconductor wiring formation method

본 발명은 반도체 배선 형성방법에 관한 것으로, 반도체 기판위에 알루미늄이나 구리의 증착 공정시 콘택트 홀에 진공이 발생하지 않도록 균일한 밀도를 갖게 하고 증착막의 표면의 평탄화를 이룰 수 있도록 한 반도체 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor wiring. It is about.

종래의 반도체 배선 형성 방법을 도시한 도1a 내지 도1d를 참조하여 설명하면 다음과 같다.Referring to FIGS. 1A to 1D, which illustrate a conventional method for forming a semiconductor wiring, are as follows.

기판(10)상에 절연막(11)을 형성하는 단계와(도1a), 이 절연막(11)을 부분 식각하여 콘택트 홀(contact hole)(12)을 형성하는 단계와(도1b), 상기 절연막(11)과 콘택트 홀(12)에 금속제의 배리어 층(barrier layer)(13)을 증착시키는 단계와(도1c), 상기 배리어 층(13) 위에 화학기상 증착법(Chemical Vapor Deposition, CVD)을 이용하여 알루미늄 또는 구리를 증착시키는 단계(도1d)로 구성되었다.Forming an insulating film 11 on the substrate 10 (FIG. 1A), forming a contact hole 12 by partially etching the insulating film 11 (FIG. 1B), and (11) and depositing a metal barrier layer (13) on the contact hole (12) (Fig. 1c), and using a chemical vapor deposition (CVD) on the barrier layer (13) To deposit aluminum or copper (FIG. 1D).

그러나, 상기와 같이 기판(10)위에 알루미늄 또는 구리를 증착시키는 공정에서 배리어 층(13)을 형성하고 나서 그 위에 증착막(14a)을 형성하기 전에 배리어 층(13)이 대기에 노출되어 배리어층(13)상에 자연 산화막(native oxide)이 형성되는데, 이 자연 산화막은 화학기상 증착법에 의해 증착막(14a)을 증착시킬 때 균일한 핵 형성을 방해하게 되고, 결국 증착막(14a)이 콘택트 홀(12) 내부를 균일한 밀도로 채우지 못하게 되어 홀(12)내에 진공을 형성하게 되고, 증착막(14a)의 표면을 거칠게 하는 근본적인 이유가 되어 증착막(14a) 표면의 평탄화를 이루지 못하는 문제점이 있었다.However, after the barrier layer 13 is formed in the process of depositing aluminum or copper on the substrate 10 as described above, the barrier layer 13 is exposed to the atmosphere before the deposition layer 14a is formed thereon. 13, a native oxide film is formed on the native oxide film, which prevents uniform nucleation when the vapor deposition film 14a is deposited by chemical vapor deposition. As a result, the deposition film 14a becomes a contact hole 12. The inside of the hole 12 is not filled with a uniform density, so that a vacuum is formed in the hole 12, which is a fundamental reason for roughening the surface of the deposition film 14a, thereby preventing the planarization of the deposition film 14a surface.

따라서, 본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 배리어층 상에 기판 의존성이 없는 전구체를 이용하여 대기에 노출된 배리어 층에 제1증착막을 형성하고, 그 위에 증착속도가 빠른 화학 기상증착법의 알루미늄 또는 구리를 이용하여 제2증착막을 형성함으로써, 화학 기상 증착법에 의한 증착공정시 콘택트 홀 내부에 균일한 밀도를 갖게 하여 진공이 발생하지 않도록 하고 증착막 표면의 평탄화를 이룰 수 있는 반도체 배선 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made in view of the above, and a first vapor deposition film is formed on a barrier layer exposed to the atmosphere by using a precursor having no substrate dependency on the barrier layer, and a chemical vapor deposition with a high deposition rate thereon. By forming the second deposition film using the aluminum or copper of the deposition method, to have a uniform density inside the contact hole during the deposition process by the chemical vapor deposition method to prevent the generation of vacuum and to form a semiconductor wiring to planarize the surface of the deposition film The purpose is to provide a method.

제1a도 내지 제1d도는 종래의 반도체 배선 형성방법을 나타낸 공정수순도.1A to 1D are process flowcharts showing a conventional method for forming a semiconductor wiring.

제2a도 내지 제2e도는 본 발명에 따른 반도체 배선 형성방법을 나타낸 공정수순도.2A to 2E are process flowcharts showing a method for forming a semiconductor wiring according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 기판 11 : 절연막10 substrate 11 insulating film

12 : 콘택트 홀 13 : 배리어층12 contact hole 13 barrier layer

14 : 제1증착막 15 : 제2증착막14: first deposition membrane 15: second deposition membrane

상기와 같은 목적을 달성하기 위하여 본 발명은 기판상에 절연막을 증착하고 이 절연막을 부분식각하여 콘택트 홀을 형성하는 단계와, 상기 절연막과 콘택트 홀에 배리어 층을 증착하는 단계와, 상기 배리어 층 위에 선택적 증착 특성이 없는 제1전구체를 증착하는 단계와, 상기 제1전구체 위에 증착속도가 빠른 제2전구체를 증착하는 단계를 포함하여 진행하는 것을 특징으로 하는 반도체 배선 형성방법이 제공된다.In order to achieve the above object, the present invention provides a method for forming a contact hole by depositing an insulating film on a substrate and partially etching the insulating film, depositing a barrier layer on the insulating film and the contact hole, And depositing a first precursor having no selective deposition characteristics, and depositing a second precursor having a high deposition rate on the first precursor.

이하, 본 발명의 반도체 배선 형성 방법을 첨부한 도면에 도시한 실시예에 따라 상세히 설명하면 다음과 같다.Hereinafter, the semiconductor wiring forming method of the present invention will be described in detail with reference to the embodiments shown in the accompanying drawings.

먼저, 기판(10)상에 절연막(11)을 증착하고 이 절연막(11)을 부분식각하여 콘택트 홀(12)을 형성하고나서, 상기 절연막(11)과 콘택트 홀(12)에 배리어 층(13)을 증착하는 것은 종래와 동일하다.First, an insulating film 11 is deposited on the substrate 10, and the insulating film 11 is partially etched to form a contact hole 12. Then, the barrier layer 13 is formed in the insulating film 11 and the contact hole 12. ) Is the same as in the prior art.

본 발명의 반도체 배선 형성방법은 상기와 같이 증착된 배리어 층(13) 위에 선택적 증착 특성이 없는 제1전구체를 증착하여 제1증착막(14)을 형성하고, 상기 제1전구체 위에 증착속도가 빠른 제2전구체를 증착하여 제2증착막(15)을 형성하는 순서로 진행된다.The method for forming a semiconductor wiring of the present invention forms a first deposition film 14 by depositing a first precursor having no selective deposition characteristics on the barrier layer 13 deposited as described above, and a deposition rate having a high deposition rate on the first precursor. 2 precursors are deposited to form a second deposition film 15.

상기 기판(10)은 실리콘(Si), 실리사이드(silicide), 알루미늄(AI), 알루미늄 합금(Al alloy)등을 포함하는 재질의 것이고, 이들의 두 개이상의 적층 구조도 이에 해당한다.The substrate 10 is made of a material including silicon (Si), silicide, aluminum (AI), aluminum alloy (Al alloy), and the like, and two or more laminated structures thereof also correspond thereto.

상기 배리어층(13)은 질화 티타늄, 질화 텅스텐 등을 포함하는 질화계 금속으로 되는 것이 바람직하다.The barrier layer 13 is preferably made of a nitride metal containing titanium nitride, tungsten nitride, or the like.

또한, 상기 배리어층(13)은 화학 증착법(CVD)이나 물리 증착법(PVD)을 이용하여 증착하고, 콘택트 홀(12)의 저면에 10-150Å의 두께로 증착되고, 절연막(11)의 상면에 10-1200Å의 두께로 증착되는 것이 바람직하다.In addition, the barrier layer 13 is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD), is deposited on the bottom surface of the contact hole 12 to a thickness of 10-150Å, the upper surface of the insulating film 11 It is desirable to deposit to a thickness of 10-1200 mm 3.

상기 제1전구체는 TMA(trimethyl aluminum)인 것이 바람직하다.Preferably, the first precursor is TMA (trimethyl aluminum).

또한, 상기 제1전구체를 증착하여 형성된 제1증착막(14)은 10-200Å 두께의 박막이다.In addition, the first deposition film 14 formed by depositing the first precursor is a thin film of 10-200 Å thickness.

상기 제2전구체는 DMAH(diethylaluminumhyride) 또는 DMEAA(dimethylaminealane)의 것이고, 콘택트 홀(12) 내부를 채우도록 증착된다.The second precursor is of dimethylaluminumhyride (DMAH) or dimethylaminealane (DMEAA), and is deposited to fill the inside of the contact hole 12.

상기 제1전구체와 제2전구체는 화학 증착법(CVD)으로 증착되고, 증착 온도는 웨이퍼 온도 25-400℃의 범위이고, 증착 압력은 0.1-760torr의 범위인 것이 바람직하다.The first precursor and the second precursor are deposited by chemical vapor deposition (CVD), the deposition temperature is in the range of wafer temperature 25-400 ℃, the deposition pressure is preferably in the range of 0.1-760torr.

상기와 같은 본 발명의 반도체 배선 형성 방법의 작용을 설명하면 다음과 같다.The operation of the semiconductor wiring forming method of the present invention as described above is as follows.

상기 배리어층(13)상에 증착된 제1증착막(14)은 선택적 증착 특성이 없는 제1전구체를 증착하여 형성된 것으로, 상기 제1전구체는 기저층의 고특성에 무관하게 증착하기 때문에 절연막이나 금속제 배리어 상에서 증착 속도가 일정하게 된다.The first deposition layer 14 deposited on the barrier layer 13 is formed by depositing a first precursor having no selective deposition characteristics. Since the first precursor is deposited regardless of the high characteristics of the base layer, an insulating film or a metal barrier The deposition rate is constant over the phase.

따라서, 상기와 같이 증착 속도가 일정한 전구체는 대기에 노출된 배리어에 1단계로 핵형성 층(nucleation layer)을 형성하게 되어 균일 핵형성 과정을 진행한다.Therefore, the precursor having a constant deposition rate as described above forms a nucleation layer in one step on the barrier exposed to the atmosphere, thereby performing a uniform nucleation process.

상기와 같은 1단계 증착 공정 후 기판 의존성은 있으나 증착 속도가 빠른 제2전구체를 제1증착막(14)위에 증착하여 제2증착막(15)을 형성하면, 상기 2단계로 증착공정은 알루미늄 또는 구리의 증착막(14) 위에서 증착되는 것이므로 1단계로 증착 공정을 수행하던 종래의 증착막(14a)보다 치밀하고 균일한 증착막(15)을 형성할 수 있게 된다After the one-step deposition process as described above, if the second precursor is deposited on the first deposition film 14 by depositing a second precursor having a high deposition rate on the substrate, the deposition process is performed in two steps. Since it is deposited on the deposition film 14, it is possible to form a deposition film 15 that is more dense and uniform than the conventional deposition film 14a in which the deposition process was performed in one step.

본 발명의 반도체 배선 형성방법에 의하면, 2단계로 진행되는 증착공정을 통해 콘택트 홀을 채우게 되므로 홀 내부에 균일한 밀도를 갖게 하여 진공이 발생하지 않도록 하고 증착막 표면의 평탄화를 이룸으로써, 반도체 소자의 신뢰성을 확보할 수 있는 효과가 있다.According to the method for forming a semiconductor wiring of the present invention, since the contact hole is filled through the deposition process performed in two steps, a uniform density is provided in the hole so that vacuum does not occur and the surface of the deposited film is flattened, It is effective to secure reliability.

Claims (6)

기판상에 절연막을 증착하고 이 절연막을 부분식각하여 콘택트 홀을 형성하는 단계와, 상기 절연막과 콘택트 홀에 배리어 층을 증착하는 단계와, 상기 배리어 층 위에 선택적 증착 특성이 없는 제1전구체를 증착하는 단계와, 상기 제1전구체 위에 증착속도가 빠른 제2전구체를 증착하는 단계를 포함하여 진행하는 것을 특징으로 하는 반도체 배선 형성방법.Depositing an insulating film on the substrate and partially etching the insulating film to form a contact hole, depositing a barrier layer in the insulating film and the contact hole, and depositing a first precursor having no selective deposition characteristics on the barrier layer. And depositing a second precursor having a high deposition rate on the first precursor. 제1항에 있어서, 상기 배리어층은 화학 증착법(CVD)이나 물리 증착법(PVD)을 이용하여 증착하는 것을 특징으로 하는 반도체 배선 형성 방법.The method of claim 1, wherein the barrier layer is deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD). 제1항 또는 제2항에 있어서, 상기 배리어층은 콘택트 홀의 저면에 10-150Å의 두께로 증착되고, 절연막의 상면에 10-1200Å의 두께로 증착되는 것을 특징으로 하는 반도체 배선 형성 방법.The method of claim 1, wherein the barrier layer is deposited on the bottom surface of the contact hole with a thickness of 10-150 GPa, and is deposited on the upper surface of the insulating film with a thickness of 10-1200 GPa. 제1항에 있어서, 상기 제1전구체는 TMA(trimethyl aluminum)이고, 10-200Å 두께의 박막으로 증착되는 것을 특징으로 하는 반도체 배선 형성방법.The method of claim 1, wherein the first precursor is trimethyl aluminum (TMA) and is deposited as a thin film having a thickness of 10-200 μs. 제1항에 있어서, 상기 제2전구체는 DMAH(diethylaluminumhyride) 또는 DMEAA(dimethylaminealane)이고, 콘택트 홀 내부를 채우도록 증착되는 것을 특징으로 하는 반도체 배선 형성방법.The method of claim 1, wherein the second precursor is dimethylaluminum hydride (DMAH) or dimethylaminealane (DMEAA), and is deposited to fill a contact hole. 제1항에 있어서, 상기 제1전구체와 제2전구체는 화학 증착법(CVD)으로 증착되고, 증착 온도는 웨이퍼 온도 25-400℃의 범위이고, 증착 압력은 0.1-760torr의 범위인 것을 특징으로 하는 반도체 배선 형성방법.The method of claim 1, wherein the first precursor and the second precursor is deposited by chemical vapor deposition (CVD), the deposition temperature is in the range of 25-400 ℃ wafer temperature, the deposition pressure is characterized in that the range of 0.1-760torr Method of forming semiconductor wiring.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7384866B2 (en) 2002-05-30 2008-06-10 Samsung Electronics Co., Ltd. Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7384866B2 (en) 2002-05-30 2008-06-10 Samsung Electronics Co., Ltd. Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer

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