KR970008361A - 반도체 기판의 전처리방법 - Google Patents

반도체 기판의 전처리방법 Download PDF

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KR970008361A
KR970008361A KR1019950021855A KR19950021855A KR970008361A KR 970008361 A KR970008361 A KR 970008361A KR 1019950021855 A KR1019950021855 A KR 1019950021855A KR 19950021855 A KR19950021855 A KR 19950021855A KR 970008361 A KR970008361 A KR 970008361A
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South Korea
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reactor
titanium nitride
substrate
sih
surface treatment
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KR1019950021855A
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English (en)
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KR0167248B1 (ko
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이영종
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문정환
Lg 반도체 주식회사
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Priority to KR1019950021855A priority Critical patent/KR0167248B1/ko
Priority to US08/571,052 priority patent/US5834372A/en
Priority to JP7333447A priority patent/JP2922145B2/ja
Publication of KR970008361A publication Critical patent/KR970008361A/ko
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Publication of KR0167248B1 publication Critical patent/KR0167248B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides

Abstract

본 발명은 반도체 기판의 전처리방법에 관한 것으로, 질화티타늄 기판을 반응기에 장입한 후 상기 반응기를 진공처리하는 공정과; N2나 Ar 또는 He 등을 이용하여 반응기 내를 퍼징한 후 반응기 내의 압력을 1mTorr 이하로 진공처리하는 공정과; WF를 포함하는 반응기체를 소정 시간 투입하여 상기 기판을 표면처리하는 공정 및; 증착하고자 하는 물질의 소스기체와 환원기체를 투입하여 상기 질화티타늄 기판 상에 박막을 형성하는 공정을 포함하여 기판을 전처리하므로써, 1) WO3등과 같은 산화막이 반도체기판의 계면에 형성되는 것을 방지할 수 있으며, 2) 표면처리시간을 적절하게 조절할 수 있어 질화티타늄 입계로의 WFX침투를 억제할 수 있고 3) 적절한 표면처리시간 조절로 질화티타늄의 표면산화층을 완전히 제거할수 있어 이후에 증착되는 박막의 핵생성이 용이할 뿐 아니라 핵생성 사이트가 고르게 분포되므로 균일한 두께를 갖는 박막을 형성할 수 있고, 또한 이로 인해 박막의 밀도를 현저하게 증가시킬 수 있게 된다.

Description

반도체 기판의 전처리방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명으로서, 산화층 화합물이 TiO2라 가정했을 때 WF6-SiH4-TiO2시스템에서의 열역학적 시뮬레이션 결과를 도시한 그래프, (WF6=1mol, SiH4=0.5 mol, P=1Torr), 제5도는 본 발명으로서, 질화티타늄 표면의 Ti2P및 N1SXPS 스펙트럼 결과를 각각 구분하여 도시한 그래프로, (a)는 반응성 스퍼터링에 의해 성장시킨 질화티타늄 박막의 XPS에 의해 분석된 Ti2P및 N1S스펙트럼 결과를 도시한 그래프, (b)는 400℃의 질화티타늄 기판에 WF6- SiH4/H2혼합기체를 20초간 반응시켜 표면 전처리를 한 다음 XPS 분석으로 얻은 Ti2P및 N1S스펙트럼 결과를 도시한 그래프.

Claims (12)

  1. 질화티타늄 기판을 반응기에 장입한 후 상기 반응기를 진공처리하는 공정과; N2나 Ar 또는 He 등을 이용하여 반응기 내를 퍼징한 후 반응기 내의 압력을 1mTorr 이하로 진공처리하는 공정과; WF를 포함하는 반응기체를 투입하여 상기 기판을 표면처리하는 공정 및; 증착하고자 하는 물질의 소스기체와 환원기체를 투입하여 상기 질화티타늄 기판 상에 박막을 형성하는 공정을 포함하여 형성됨을 특징으로 하는 반도체 기판의 전처리방법.
  2. 제1항에 있어서, 상기 WF를 포함하는 반응기체는 WF6화합물을 바탕으로 한 WF6-SiH4이나, WF6-H2, 혹은 WF6-SiH4-H2중 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 기판의 전처리방법.
  3. 제1항에 있어서, 상기 WF를 포함하는 반응기체는 WF4Cl2를 바탕으로 한 WF4Cl2-SiH2이나, WF4Cl2-H2, 혹은 WF4Cl2-SiH2-H2중 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 기판의 전처리방법.
  4. 제2항 또는 제3항에 있어서, 상기 반응기체에 포함되는 SiH4는 Si2H6나 Si3H8로 대체 가능한 것을 특징으로 하는 반도체 기판의 전처리방법.
  5. 제1항에 있어서, 상기 질화티타늄기판의 표면처리 공정 진행시 반응기내의 압력을 10-3Torr-수십 Torr범위 내로 형성하는 것을 특징으로 하는 반도체 기판의 전처리방법.
  6. 제1항 또는 제2항에 있어서, 상기 반응기체의 분압비는 WF6에 대한 SiH4의 분압비가 0.1-1.0의 값을 가지도록 형성하는 것을 특징으로 하는 반도체 기판의 전처리방법.
  7. 제1항에 있어서, 상기 표면처리 공정 진행시의 질화티타늄기판은 300 내지 600℃의 온도를 유지하도록 형성하는 것을 특징으로 하는 반도체 기판의 전처리방법.
  8. 제1항에 있어서, 상기 표면처리 공정은 텅스텐 증착시의 지연시간을 조사하여, 그 지연시간 범위 내에서 상기 공정을 실시하는 것을 특징으로 하는 반도체 기판의 전처리방법.
  9. 제1항 또는 제8항에 있어서, 상기 표면처리 공정은 지연시간의 약 60 - 80% 동안 실시하는 것을 특징으로 하는 반도체 기판의 전처리방법.
  10. 제1항에 있어서, 상기 질화티타늄 기판 상의 박막은 구리, 알루미늄, 텅스텐 및, 각종 금속 실리사이드중 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 기판의 전처리방법.
  11. 제10항에 있어서, 상기 금속 실리사이드는 WSiX또는 TiSiX로 형성하는 것을 특징으로 하는 반도체 기판의 전처리방법.
  12. 제1항에 있어서, 상기 표면처리 및 박막은 인-시튜 공정으로 형성하는 것을 특징으로 하는 반도체 기판의 전처리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950021855A 1995-07-24 1995-07-24 반도체 기판의 전처리방법 KR0167248B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950021855A KR0167248B1 (ko) 1995-07-24 1995-07-24 반도체 기판의 전처리방법
US08/571,052 US5834372A (en) 1995-07-24 1995-12-12 Pretreatment of semiconductor substrate
JP7333447A JP2922145B2 (ja) 1995-07-24 1995-12-21 半導体基板の前処理方法

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KR1019950021855A KR0167248B1 (ko) 1995-07-24 1995-07-24 반도체 기판의 전처리방법

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KR0167248B1 KR0167248B1 (ko) 1999-02-01

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US5834372A (en) 1998-11-10
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KR0167248B1 (ko) 1999-02-01

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