KR950006859A - 기억 장치 - Google Patents

기억 장치 Download PDF

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Publication number
KR950006859A
KR950006859A KR1019940018966A KR19940018966A KR950006859A KR 950006859 A KR950006859 A KR 950006859A KR 1019940018966 A KR1019940018966 A KR 1019940018966A KR 19940018966 A KR19940018966 A KR 19940018966A KR 950006859 A KR950006859 A KR 950006859A
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KR
South Korea
Prior art keywords
power supply
flip
flops
memory
transistor
Prior art date
Application number
KR1019940018966A
Other languages
English (en)
Other versions
KR0132636B1 (en
Inventor
쯔네오 고이께
Original Assignee
가네꼬 히사시
닛본덴기 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가네꼬 히사시, 닛본덴기 가부시끼가이샤 filed Critical 가네꼬 히사시
Publication of KR950006859A publication Critical patent/KR950006859A/ko
Application granted granted Critical
Publication of KR0132636B1 publication Critical patent/KR0132636B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

플립플릅을 메모리 셀로 하는 기억 장치에 있어서, 플립플릅을 구성하는 트랜지스터에 접속되는 전원 라인을 제어함으로써, 서입 이외의 수단으로 메모리의 내용을 설정할 수 있도록 한다.
메모리 셀의 플립플릅을 구성하는 트랜지스터(1및2)에 접속되는 전원 라인을 배열의 일부에서 각각 상호 접속하여 상호 접속된 라인을 전원/그라운드 전위에 접속하는 수위치와 제어 회로(31)을 갖는다.

Description

기억 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예의 메모리 셀 부분의 회로도.
제2도는 본 발명의 제2실시예의 비트선 방향으로 블록화한 메모리의 회로도.

Claims (2)

  1. 한쪽 트랜지스터의 입력을 다른 쪽 트랜지스터의 출력에 접속하고, 출력을 입력에 접속하며, X자 형태로 배치하여 접속한 플립플릅을 메모리 셀로 하여 이 메모리 셀을 복수개 배열한 기억 장치에 있어서, 상기 배열된 플립플릅을 구성하는 X자 형태로 배치된 트랜지스터에 접속되는 전원 라인을 전원으로부터 분리하고, 이 분리된 전원 라인을 배열의 일부에서 각각 상호 접속하여 이들 상호 접속된 라인을 전원 또는 그라운드 전위에 접속하는 스위치 회로를 구비하는 것을 특징으로 하는 기억 장치.
  2. 제1항에 있어서, 스위치 회로가 양쪽 트랜지스터를 동시에 전원 라인에 접속하거나 또는 한쪽 트랜지스터만을 전원 라인에 접속하도록 제어하는 제어 회로에 접속되는 것을 특징으로 하는 기억 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR94018966A 1993-08-02 1994-08-01 Memory device KR0132636B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP93-191044 1993-08-02
JP19104493A JPH0745077A (ja) 1993-08-02 1993-08-02 記憶装置

Publications (2)

Publication Number Publication Date
KR950006859A true KR950006859A (ko) 1995-03-21
KR0132636B1 KR0132636B1 (en) 1998-04-16

Family

ID=16267961

Family Applications (1)

Application Number Title Priority Date Filing Date
KR94018966A KR0132636B1 (en) 1993-08-02 1994-08-01 Memory device

Country Status (4)

Country Link
US (1) US5450353A (ko)
EP (1) EP0642131A3 (ko)
JP (1) JPH0745077A (ko)
KR (1) KR0132636B1 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101672979B1 (ko) 2015-09-15 2016-11-04 (주)금부치아 박판가공장치 및 박판가공방법
KR102619195B1 (ko) 2023-04-26 2023-12-29 주식회사 쥬미에르 우수한 강성 및 내구성을 가지는 순금 세공 방법 및 이를 이용한 금 가공품

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652844A (en) * 1995-06-26 1997-07-29 Motorola, Inc. Flexible pin configuration for use in a data processing system during a reset operation and method therefor
KR100417225B1 (ko) * 1996-04-16 2004-04-21 삼성전자주식회사 서보 어드레스마크 검출 향상을 위한 장치
US5745405A (en) * 1996-08-26 1998-04-28 Taiwan Semiconductor Manufacturing Company, Ltd Process leakage evaluation and measurement method
US5793682A (en) * 1996-11-01 1998-08-11 Cypress Semiconductor Corp. Circuit and method for disabling a bitline load
FR2760286B1 (fr) * 1997-02-28 1999-04-16 Sgs Thomson Microelectronics Procede d'effacement d'une memoire ram statique et memoire en circuit integre associe
US6128215A (en) * 1997-08-19 2000-10-03 Altera Corporation Static random access memory circuits
DE69914142T2 (de) * 1998-03-18 2004-10-28 Koninklijke Philips Electronics N.V. Halbleiteranordnung mit einer speicherzelle
JP2001167573A (ja) 1999-12-06 2001-06-22 Mitsubishi Electric Corp 半導体記憶装置
US6166946A (en) * 2000-01-21 2000-12-26 Hewlett-Packard Company System and method for writing to and reading from a memory cell
US6772277B2 (en) * 2001-04-30 2004-08-03 Hewlett-Packard Development Company, L.P. Method of writing to a memory array using clear enable and column clear signals
US6836420B1 (en) * 2002-03-04 2004-12-28 Synplicity, Inc. Method and apparatus for resetable memory and design approach for same
US7057918B2 (en) * 2004-03-01 2006-06-06 Faraday Technology Corp. Memory unit and memory module using the same
US7458040B1 (en) * 2005-09-01 2008-11-25 Synopsys, Inc. Resettable memory apparatuses and design
US7570537B2 (en) * 2007-07-12 2009-08-04 Sun Microsystems, Inc. Memory cells with power switch circuit for improved low voltage operation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3757313A (en) * 1972-06-29 1973-09-04 Ibm Data storage with predetermined settable configuration
US4858182A (en) * 1986-12-19 1989-08-15 Texas Instruments Incorporated High speed zero power reset circuit for CMOS memory cells
US5267210A (en) * 1988-05-18 1993-11-30 Sgs-Thomson Microelectronics, Inc. SRAM with flash clear for selectable I/OS
US4890263A (en) * 1988-05-31 1989-12-26 Dallas Semiconductor Corporation RAM with capability for rapid clearing of data from memory by simultaneously selecting all row lines
JPH02143992A (ja) * 1988-11-25 1990-06-01 Hitachi Ltd 半導体記憶装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101672979B1 (ko) 2015-09-15 2016-11-04 (주)금부치아 박판가공장치 및 박판가공방법
KR102619195B1 (ko) 2023-04-26 2023-12-29 주식회사 쥬미에르 우수한 강성 및 내구성을 가지는 순금 세공 방법 및 이를 이용한 금 가공품

Also Published As

Publication number Publication date
EP0642131A3 (en) 1995-06-07
US5450353A (en) 1995-09-12
EP0642131A2 (en) 1995-03-08
KR0132636B1 (en) 1998-04-16
JPH0745077A (ja) 1995-02-14

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