KR940003098A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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KR940003098A
KR940003098A KR1019930012380A KR930012380A KR940003098A KR 940003098 A KR940003098 A KR 940003098A KR 1019930012380 A KR1019930012380 A KR 1019930012380A KR 930012380 A KR930012380 A KR 930012380A KR 940003098 A KR940003098 A KR 940003098A
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semiconductor device
doping concentration
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마사후미 미야모또
료 나가이
다쯔야 이시이
고이찌 세끼
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가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract

채널 길이 변동에 의한 스레쉬홀드 전압의 변동을 억제할 수 있고 저전압 동작에 적합한 반도체 장치로서, 쇼트 채널 효과에 의한 스레쉬홀드 전압의 저하를 억제하고 게이트 전극의 치수 변동에 의한 스레쉬홀드 전압의 변동을 저감하며 캐리어 이동도를 높이기 위해, 반도체 기판의 표면에 형성된 저농도의 제1의 영역에 소스, 드레인 영역을 형성하고, 제1의 영역보다 도핑 농도가 높은 제2의 영역을 형성하고, 제2의 영역에, 제2의 영역보다 도핑 농도가 높은 영역을 서로 분리하여 형성한다.
이러한 반도체 장치를 사용하는 것에 의해, 채널길이의 저감에 수반되는 스레쉬홀드 전압의 상승이 제3의 영역에 의해 상쇄되어 쇼트 채널 효과가 억제되며, 제7의 영역의 도핑 농도가 낮으므로, 높은 캐리어 이동도를 얻을 수 있다.

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예1을 도시한 단면도.
제2도는 본 발명의 실시예2를 도시한 단면도.
제3도a및 제3도b는 본 발명의 실시예3을 도시한 단면도 및 반도체 기판내에 도핑 농도 프로파일을 도시한 그래프.
제4도는 제3도b의 스레쉬홀드 전압과 도핑 농도 프로파일의 기울기 α사이의 관계를 도시한 그래프.

Claims (18)

  1. 제1의 도전형을 갖는 반도체 기판의 표면 영역내에 형성되고 낮은 도핑 농도 및 상기 제1의 도전형을 갖는 제1의 영역 상기 제1의 영역의 표면 영역내에 소정의 거리를 두고 배치되고 상기 제1의 도전형과 반대인 제2의 도전형을 갖는 소스 영역 및 드레인 영역, 상기 제1의 영역의 아래면과 접촉하는 상기 반도체 기판내에 형성되고 상기 제1의 영역보다 높은 도핑 농도 및 상기 제1의 도전형을 갖는 제2의 영역과 상기 소스 영역 아래의 상기 제2의 영역내에 형성되고 상기 제2의 영역보다 높은 도핑 농도 및 상기 제1의 도전형을 갖는 제3의 영역을 포함하는 반도체 장치.
  2. 제1항에 있어서, 상기 드레인 영역아래의 상기 제2의 영역내에 형성되고 상기 제2의 영역보다 높은 도핑 농도 및 상기 제1의 도전형을 갖는 제4의 영역을 또 포함하는 반도체 장치.
  3. 제2항에 있어서, 상기 소스 영역 또는 드레인 영역의 끝에서 상기 제3의 영역까지의 좌우 거리는 상기 소스 영역과 상기 드레인 영역사이 거리의 1/2이하인 반도체 장치.
  4. 제2항에 있어서, 상기 제2의 영역 및 상기 제3의 영역은 절연막에 형성되는 반도체 장치.
  5. 제2항에 있어서, 상기 제3의 영역의 아래면의 깊이는 상기 제2의 영역의 아래면의 깊이와 같은 반도체 장치.
  6. 제2항에 있어서, 상기 제3의 영역의 아래면의 깊이는 상기 제2의 영역의 아래면의 깊이보다 얕은 반도체 장치.
  7. 제6항에 있어서, 상기 제3의 영역의 위면의 깊이는 상기 제1의 영역의 깊이보다 얕은 반도체 장치.
  8. 제2항에 있어서, 상기 게이트 전극의 옆부분에는 절연체의 측벽이 형성되는 반도체장치.
  9. 제8항에 있어서, 상기 제3의 영역은 상기 측벽은 마스크로서 사용하여 경사 이온주입에 의해 형성된 영역인 반도체 장치.
  10. 제2항에 있어서, 상기 제1의 도전형을 갖는 저농도 영역은 상기 드레인 영역 및 상기 소스 영역의 글과 각각 접속하여 형성되는 반도체 장치.
  11. 제2항에 있어서, 상기 제1의 영역의 아래면의 깊이는 0.01㎛∼0.2㎛인 반도체 장치.
  12. 제2항에 있어서, 상기 제1의 영역의 도핑 농도는 1×1015∼1×1018/㎤인 반도체 장치.
  13. 제2항에 있어서, 상기 제2외 영역의 두께는 0.01∼0.6㎛인 반도체 장치.
  14. 제2항에 있어서, 상기 제2의 영역의 도핑 농도는 1×1017∼1×1019/㎤인 반도체 장치.
  15. 제2항에 있어서, 상기 제3의 영역의 두께는 0.01∼0.6㎛인 반도체 장치.
  16. 제2항에 있어서, 상기 제3의 영역의 도핑 농도는 1×1017∼1×1019/㎤인 반도체 장치.
  17. 제2항에 있어서, 상기 제3의 영역의 서로 대향하는 끝사이의 거리는 상기 소스영역과 상기 드레인 영역사이 거리의 1/2보다 작은 반도체 장치.
  18. 제2항에 있어서, 상기 제1의 영역의 끝과 상기 제3의 영역의 끝사이의 좌우 거리는 0.01㎛∼0.2㎛인 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930012380A 1992-07-10 1993-07-02 반도체 장치 KR100277198B1 (ko)

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JP92-183448 1992-07-10
JP18344892A JP3435173B2 (ja) 1992-07-10 1992-07-10 半導体装置

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