KR920013788A - 단일의 폴리(poly) 바이폴라 공정중에 쇼트키 장벽 다이오드를 제조하는 개선된 방법 - Google Patents
단일의 폴리(poly) 바이폴라 공정중에 쇼트키 장벽 다이오드를 제조하는 개선된 방법 Download PDFInfo
- Publication number
- KR920013788A KR920013788A KR1019910022712A KR910022712A KR920013788A KR 920013788 A KR920013788 A KR 920013788A KR 1019910022712 A KR1019910022712 A KR 1019910022712A KR 910022712 A KR910022712 A KR 910022712A KR 920013788 A KR920013788 A KR 920013788A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide layer
- substrate
- region
- forming
- polybipolar
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims 5
- 230000004888 barrier function Effects 0.000 title 1
- 239000000758 substrate Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims 3
- 238000000151 deposition Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66212—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0761—Vertical bipolar transistor in combination with diodes only
- H01L27/0766—Vertical bipolar transistor in combination with diodes only with Schottky diodes only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/14—Schottky barrier contacts
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 실시예에 따라 산화물층을 선택적으로 도포한 실리콘 기판, 제3도는 본 발명의 실시예에 따라 폴리실리콘 층을 데포지트한 실리콘 기판, 제4도는 본 발명의 실시예에 따라 주입 마스크를 폴리실리콘층상에 도포한 실리콘 기판.
Claims (1)
- 상부표면을 지니되, 선택된 위치에 N도전성 영역이 형성되어 있는 집적회로 기판상에 다이오드를 형성하는 방법에 있어서, (a)상기 기판의 상부 표면상에 산화물층을 형성하는 단계, (b)적어도 상기 기판의 상부표면에 인접해 있는 N영역의 폭을 따라 상기 산화물층이 남아있도록 마스크를 사용하여 산화물층의 일부를 제거하는 단계.(c)상기 기판의 상부표면 및 상기 산화물층상에 재료층을 데포지트하는 단계 (d)적어도 다이오드 애노드가 형성될 선택된 영역에서 상기 재료를 제거하되, 상기 재료의 제거가 상기 산화물층상에서 중지되게 하는 단계.(e)적어도 상기 기판의 표면과 접촉하는 N영역의 주어진 부분상에 상기 N영역을 노출시키도록 플라즈마 공정을 사용하지 않고서도 상기 산화물을 제거하는 단계, 및 (g)다이오드 애노드를 형성하도록 상기 N영역의 노출된 부분상에 금속을 데포지트시키는 단계를 포함하는 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US62716090A | 1990-12-13 | 1990-12-13 | |
US90-627160 | 1990-12-13 | ||
US90-07627160 | 1990-12-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920013788A true KR920013788A (ko) | 1992-07-29 |
KR100238503B1 KR100238503B1 (ko) | 2000-01-15 |
Family
ID=24513454
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910022712A KR100238503B1 (ko) | 1990-12-13 | 1991-12-12 | 단일의 폴리 바이폴라 공정중에 쇼트키 장벽 다이오드를 제조하는 개선된 방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5298437A (ko) |
EP (1) | EP0490236A3 (ko) |
JP (1) | JP3388590B2 (ko) |
KR (1) | KR100238503B1 (ko) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06310492A (ja) * | 1993-04-23 | 1994-11-04 | Fuji Xerox Co Ltd | チタン系薄膜のエッチング液及び半導体装置の製造方法 |
JP4944460B2 (ja) * | 2005-03-30 | 2012-05-30 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置 |
US8338906B2 (en) * | 2008-01-30 | 2012-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Schottky device |
US8686419B2 (en) * | 2010-02-23 | 2014-04-01 | Sandisk 3D Llc | Structure and fabrication method for resistance-change memory cell in 3-D memory |
JP2019033180A (ja) * | 2017-08-08 | 2019-02-28 | 株式会社村田製作所 | 半導体装置 |
JP7258668B2 (ja) * | 2019-06-13 | 2023-04-17 | 三菱電機株式会社 | 半導体装置、及び、半導体装置の製造方法 |
CN110752256B (zh) * | 2019-10-22 | 2021-04-06 | 深圳第三代半导体研究院 | 一种碳化硅肖特基钳位晶体管及其制备方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4628339A (en) * | 1981-02-11 | 1986-12-09 | Fairchild Camera & Instr. Corp. | Polycrystalline silicon Schottky diode array |
JPS5975659A (ja) * | 1982-10-22 | 1984-04-28 | Fujitsu Ltd | 半導体装置の製造方法 |
US4982244A (en) * | 1982-12-20 | 1991-01-01 | National Semiconductor Corporation | Buried Schottky clamped transistor |
US4609568A (en) * | 1984-07-27 | 1986-09-02 | Fairchild Camera & Instrument Corporation | Self-aligned metal silicide process for integrated circuits having self-aligned polycrystalline silicon electrodes |
US4764480A (en) * | 1985-04-01 | 1988-08-16 | National Semiconductor Corporation | Process for making high performance CMOS and bipolar integrated devices on one substrate with reduced cell size |
US4674173A (en) * | 1985-06-28 | 1987-06-23 | Texas Instruments Incorporated | Method for fabricating bipolar transistor |
US4898838A (en) * | 1985-10-16 | 1990-02-06 | Texas Instruments Incorporated | Method for fabricating a poly emitter logic array |
US4717678A (en) * | 1986-03-07 | 1988-01-05 | International Business Machines Corporation | Method of forming self-aligned P contact |
US4835580A (en) * | 1987-04-30 | 1989-05-30 | Texas Instruments Incorporated | Schottky barrier diode and method |
EP0304729B1 (en) * | 1987-08-14 | 1993-03-17 | Fairchild Semiconductor Corporation | Etch back detection |
US4969027A (en) * | 1988-07-18 | 1990-11-06 | General Electric Company | Power bipolar transistor device with integral antisaturation diode |
US4897364A (en) * | 1989-02-27 | 1990-01-30 | Motorola, Inc. | Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer |
US4983531A (en) * | 1990-02-12 | 1991-01-08 | Motorola, Inc. | Method of fabricating a single polysilicon bipolar transistor which is compatible with a method of fabricating CMOS transistors |
US5059555A (en) * | 1990-08-20 | 1991-10-22 | National Semiconductor Corporation | Method to fabricate vertical fuse devices and Schottky diodes using thin sacrificial layer |
-
1991
- 1991-12-03 EP EP19910120753 patent/EP0490236A3/en not_active Withdrawn
- 1991-12-11 JP JP32721791A patent/JP3388590B2/ja not_active Expired - Lifetime
- 1991-12-12 KR KR1019910022712A patent/KR100238503B1/ko not_active IP Right Cessation
-
1992
- 1992-07-28 US US07/922,341 patent/US5298437A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0490236A2 (en) | 1992-06-17 |
JPH06216369A (ja) | 1994-08-05 |
JP3388590B2 (ja) | 2003-03-24 |
EP0490236A3 (en) | 1992-08-12 |
KR100238503B1 (ko) | 2000-01-15 |
US5298437A (en) | 1994-03-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR920005345A (ko) | 터널 주입형 반도체장치 및 그 제조방법 | |
KR970030681A (ko) | 반도체장치의 제조방법 | |
KR940016513A (ko) | 반도체소자의 저저항 접촉형성방법 | |
KR870007565A (ko) | 반도체장치 및 그 제조방법 | |
KR890007364A (ko) | 반도체 소자 제조 방법 | |
KR920013788A (ko) | 단일의 폴리(poly) 바이폴라 공정중에 쇼트키 장벽 다이오드를 제조하는 개선된 방법 | |
KR930009023A (ko) | 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택매립방법 | |
KR950021526A (ko) | 반도체 장치 및 그의 제조방법 | |
KR890001168A (ko) | 반도체 장치에서의 절연산화물 형성방법 및 그 방법에 따라 제조된 반도체 장치 | |
KR910005458A (ko) | 반도체장비의 제조방법 | |
KR970008640A (ko) | 반도체 장치 | |
KR900019257A (ko) | 쌍극 범프 트랜지스터와 그 트랜지스터 제조 방법 | |
KR900003974A (ko) | 반도체장치의 제조방법 | |
KR970008265A (ko) | 금속이 코팅된 3극 필드 에미터 제조방법 | |
KR960026428A (ko) | 박막트랜지스터의 제조방법 | |
KR930024106A (ko) | 반도체 소자의 콘택형성방법 | |
KR930011227A (ko) | 롬 제조방법 | |
KR970077349A (ko) | 반도체 소자에서의 금속배선의 구조 및 그 제조 방법 | |
KR980005619A (ko) | 반도체 소자의 콘택홀 형성방법 | |
KR980006235A (ko) | 반도체 소자의 제조방법 | |
KR980005380A (ko) | 얼라인 마크의 형성 방법 | |
KR970018742A (ko) | 고속 회복 다이오드 제조 방법 및 그 소자 | |
KR970067639A (ko) | 바이폴라 소자의 컨택형성 방법 | |
JPH05283715A (ja) | 高安定ツェナーダイオード | |
KR970063500A (ko) | 반도체소자의 금속배선 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20110928 Year of fee payment: 13 |
|
EXPY | Expiration of term |