KR940016513A - 반도체소자의 저저항 접촉형성방법 - Google Patents

반도체소자의 저저항 접촉형성방법 Download PDF

Info

Publication number
KR940016513A
KR940016513A KR1019920026723A KR920026723A KR940016513A KR 940016513 A KR940016513 A KR 940016513A KR 1019920026723 A KR1019920026723 A KR 1019920026723A KR 920026723 A KR920026723 A KR 920026723A KR 940016513 A KR940016513 A KR 940016513A
Authority
KR
South Korea
Prior art keywords
contact
metal
forming
diffusion layer
low resistance
Prior art date
Application number
KR1019920026723A
Other languages
English (en)
Other versions
KR960004089B1 (ko
Inventor
김상영
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920026723A priority Critical patent/KR960004089B1/ko
Priority to US08/173,552 priority patent/US5391521A/en
Publication of KR940016513A publication Critical patent/KR940016513A/ko
Application granted granted Critical
Publication of KR960004089B1 publication Critical patent/KR960004089B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 N+접촉에는 N+실리콘과 전위장벽이 낮은 물질을 N+접촉용 금속으로 사용하고 P+접촉에는 P+실리콘과 전위장벽이 낮은 물질을 P+접촉용 금속으로 사용하여 저저항을 갖는 접촉을 형성하기 위하여 2번의 마스크 작업을 통하여 N+접촉과 P+접촉을 분리하여 형성시켜서 저저항의 접촉을 실현하는 기술이다.

Description

반도체소자의 저저항 접촉형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 내지 제1I도는 실리콘기판에 N+확산층과 P+확산층을 형성한 후 N+확산층 위에만 접촉창을 열고 N+실리콘과 장벽높이가 낮은 금속으로 접촉을 형성한 후 또 한번의 마스크 작업을 통하여 P+확산층 위에 접촉창을 열고 P+실리콘과 장벽높이가 낮은 금속으로 접촉을 형성하고 확산 방지금속층이 있는 금속배선을 형성하는 공정을 나타내는 반도체소자의 단면도.

Claims (3)

  1. 고집적 반도체소자의 저저항 접촉형성방법에 있어서, 실리콘기판(1)에 N+확산층(2) 및 P+확산층(3)을 형성하는 단계와, 상기 N+확산층(2) 및 P+확산층(3)이 형성된 실리콘기판(1)상에 층간 절연막(4)을 증착하고, 그 상부에 감광막(5)을 코팅한 후 상기 N+확산층(2) 상부에 N+접촉창을 형성하는 단계와, 잔존하는 감광막(5)을 제거하는 단계와, 상기 N+접촉창 상부에 N+접촉용 금속(6)을 증착한 후, 마스크 작업을 통하여 N+접촉용 금속(6) 패턴을 형성하는 단게와, 전체구조 상부에 감광막(5)을 코팅한 후 마스크 작과 건식식각 공정으로 P+확산층(3) 상부에 P+접촉창을 형성하는 단계와, 잔존하는 감광막(5)을 제거하는 단계와, 전체구조 상부에 P+접촉용 금속(7)을 증착한 후 마스크공정으로 P+접촉용 금속(7)의 패턴을 형성하는 단계와 전체구조 상부에 확산방지 금속층(8)과 금속배선(9)을 순차적으로 증착한 후, 마스크공정을 통하여 금속배선을 형성하는 단계를 포함하는 것을 특징으로 하는 고집적 반도체소자의 저저항 접촉형성 방법.
  2. 제 1 항에 있어서, N+접촉용 금속은 Ti인 것을 특징으로 하는 고집적 반도체소자의 저저항 접촉형성 방법.
  3. 제 1 항에 있어서, P+접촉용 금속은 PtSi인 것을 특징으로 하는 고집적 반도체소자의 저저항 접촉형성 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920026723A 1992-12-30 1992-12-30 반도체소자의 저저항 접촉형성방법 KR960004089B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019920026723A KR960004089B1 (ko) 1992-12-30 1992-12-30 반도체소자의 저저항 접촉형성방법
US08/173,552 US5391521A (en) 1992-12-30 1993-12-27 Method for fabricating low resistance contacts of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920026723A KR960004089B1 (ko) 1992-12-30 1992-12-30 반도체소자의 저저항 접촉형성방법

Publications (2)

Publication Number Publication Date
KR940016513A true KR940016513A (ko) 1994-07-23
KR960004089B1 KR960004089B1 (ko) 1996-03-26

Family

ID=19347858

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920026723A KR960004089B1 (ko) 1992-12-30 1992-12-30 반도체소자의 저저항 접촉형성방법

Country Status (2)

Country Link
US (1) US5391521A (ko)
KR (1) KR960004089B1 (ko)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070228110A1 (en) * 1993-11-16 2007-10-04 Formfactor, Inc. Method Of Wirebonding That Utilizes A Gas Flow Within A Capillary From Which A Wire Is Played Out
US6184053B1 (en) 1993-11-16 2001-02-06 Formfactor, Inc. Method of making microelectronic spring contact elements
US6727580B1 (en) 1993-11-16 2004-04-27 Formfactor, Inc. Microelectronic spring contact elements
US6624648B2 (en) 1993-11-16 2003-09-23 Formfactor, Inc. Probe card assembly
US7579269B2 (en) * 1993-11-16 2009-08-25 Formfactor, Inc. Microelectronic spring contact elements
US20020053734A1 (en) 1993-11-16 2002-05-09 Formfactor, Inc. Probe card assembly and kit, and methods of making same
US6246247B1 (en) 1994-11-15 2001-06-12 Formfactor, Inc. Probe card assembly and kit, and methods of using same
US6835898B2 (en) * 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US6727579B1 (en) 1994-11-16 2004-04-27 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
ATE210895T1 (de) 1995-03-20 2001-12-15 Unitive Int Ltd Löthöcker-herstellungsverfahren und strukturen mit einer titan-sperrschicht
US20100065963A1 (en) * 1995-05-26 2010-03-18 Formfactor, Inc. Method of wirebonding that utilizes a gas flow within a capillary from which a wire is played out
US6483328B1 (en) * 1995-11-09 2002-11-19 Formfactor, Inc. Probe card for probing wafers with raised contact elements
US8033838B2 (en) 1996-02-21 2011-10-11 Formfactor, Inc. Microelectronic contact structure
US5728619A (en) * 1996-03-20 1998-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Selective reactive Ion etch (RIE) method for forming a narrow line-width high aspect ratio via through an integrated circuit layer
WO1997043653A1 (en) * 1996-05-17 1997-11-20 Formfactor, Inc. Contact tip structures for microelectronic interconnection elements and methods of making same
TW341747B (en) * 1996-05-17 1998-10-01 Formfactor Inc Techniques of fabricating interconnection elements and tip structures for same using sacrificial substrates
US6520778B1 (en) 1997-02-18 2003-02-18 Formfactor, Inc. Microelectronic contact structures, and methods of making same
US7714235B1 (en) 1997-05-06 2010-05-11 Formfactor, Inc. Lithographically defined microelectronic contact structures
EP0985231A1 (en) * 1997-05-15 2000-03-15 Formfactor, Inc. Lithographically defined microelectronic contact structures
KR100268456B1 (ko) * 1997-12-04 2000-11-01 윤종용 반도체장치의콘택형성방법
US6807734B2 (en) 1998-02-13 2004-10-26 Formfactor, Inc. Microelectronic contact structures, and methods of making same
US6255126B1 (en) * 1998-12-02 2001-07-03 Formfactor, Inc. Lithographic contact elements
US6759311B2 (en) 2001-10-31 2004-07-06 Formfactor, Inc. Fan out of interconnect elements attached to semiconductor wafer
KR100443079B1 (ko) * 2002-08-19 2004-08-02 삼성전자주식회사 반도체 장치의 제조방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01268150A (ja) * 1988-04-20 1989-10-25 Yamaha Corp 半導体装置
JPH02123740A (ja) * 1988-11-02 1990-05-11 Mitsubishi Electric Corp 半導体装置
US5234863A (en) * 1990-12-11 1993-08-10 Seiko Instruments Inc. Method of manufacturing doped contacts to semiconductor devices
JPH04349660A (ja) * 1991-05-28 1992-12-04 Toshiba Corp 半導体装置及び製造方法

Also Published As

Publication number Publication date
US5391521A (en) 1995-02-21
KR960004089B1 (ko) 1996-03-26

Similar Documents

Publication Publication Date Title
KR940016513A (ko) 반도체소자의 저저항 접촉형성방법
KR950034678A (ko) 집적 회로내에 전도성 접속부 형성 방법 및, 그 회로내의 전도성 부재
KR950021526A (ko) 반도체 장치 및 그의 제조방법
KR920013788A (ko) 단일의 폴리(poly) 바이폴라 공정중에 쇼트키 장벽 다이오드를 제조하는 개선된 방법
KR950025869A (ko) 콘택홀 형성방법
KR970067645A (ko) 반도체 소자의 금속층 형성 방법
KR970072086A (ko) 반도체 소자의 금속 배선 형성 방법
KR940016629A (ko) 삼층감광막 패턴 형성방법
KR950001896A (ko) 배선층 스텝커버리지 특성 개선방법
KR950021285A (ko) 금속배선층 형성방법
KR970053571A (ko) 반도체 장치 및 그의 제조 방법
KR970052537A (ko) 반도체장치의 제조방법
KR960035969A (ko) 금속 배선층 형성 방법
KR950034523A (ko) 반도체장치 제조방법
KR980005531A (ko) 반도체 소자의 금속배선 형성방법
KR930003254A (ko) 반도체 장치의 금속배선 방법
KR910003761A (ko) 반도체 소자의 다층금속배선 공정방법
KR950025937A (ko) 반도체 소자의 패드 형성방법
KR930017096A (ko) 반도체장치와 그 제조방법
KR960039420A (ko) 3극 필드 에미터 제조방법
KR980005650A (ko) 반도체 장치의 콘택홀 형성방법
KR930001390A (ko) 금속 배선막 형성방법
KR950006539A (ko) 반도체소자의 제조 방법
KR970003851A (ko) 반도체 소자의 금속배선 형성방법
KR920010877A (ko) 금속배선 콘택형성 방법

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110222

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee