KR930009023A - 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택매립방법 - Google Patents

선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택매립방법 Download PDF

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Publication number
KR930009023A
KR930009023A KR1019910018500A KR910018500A KR930009023A KR 930009023 A KR930009023 A KR 930009023A KR 1019910018500 A KR1019910018500 A KR 1019910018500A KR 910018500 A KR910018500 A KR 910018500A KR 930009023 A KR930009023 A KR 930009023A
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South Korea
Prior art keywords
layer
interlayer insulating
insulating layer
contact
metal layer
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KR1019910018500A
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English (en)
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KR950012918B1 (ko
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김상영
송용욱
김헌도
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정몽헌
현대전자산업 주식회사
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Priority to KR1019910018500A priority Critical patent/KR950012918B1/ko
Publication of KR930009023A publication Critical patent/KR930009023A/ko
Priority to US08/327,887 priority patent/US5683938A/en
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Publication of KR950012918B1 publication Critical patent/KR950012918B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 고집적 반도체 소자 제조공정중 콘택홈에 금속을 매립하는 방법에 관한것으로, 단차가 차이나는 콘택홈에서 금속층의 스탭커버리지를 향상시키기 위하여 선택적 텅스텐 박막을 2단계로 퇴적하는 콘택매립방법에 관한 기술이다.

Description

선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택매립방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2D도는 본 발명의 공정방법에 의하여 2단계로 콘택홈을 형성하고 2단계로 선택적 텅스텐 박막을 퇴적시킨 상태를 도시한 단면도.

Claims (2)

  1. 실리콘 기판 상부에 필드산화막, N+ 또는 P+ 접합층 및 게이트 전극을 각각 형성하고, 전체구조 상부에 제1층간절연층을 형성하고, 제1층간 절연층의 예정된 영역에 도전층 패턴을 형성한다음, 전체구조 상부에 제2층간 절연층을 형성하고, 상기의 제2층간 절연층, 제1층간 절연층의 에정된 부분을 제거하여 접합층, 게이트 전극 및 도전층 패턴등이 노출된 콘택홈을 형성하고 금속층을 콘택홈에 매립하는 방법에 있어서, 콘택홈의 단차의 차이로 인해 금속층의 스텝커버리지가 나빠지는 것을 방지하기 위하여, 실리콘 기판 상부에 필드산화막, 접합층, 및 게이트전극을 각각 형성하고, 전체구조 상부에 제1층간 절연층의 예정된 부분을 제거하여 하부의 접합층 및 게이트 전극이 노출된 제1콘택홈을 형성하는 단계와, 제1콘택홈에 금속층을 완전히 매립한다음, 이 금속층과 이격된 제1층간 절연층 상부에 도전층 패턴을 형성하는 단계와, 전체 구조 상부에 제2층간절연층을 형성한후, 제2층간 절연층의 예정된 부분을 제거하여 하부의 제1콘태홈의 금속층과 도전층 패턴이 노출된 제2콘택홈을 형성하는 단계와, 제2콘택홈에 금속층을 매립하여 하부의 금속층과 도전층 패턴에 접속하는 단계로 이루어지는 것을 특징으로 하는 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택 매립방법.
  2. 제1항에 있어서, 상기 제1콘택홈 및 제2콘택홈에 매립하는 금속층은 선택적 텅스텐 박막을 화학시상 증착법으로 형성하는 것을 특징으로 하는 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택 매립방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910018500A 1991-10-21 1991-10-21 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택 매립방법 KR950012918B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019910018500A KR950012918B1 (ko) 1991-10-21 1991-10-21 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택 매립방법
US08/327,887 US5683938A (en) 1991-10-21 1994-10-24 Method for filling contact holes with metal by two-step deposition

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910018500A KR950012918B1 (ko) 1991-10-21 1991-10-21 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택 매립방법

Publications (2)

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KR930009023A true KR930009023A (ko) 1993-05-22
KR950012918B1 KR950012918B1 (ko) 1995-10-23

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US (1) US5683938A (ko)
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KR950012918B1 (ko) 1995-10-23
US5683938A (en) 1997-11-04

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