KR910003670A - 정적형 반도체 기억장치 - Google Patents

정적형 반도체 기억장치 Download PDF

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Publication number
KR910003670A
KR910003670A KR1019900010671A KR900010671A KR910003670A KR 910003670 A KR910003670 A KR 910003670A KR 1019900010671 A KR1019900010671 A KR 1019900010671A KR 900010671 A KR900010671 A KR 900010671A KR 910003670 A KR910003670 A KR 910003670A
Authority
KR
South Korea
Prior art keywords
semiconductor memory
memory cells
voltage source
driving
columns
Prior art date
Application number
KR1019900010671A
Other languages
English (en)
Other versions
KR930009544B1 (ko
Inventor
요우이찌 도비다
유우지 기하라
Original Assignee
시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시기 모리야, 미쓰비시 뎅끼 가부시끼가이샤 filed Critical 시기 모리야
Publication of KR910003670A publication Critical patent/KR910003670A/ko
Application granted granted Critical
Publication of KR930009544B1 publication Critical patent/KR930009544B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음.

Description

정적형 반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예를 표시하는 SRAM의 부분회로도.
제3도는 본 발명의 타의 실시예를 표시하는 테스트용 전원 회로의 회로도.
제4도는 본 발명의 타의 실시예를 표시하는 신호 발생 회로의 회로도.

Claims (1)

  1. 정직형 반도체 기억 장치에 있어서, 각각이 플립플롭으로 이루고 또한 행 및 열의 매트릭스 로 배열된 복수개의 메모리셀과, 상기 메모리셀의 열에 따라 설정되어 또한 각 메모리셀에 접속되는 복수개의 비트선과, 상기 복수개의 메모리셀에 접속되어 상기 메모리셀을 구동하는 전압원을 비치하고, 상기 전압원을 복수의 크기의 구동 전압을 포함하고, 상기 반도체 기억 장치의 통상 모드와, 적어도 1개의 테스트 모드를 각각 지시하는 지수 수단과, 상기 지시 수단에서의 지시 출력에 응답하고 상기 전압원의 구동 전압의 크기를 선택하는 선택수 단을 더욱 비치한 정적형 반도체 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900010671A 1989-07-13 1990-07-13 정적형 반도체 기억 장치 KR930009544B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1180969A JPH0346193A (ja) 1989-07-13 1989-07-13 スタティック型半導体記憶装置
JP1-180969 1989-07-13
JP89-180969 1989-07-13

Publications (2)

Publication Number Publication Date
KR910003670A true KR910003670A (ko) 1991-02-28
KR930009544B1 KR930009544B1 (ko) 1993-10-06

Family

ID=16092446

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900010671A KR930009544B1 (ko) 1989-07-13 1990-07-13 정적형 반도체 기억 장치

Country Status (4)

Country Link
US (1) US5079744A (ko)
JP (1) JPH0346193A (ko)
KR (1) KR930009544B1 (ko)
DE (1) DE4022157A1 (ko)

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US5289475A (en) * 1990-11-29 1994-02-22 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with inverted write-back capability and method of testing a memory using inverted write-back
US5199034A (en) * 1990-12-31 1993-03-30 Texas Instruments Incorporated Apparatus and method for testing semiconductors for cell to bitline leakage
US5257227A (en) * 1991-01-11 1993-10-26 International Business Machines Corp. Bipolar FET read-write circuit for memory
US5250854A (en) * 1991-11-19 1993-10-05 Integrated Device Technology, Inc. Bitline pull-up circuit operable in a low-resistance test mode
JP2762826B2 (ja) * 1992-03-09 1998-06-04 日本電気株式会社 半導体メモリ
JPH0612896A (ja) * 1992-04-28 1994-01-21 Nec Corp 半導体記憶装置
KR940016288A (ko) * 1992-12-25 1994-07-22 오가 노리오 반도체메모리 및 그 선별방법
JP3212396B2 (ja) * 1993-01-14 2001-09-25 富士通株式会社 不揮発性半導体記憶装置
JPH06349298A (ja) * 1993-04-14 1994-12-22 Nec Corp 半導体装置
GB2277161B (en) * 1993-04-14 1997-06-04 Plessey Semiconductors Ltd Memory defect detection arrangement
TW243531B (ko) * 1993-09-03 1995-03-21 Motorola Inc
US5379260A (en) * 1993-09-30 1995-01-03 Sgs-Thomson Microelectronics, Inc. Memory cell having a super supply voltage
JPH0862294A (ja) * 1994-08-25 1996-03-08 Mitsubishi Electric Corp 半導体装置及び半導体装置のテスト方法
US5619459A (en) * 1995-05-31 1997-04-08 Micron Technology, Inc. On-chip mobile ion contamination test circuit
US5880593A (en) 1995-08-30 1999-03-09 Micron Technology, Inc. On-chip substrate regulator test mode
US6822470B2 (en) 1995-08-30 2004-11-23 Micron Technology, Inc. On-chip substrate regulator test mode
KR0172350B1 (ko) * 1995-12-29 1999-03-30 김광호 반도체 메모리 장치의 고속 디스터브 테스트 방법 및 워드라인 디코더
US5867719A (en) * 1996-06-10 1999-02-02 Motorola, Inc. Method and apparatus for testing on-chip memory on a microcontroller
JPH10144096A (ja) * 1996-11-14 1998-05-29 Mitsubishi Electric Corp スタティック型半導体記憶装置およびそのテスト方法
US5898235A (en) * 1996-12-31 1999-04-27 Stmicroelectronics, Inc. Integrated circuit with power dissipation control
US5901103A (en) * 1997-04-07 1999-05-04 Motorola, Inc. Integrated circuit having standby control for memory and method thereof
US5905682A (en) * 1997-08-22 1999-05-18 Micron Technology, Inc. Method and apparatus for biasing the substrate of an integrated circuit to an externally adjustable voltage
JP2000215696A (ja) * 1999-01-18 2000-08-04 Mitsubishi Electric Corp 半導体記憶装置および半導体テスト方法
JP2001076500A (ja) * 1999-06-28 2001-03-23 Mitsubishi Electric Corp 半導体記憶装置
JP2002216497A (ja) 2001-01-23 2002-08-02 Mitsubishi Electric Corp スタティック型半導体記憶装置
TWI265672B (en) * 2004-12-29 2006-11-01 Inventec Corp Testing device for output power source of memory
JP2008065974A (ja) * 2006-08-11 2008-03-21 Matsushita Electric Ind Co Ltd 半導体記憶装置
US8111577B2 (en) * 2007-04-17 2012-02-07 Cypress Semiconductor Corporation System comprising a state-monitoring memory element
US7907457B2 (en) * 2008-03-12 2011-03-15 Winbond Electronics Corp. Memory and voltage monitoring device thereof
US8897085B2 (en) 2012-03-19 2014-11-25 Sandisk Technologies Inc. Immunity against temporary and short power drops in non-volatile memory: pausing techniques
US9329986B2 (en) 2012-09-10 2016-05-03 Sandisk Technologies Inc. Peak current management in multi-die non-volatile memory devices
US9647476B2 (en) 2014-09-16 2017-05-09 Navitas Semiconductor Inc. Integrated bias supply, reference and bias current circuits for GaN devices
US9571093B2 (en) 2014-09-16 2017-02-14 Navitas Semiconductor, Inc. Half bridge driver circuits
US9831867B1 (en) 2016-02-22 2017-11-28 Navitas Semiconductor, Inc. Half bridge driver circuits

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JPS5589980A (en) * 1978-11-27 1980-07-08 Nec Corp Semiconductor memory unit
JPS5853775A (ja) * 1981-09-26 1983-03-30 Fujitsu Ltd Ｉｃメモリ試験方法
US4719418A (en) * 1985-02-19 1988-01-12 International Business Machines Corporation Defect leakage screen system
JPS61280095A (ja) * 1985-06-04 1986-12-10 Mitsubishi Electric Corp スタチツク形半導体記憶装置

Also Published As

Publication number Publication date
DE4022157C2 (ko) 1992-03-05
US5079744A (en) 1992-01-07
DE4022157A1 (de) 1991-01-24
JPH0346193A (ja) 1991-02-27
KR930009544B1 (ko) 1993-10-06

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