KR900017304A - Pla 회로 - Google Patents

Pla 회로 Download PDF

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Publication number
KR900017304A
KR900017304A KR1019900004613A KR900004613A KR900017304A KR 900017304 A KR900017304 A KR 900017304A KR 1019900004613 A KR1019900004613 A KR 1019900004613A KR 900004613 A KR900004613 A KR 900004613A KR 900017304 A KR900017304 A KR 900017304A
Authority
KR
South Korea
Prior art keywords
circuit
pla circuit
pla
decoder
timing
Prior art date
Application number
KR1019900004613A
Other languages
English (en)
Other versions
KR0155993B1 (ko
Inventor
다나가와 고우지
Original Assignee
고스기 노부미쓰
오끼뎅끼고오교오가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 고스기 노부미쓰, 오끼뎅끼고오교오가부시끼가이샤 filed Critical 고스기 노부미쓰
Publication of KR900017304A publication Critical patent/KR900017304A/ko
Application granted granted Critical
Publication of KR0155993B1 publication Critical patent/KR0155993B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음

Description

PLA 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예를 표시하는 PLA회로의 회로도,
제2도는 제1도의 타이밍 챠트이다.

Claims (1)

  1. 제1의 프리챠지 타이밍 중에 소정의 신호를 해독하는 디코더와, 상기 디코더로부터의 출력 신호를 제2의 프리챠지 타이밍 직전에 래치하는 래치 회로와, 소정의 타이밍 신호에서 상기 래치 회로의 출력의 도통 상태를 제어하는 게이트 회로와를, 구비한 것을 특징으로 하는 PLA 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900004613A 1989-04-06 1990-04-04 Pla 회로 KR0155993B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1989040748U JP2515853Y2 (ja) 1989-04-06 1989-04-06 ダイナミック型ｐｌａ回路
JP1-40748 1989-04-06

Publications (2)

Publication Number Publication Date
KR900017304A true KR900017304A (ko) 1990-11-16
KR0155993B1 KR0155993B1 (ko) 1998-12-15

Family

ID=12589255

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900004613A KR0155993B1 (ko) 1989-04-06 1990-04-04 Pla 회로

Country Status (5)

Country Link
US (1) US5059828A (ko)
EP (1) EP0391379B1 (ko)
JP (1) JP2515853Y2 (ko)
KR (1) KR0155993B1 (ko)
DE (1) DE69031398T2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100479361B1 (ko) * 2002-05-14 2005-03-28 학교법인 울산공업학원 차량용 차광장치

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2623979B2 (ja) * 1991-01-25 1997-06-25 日本電気株式会社 ダイナミック型論理回路
US5633830A (en) * 1995-11-08 1997-05-27 Altera Corporation Random access memory block circuitry for programmable logic array integrated circuit devices
USRE35977E (en) * 1992-05-08 1998-12-01 Altera Corporation Look up table implementation of fast carry arithmetic and exclusive-or operations
US5274581A (en) * 1992-05-08 1993-12-28 Altera Corporation Look up table implementation of fast carry for adders and counters
US5384500A (en) * 1992-05-15 1995-01-24 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes
US5331227A (en) * 1992-05-15 1994-07-19 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback line and an exclusive external input line
US5287017A (en) * 1992-05-15 1994-02-15 Micron Technology, Inc. Programmable logic device macrocell with two OR array inputs
US5300830A (en) * 1992-05-15 1994-04-05 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control
US5298803A (en) * 1992-07-15 1994-03-29 Micron Semiconductor, Inc. Programmable logic device having low power microcells with selectable registered and combinatorial output signals
JPH06176175A (ja) * 1992-12-10 1994-06-24 Rohm Co Ltd オプション設定回路及び電子機器
US5517133A (en) * 1993-07-14 1996-05-14 Sun Microsystems, Inc. Multiple-input OR-gate employing a sense amplifier
JP3400124B2 (ja) * 1994-08-08 2003-04-28 株式会社日立製作所 パストランジスタ型セレクタ回路及び論理回路
US5999019A (en) * 1997-10-10 1999-12-07 The Research Foundation Of State University Of New York Fast CMOS logic circuit with critical voltage transition logic
US6020772A (en) * 1998-02-05 2000-02-01 International Business Machines Corporation Flash output LSSD latch
US6097207A (en) * 1998-08-21 2000-08-01 International Business Machines Corporation Robust domino circuit design for high stress conditions
US6407576B1 (en) 1999-03-04 2002-06-18 Altera Corporation Interconnection and input/output resources for programmable logic integrated circuit devices
EP1076931A1 (en) 1999-03-04 2001-02-21 Altera Corporation Programmable logic device with carry-select addition
US6323680B1 (en) 1999-03-04 2001-11-27 Altera Corporation Programmable logic device configured to accommodate multiplication
US6278290B1 (en) * 1999-08-13 2001-08-21 Xilinx, Inc. Method and circuit for operating programmable logic devices during power-up and stand-by modes
KR100484247B1 (ko) * 2000-12-28 2005-04-20 매그나칩 반도체 유한회사 재설정가능 인스트럭션 세트 마이크로 컨트롤러 유니트의인스트럭션 디코더 장치
KR20040014060A (ko) * 2002-08-09 2004-02-14 삼성전자주식회사 효율적인 다이내믹 ｐｌａ 디코더
US6768335B1 (en) * 2003-01-30 2004-07-27 Xilinx, Inc. Integrated circuit multiplexer including transistors of more than one oxide thickness
US6768338B1 (en) 2003-01-30 2004-07-27 Xilinx, Inc. PLD lookup table including transistors of more than one oxide thickness
US9401364B2 (en) * 2014-09-19 2016-07-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic component, and electronic device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54111748A (en) * 1978-02-21 1979-09-01 Mitsubishi Electric Corp Programmable logic array
JPS57116431A (en) * 1981-01-10 1982-07-20 Nec Corp Programmable logic array
JPS592438A (ja) * 1982-06-28 1984-01-09 Toshiba Corp ダイナミツク型論理回路
US4488230A (en) * 1982-12-08 1984-12-11 At&T Bell Laboratories Programmed logic array with external signals introduced between its AND plane and its OR plane
US4577190A (en) * 1983-04-11 1986-03-18 At&T Bell Laboratories Programmed logic array with auxiliary pull-up means to increase precharging speed
CA1204171A (en) * 1983-07-15 1986-05-06 Stephen K. Sunter Programmable logic array
US4687959A (en) * 1986-03-27 1987-08-18 Motorola, Inc. Method and apparatus for access to a PLA
US4675556A (en) * 1986-06-09 1987-06-23 Intel Corporation Binomially-encoded finite state machine
FR2611099B1 (fr) * 1987-02-12 1993-02-12 Bull Sa Reseau logique dynamique
US4831573A (en) * 1987-03-06 1989-05-16 Altera Corporation Programmable integrated circuit micro-sequencer device
JPS63276327A (ja) * 1987-05-08 1988-11-14 Hitachi Ltd ダイナミック型ロジック・アレイ
JPS63294124A (ja) * 1987-05-27 1988-11-30 Toshiba Corp プログラマブル・ロジック・アレ−
JPH0193928A (ja) * 1987-10-05 1989-04-12 Nec Corp ダイナミック方式プログラマブルロジックアレイ
JP2541248B2 (ja) * 1987-11-20 1996-10-09 三菱電機株式会社 プログラマブル・ロジック・アレイ
US4912348A (en) * 1988-12-09 1990-03-27 Idaho Research Foundation Method for designing pass transistor asynchronous sequential circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100479361B1 (ko) * 2002-05-14 2005-03-28 학교법인 울산공업학원 차량용 차광장치

Also Published As

Publication number Publication date
US5059828A (en) 1991-10-22
EP0391379A2 (en) 1990-10-10
JP2515853Y2 (ja) 1996-10-30
KR0155993B1 (ko) 1998-12-15
EP0391379A3 (en) 1992-05-13
DE69031398D1 (de) 1997-10-16
DE69031398T2 (de) 1998-04-09
EP0391379B1 (en) 1997-09-10
JPH02133028U (ko) 1990-11-05

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