JPS54111748A - Programmable logic array - Google Patents
Programmable logic arrayInfo
- Publication number
- JPS54111748A JPS54111748A JP1948578A JP1948578A JPS54111748A JP S54111748 A JPS54111748 A JP S54111748A JP 1948578 A JP1948578 A JP 1948578A JP 1948578 A JP1948578 A JP 1948578A JP S54111748 A JPS54111748 A JP S54111748A
- Authority
- JP
- Japan
- Prior art keywords
- term
- programmable logic
- logic array
- circuits
- series
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
- H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To make small the chip size by reducing the number of elements and quickening the operation speed, through the input of timing signal is series with the OR term, in the programmable logic array constituted with AND term and OR term. CONSTITUTION:The input signals A, B, C and their inversion signals are inputted to the AND term 101 consisting of the NOR circuits 4, 5, 6, 7, and the different outputs 20S and 21S are introduced by multiplex in time sharing manner from the OR term 104 consisting of the AND and OR circuits 20 and 21. In consitituting this circuit on the semiconductor substrate, the timing signal T2 is inserted in series between the part 222 treating OR for the outputs 4S and 5S of the AND term 101 and the power supply 211, and the output line 221 is in common use with the output line of other AND OR circuit 212. Accordingly, the number of elements is reduced than the case with normal constitution and the length of wiring can be made shorter
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1948578A JPS54111748A (en) | 1978-02-21 | 1978-02-21 | Programmable logic array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1948578A JPS54111748A (en) | 1978-02-21 | 1978-02-21 | Programmable logic array |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54111748A true JPS54111748A (en) | 1979-09-01 |
Family
ID=12000644
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1948578A Pending JPS54111748A (en) | 1978-02-21 | 1978-02-21 | Programmable logic array |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54111748A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01138816A (en) * | 1987-11-26 | 1989-05-31 | Oki Electric Ind Co Ltd | Pla circuit |
JPH02133028U (en) * | 1989-04-06 | 1990-11-05 |
-
1978
- 1978-02-21 JP JP1948578A patent/JPS54111748A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01138816A (en) * | 1987-11-26 | 1989-05-31 | Oki Electric Ind Co Ltd | Pla circuit |
JPH02133028U (en) * | 1989-04-06 | 1990-11-05 |
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