JPS5495161A - False random signal generator circuit - Google Patents

False random signal generator circuit

Info

Publication number
JPS5495161A
JPS5495161A JP239678A JP239678A JPS5495161A JP S5495161 A JPS5495161 A JP S5495161A JP 239678 A JP239678 A JP 239678A JP 239678 A JP239678 A JP 239678A JP S5495161 A JPS5495161 A JP S5495161A
Authority
JP
Japan
Prior art keywords
circuit
signal
ffs
inputted
false random
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP239678A
Other languages
Japanese (ja)
Inventor
Hiroshi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP239678A priority Critical patent/JPS5495161A/en
Publication of JPS5495161A publication Critical patent/JPS5495161A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

PURPOSE:To facilitate the intergration of one chip by defining the load of a signal, which resets a circuit, as one to reduce the load and the number of wirings in the circuit which is constituted by a feedback shift register having shift function. CONSTITUTION:In the false random signal generator circuit using the feedback shift register which is constituted by FFs 2 to 6 having shift function, OR circuit 1 which constitutes an exclusive OR circuit where the output of the register is inputted and OR circuit 7 which constitutes an OR circuit where the output of circuit 1 and a reset signal are inputted are provided. In this constitution, the output of OR circuit 7 is applied to the first-stage date input of the register, and a timing pulse is applied to each of FFs 2 to 6. Then, until all of FFs 2 to 6 correspond to a reset state, the reset signal is inputted to generate false random signals, thereby reducing the load of the reset circuit and the number of signal input terminals.
JP239678A 1978-01-13 1978-01-13 False random signal generator circuit Pending JPS5495161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP239678A JPS5495161A (en) 1978-01-13 1978-01-13 False random signal generator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP239678A JPS5495161A (en) 1978-01-13 1978-01-13 False random signal generator circuit

Publications (1)

Publication Number Publication Date
JPS5495161A true JPS5495161A (en) 1979-07-27

Family

ID=11528069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP239678A Pending JPS5495161A (en) 1978-01-13 1978-01-13 False random signal generator circuit

Country Status (1)

Country Link
JP (1) JPS5495161A (en)

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