UST956003I4 - Interconnect logic for a serial processor - Google Patents

Interconnect logic for a serial processor Download PDF

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Publication number
UST956003I4
UST956003I4 US05/695,675 US69567576A UST956003I4 US T956003 I4 UST956003 I4 US T956003I4 US 69567576 A US69567576 A US 69567576A US T956003 I4 UST956003 I4 US T956003I4
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US
United States
Prior art keywords
inputs
gates
control unit
main control
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US05/695,675
Inventor
Richard B. Simone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Priority to US05/695,675 priority Critical patent/UST956003I4/en
Application granted granted Critical
Publication of UST956003I4 publication Critical patent/UST956003I4/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems

Abstract

the interconnect logic between a main control unit and the data handling register of a serial processor is formed of a programmable logic array (PLA). The serial processor includes a main control unit, a plurality of registers and PLA interconnect logic. The interconnect logic decodes and implements instructions supplied from the main control unit to control the flow of data into and out of the serial registers. The interconnect logic includes a plurality of input terminals I1 -Im ; D1 -Dn and a plurality of output terminals A-N. The input lines are connected to a plurality of lines directly and to another plurality of lines indirectly through inverters. A plurality of AND gates 34 are provided with their inputs connected to various ones of the lines. The outputs of the AND gates are connected to various ones of the inputs to the OR gate 36. If the PLA is made in integrated circuit technology, the selected connections are mask options which are represented in the drawing by an X at each of the connections.
The input terminals I1 -Im are adapted to receive instructions from the main control unit. The input terminals D1 -Dn are adapted to receive the outputs of respective ones of the general registers. Accordingly, selected inputs from the instructions supplied by the main control unit are their complements as provided by the inverters and selected inputs from the registers and their complements as provided by the inverters may be connected by mask options to the inputs of any one of the AND gates 34. The output of the AND gates form partial product terms. Selected ones of the partial product terms may therefore be connected by mask options to the inputs of any one of the OR gates 36 to form outputs on the output terminal 20. Thus, the circuit can be used to transfer data between registers and to recirculate data within a register.
US05/695,675 1975-06-06 1976-06-14 Interconnect logic for a serial processor Pending UST956003I4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US05/695,675 UST956003I4 (en) 1975-06-06 1976-06-14 Interconnect logic for a serial processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58463775A 1975-06-06 1975-06-06
US05/695,675 UST956003I4 (en) 1975-06-06 1976-06-14 Interconnect logic for a serial processor

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US58463775A Continuation 1975-06-06 1975-06-06

Publications (1)

Publication Number Publication Date
UST956003I4 true UST956003I4 (en) 1977-03-01

Family

ID=27079159

Family Applications (1)

Application Number Title Priority Date Filing Date
US05/695,675 Pending UST956003I4 (en) 1975-06-06 1976-06-14 Interconnect logic for a serial processor

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US (1) UST956003I4 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4286330A (en) 1976-04-07 1981-08-25 Isaacson Joel D Autonomic string-manipulation system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4286330A (en) 1976-04-07 1981-08-25 Isaacson Joel D Autonomic string-manipulation system

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