KR900000769A - 테스트 용이화회로 - Google Patents

테스트 용이화회로

Info

Publication number
KR900000769A
KR900000769A KR1019890008564A KR890008564A KR900000769A KR 900000769 A KR900000769 A KR 900000769A KR 1019890008564 A KR1019890008564 A KR 1019890008564A KR 890008564 A KR890008564 A KR 890008564A KR 900000769 A KR900000769 A KR 900000769A
Authority
KR
South Korea
Prior art keywords
circuit blocks
circuit
output
input
analyzed
Prior art date
Application number
KR1019890008564A
Other languages
English (en)
Other versions
KR920003473B1 (ko
Inventor
야스유키 노즈야마
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR900000769A publication Critical patent/KR900000769A/ko
Application granted granted Critical
Publication of KR920003473B1 publication Critical patent/KR920003473B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

내용 없음.

Description

테스트 용이화회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 따른 테스트용이화회로의 구성을 나타낸 도면.
제2도는 제1도에 도시된 회로의 동작을 나타낸 타이밍챠트.

Claims (1)

  1. 마이크로명령에 의해 제어되는 회로블럭(1,3)의 해석에 필요한 마이크로명령형식의 제어정보가 세트되는 격납수단(31,33)과, 이 격납수단(31,33)으로부터 독출되는 제어정보를 무효화 및 유효화하는 마스크수단(37), 이 마스크수단(37)에 의해 유효화된 제어정보를 디코드해서 상기 회로블럭(1,3)의 해석시에 해당 회로블럭(1,3)의 동작지령으로 되는 디코드출력을 상기 회로블럭(1,3)에 공급하는 디코드수단(35), 상기 회로블럭(1,3)의 해석시에 해당 회로블럭(1,3)과 외부회로부간의 데이터입출력을 가능하게 하는 입출력수단(11) 및, 상기 회로블럭(1,3)의 해석시에 상기 입출력수단(11)을 통해 소정의 해석시퀀스를 실행하여 데이터의 입출력상태 및 상기 마스크수단(37)을 외부로부터 인가되는 제어신호에 따라 제어하는 제어수단(21,39)을 구비하여 구성된 것을 특징으로 하는 테스트용이화회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890008564A 1988-06-22 1989-06-21 테스트 용이화회로 KR920003473B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP63154015A JPH01320544A (ja) 1988-06-22 1988-06-22 テスト容易化回路
JP63-154015 1988-06-22
JP88-154015 1988-06-22

Publications (2)

Publication Number Publication Date
KR900000769A true KR900000769A (ko) 1990-01-31
KR920003473B1 KR920003473B1 (ko) 1992-05-01

Family

ID=15575045

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890008564A KR920003473B1 (ko) 1988-06-22 1989-06-21 테스트 용이화회로

Country Status (5)

Country Link
US (1) US5398250A (ko)
EP (1) EP0347905B1 (ko)
JP (1) JPH01320544A (ko)
KR (1) KR920003473B1 (ko)
DE (1) DE68924304T2 (ko)

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JPH0682325B2 (ja) * 1990-05-29 1994-10-19 株式会社東芝 情報処理装置のテスト容易化回路
JP2806075B2 (ja) * 1991-06-06 1998-09-30 日本電気株式会社 マイクロコンピュータ
JPH05233352A (ja) * 1992-02-19 1993-09-10 Nec Corp マイクロプロセッサ
US5869979A (en) * 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US5764655A (en) * 1997-07-02 1998-06-09 International Business Machines Corporation Built in self test with memory
US6230290B1 (en) 1997-07-02 2001-05-08 International Business Machines Corporation Method of self programmed built in self test
US6108798A (en) * 1997-07-02 2000-08-22 International Business Machines Corporation Self programmed built in self test
US5936976A (en) * 1997-07-25 1999-08-10 Vlsi Technology, Inc. Selecting a test data input bus to supply test data to logical blocks within an integrated circuit
US6185712B1 (en) 1998-07-02 2001-02-06 International Business Machines Corporation Chip performance optimization with self programmed built in self test
US6643800B1 (en) * 2000-02-02 2003-11-04 Hewlett-Packard Development Company, L.P. Method and apparatus for testing microarchitectural features by using tests written in microcode
JP4228061B2 (ja) * 2000-12-07 2009-02-25 富士通マイクロエレクトロニクス株式会社 集積回路の試験装置および試験方法
US6573862B2 (en) * 2000-12-12 2003-06-03 Harris Corporation Phased array antenna including element control device providing fault detection and related methods
JP2007101395A (ja) * 2005-10-05 2007-04-19 Sony Corp 回路装置の検査装置、検査方法及び製造方法
US8365029B2 (en) * 2007-12-26 2013-01-29 Infineon Technologies Ag Digital circuits and methods for testing a digital circuit

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3603936A (en) * 1969-12-08 1971-09-07 Ibm Microprogrammed data processing system
US3786434A (en) * 1972-12-20 1974-01-15 Ibm Full capacity small size microprogrammed control unit
US4212059A (en) * 1977-03-14 1980-07-08 Tokyo Shibaura Electric Co., Ltd. Information processing system
US4313200A (en) * 1978-08-28 1982-01-26 Takeda Riken Kogyo Kabushikikaisha Logic test system permitting test pattern changes without dummy cycles
US4342084A (en) * 1980-08-11 1982-07-27 International Business Machines Corporation Main storage validation means
JPS58146834A (ja) * 1982-02-24 1983-09-01 Sumitomo Metal Ind Ltd 炉体耐火物状態の推定方法
JPS59216249A (ja) * 1983-05-23 1984-12-06 Toshiba Corp 集積回路装置
EP0126785B1 (de) * 1983-05-25 1989-03-08 Ibm Deutschland Gmbh Prüf- und Diagnoseeinrichtung für Digitalrechner
DE3373729D1 (en) * 1983-12-08 1987-10-22 Ibm Deutschland Testing and diagnostic device for a digital calculator
JPH0668732B2 (ja) * 1984-11-21 1994-08-31 株式会社日立製作所 情報処理装置のスキヤン方式
IT1184054B (it) * 1985-03-25 1987-10-22 Cselt Centro Studi Lab Telecom Unita di controllo di microprogramma autocollaudante con rilevazione in linea degli errori in tecnologia mos
US4720811A (en) * 1985-04-26 1988-01-19 Hitachi, Ltd. Microprocessor capable of stopping its operation at any cycle time
US4920538A (en) * 1985-06-28 1990-04-24 International Business Machines Corporation Method of checking the execution of microcode sequences
US4710927A (en) * 1986-07-24 1987-12-01 Integrated Device Technology, Inc. Diagnostic circuit
US4811345A (en) * 1986-12-16 1989-03-07 Advanced Micro Devices, Inc. Methods and apparatus for providing a user oriented microprocessor test interface for a complex, single chip, general purpose central processing unit
JPS63193237A (ja) * 1987-02-06 1988-08-10 Toshiba Corp 半導体集積回路装置
JPH0743672B2 (ja) * 1987-02-18 1995-05-15 株式会社東芝 メモリ保護違反検出装置
US5043985A (en) * 1987-05-05 1991-08-27 Industrial Technology Research Institute Integrated circuit testing arrangement
JP2513762B2 (ja) * 1988-01-29 1996-07-03 株式会社東芝 論理回路

Also Published As

Publication number Publication date
DE68924304D1 (de) 1995-10-26
EP0347905B1 (en) 1995-09-20
US5398250A (en) 1995-03-14
EP0347905A2 (en) 1989-12-27
DE68924304T2 (de) 1996-04-04
JPH01320544A (ja) 1989-12-26
EP0347905A3 (en) 1991-06-12
KR920003473B1 (ko) 1992-05-01

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