KR910008565A - 분기 제어 회로 - Google Patents
분기 제어 회로 Download PDFInfo
- Publication number
- KR910008565A KR910008565A KR1019900016351A KR900016351A KR910008565A KR 910008565 A KR910008565 A KR 910008565A KR 1019900016351 A KR1019900016351 A KR 1019900016351A KR 900016351 A KR900016351 A KR 900016351A KR 910008565 A KR910008565 A KR 910008565A
- Authority
- KR
- South Korea
- Prior art keywords
- instruction
- branch
- control circuit
- branch control
- succeeds
- Prior art date
Links
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 이 발명의 회로에 쓰이는 각형의 상대 분기 명령 포맷도.
제4도는 제1도의 부디코더 회로의 상세도.
제5도는 제4도의 각 분기 예측 정보, 폐치의 각 비트 상태와 선택기 출력의 관계를 도시한 도면.
Claims (1)
- 파이프 라인 방식에 의하여 분기 명령을 포함하는 명령을 처리하는 데이타 처리 장치에 있어서, 명령 페치단에서 명령 버퍼(101)로 입려되는 명령군 중 단축형인 상대 분기 명령을 처리하는 동시에, 상기 명령내에 포함된 분기 정보에서 분기가 성공된다고 예측된 경우에, 그 분기선 어드레스를 성공하는 부디코더 회로(102), 및 상기 명령군 중 일반형인 상대 분기 명령을 처리하는 동시에 상기 명령 내에 포함되어 있는 분기 정보에서 분기가 성공한다고 예측된 경우에, 그 분기선 어드레스를 생성하는 주디코더 회로(103)을 구비하는 것을 특징으로 하는 분기 제어 회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1266158A JPH0650465B2 (ja) | 1989-10-16 | 1989-10-16 | 分岐制御回路 |
JP1-266158 | 1989-10-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910008565A true KR910008565A (ko) | 1991-05-31 |
KR930005769B1 KR930005769B1 (ko) | 1993-06-24 |
Family
ID=17427093
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900016351A KR930005769B1 (ko) | 1989-10-16 | 1990-10-15 | 분기 제어회로 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5295248A (ko) |
EP (1) | EP0423726B1 (ko) |
JP (1) | JPH0650465B2 (ko) |
KR (1) | KR930005769B1 (ko) |
DE (1) | DE69032463T2 (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2761688B2 (ja) * | 1992-02-07 | 1998-06-04 | 三菱電機株式会社 | データ処理装置 |
JP3345787B2 (ja) * | 1993-04-13 | 2002-11-18 | 三菱電機株式会社 | データ処理装置 |
JPH09500989A (ja) * | 1993-05-14 | 1997-01-28 | インテル・コーポレーション | 分岐ターゲット・バッファにおける推論履歴 |
US5724565A (en) * | 1995-02-03 | 1998-03-03 | International Business Machines Corporation | Method and system for processing first and second sets of instructions by first and second types of processing systems |
JP3760041B2 (ja) * | 1996-12-09 | 2006-03-29 | 松下電器産業株式会社 | 分岐予測する情報処理装置 |
US5974538A (en) * | 1997-02-21 | 1999-10-26 | Wilmot, Ii; Richard Byron | Method and apparatus for annotating operands in a computer system with source instruction identifiers |
US6134649A (en) * | 1997-11-17 | 2000-10-17 | Advanced Micro Devices, Inc. | Control transfer indication in predecode which identifies control transfer instruction and an alternate feature of an instruction |
US6167506A (en) * | 1997-11-17 | 2000-12-26 | Advanced Micro Devices, Inc. | Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location |
US6061786A (en) * | 1998-04-23 | 2000-05-09 | Advanced Micro Devices, Inc. | Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction |
EP0953898A3 (en) * | 1998-04-28 | 2003-03-26 | Matsushita Electric Industrial Co., Ltd. | A processor for executing Instructions from memory according to a program counter, and a compiler, an assembler, a linker and a debugger for such a processor |
US6237087B1 (en) * | 1998-09-30 | 2001-05-22 | Intel Corporation | Method and apparatus for speeding sequential access of a set-associative cache |
JP2001273138A (ja) * | 2000-03-24 | 2001-10-05 | Fujitsu Ltd | プログラム変換装置および方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3764988A (en) * | 1971-03-01 | 1973-10-09 | Hitachi Ltd | Instruction processing device using advanced control system |
JPS5848144A (ja) * | 1981-09-16 | 1983-03-22 | Nec Corp | デ−タ処理装置の分岐命令制御方式 |
US4991080A (en) * | 1986-03-13 | 1991-02-05 | International Business Machines Corporation | Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions |
GB8728493D0 (en) * | 1987-12-05 | 1988-01-13 | Int Computers Ltd | Jump prediction |
JPH02287626A (ja) * | 1989-04-28 | 1990-11-27 | Toshiba Corp | パイプライン方式の分岐命令制御装置 |
-
1989
- 1989-10-16 JP JP1266158A patent/JPH0650465B2/ja not_active Expired - Fee Related
-
1990
- 1990-10-15 US US07/597,319 patent/US5295248A/en not_active Expired - Lifetime
- 1990-10-15 KR KR1019900016351A patent/KR930005769B1/ko not_active IP Right Cessation
- 1990-10-16 EP EP90119840A patent/EP0423726B1/en not_active Expired - Lifetime
- 1990-10-16 DE DE69032463T patent/DE69032463T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5295248A (en) | 1994-03-15 |
EP0423726A3 (en) | 1992-09-16 |
EP0423726A2 (en) | 1991-04-24 |
DE69032463T2 (de) | 1998-12-17 |
JPH03129432A (ja) | 1991-06-03 |
JPH0650465B2 (ja) | 1994-06-29 |
DE69032463D1 (de) | 1998-08-13 |
KR930005769B1 (ko) | 1993-06-24 |
EP0423726B1 (en) | 1998-07-08 |
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