KR900011038A - T형 게이트 형상을 가진 자기정합 mesfet의 제조방법 - Google Patents

T형 게이트 형상을 가진 자기정합 mesfet의 제조방법 Download PDF

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KR900011038A
KR900011038A KR1019880015986A KR880015986A KR900011038A KR 900011038 A KR900011038 A KR 900011038A KR 1019880015986 A KR1019880015986 A KR 1019880015986A KR 880015986 A KR880015986 A KR 880015986A KR 900011038 A KR900011038 A KR 900011038A
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thin film
silicon
film
tungsten
silicon nitride
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KR1019880015986A
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KR910006702B1 (ko
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박형무
김동구
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경상현
재단법인 한국전자통신연구소
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Priority to KR1019880015986A priority Critical patent/KR910006702B1/ko
Priority to US07/443,750 priority patent/US4929567A/en
Priority to DE3939635A priority patent/DE3939635A1/de
Priority to JP1310806A priority patent/JPH0620081B2/ja
Priority to FR8915925A priority patent/FR2640079B1/fr
Publication of KR900011038A publication Critical patent/KR900011038A/ko
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Publication of KR910006702B1 publication Critical patent/KR910006702B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28581—Deposition of Schottky electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음

Description

T형 게이트 형상을 가진 자기정합 MESFET의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도는 n층 이온 주입 공정도, 제1B도는 질화 규소막 부식 공정도, 제1C도는 텅스텐의 선택적 화학 증착도, 제1D도는 n+층 이온 주입 공정도, 제1E도는 소자간 분리 공정도, 제1F는 SiN4와 Si부식 공정 및 저항 금속 증착 공정도, 제1G는 완성된 T형 게이트의 단면도.

Claims (4)

  1. PECVD방법에 의한 실리콘(Si)박막과 PCVD방법에 의한 질화 규소(Si3N4)막을 이용한 이온주입 공정, 게이트 전극 형성을 위해 포토레지스트를 마스크로 하여 상기 질화 규소막을 부식하여 게이트 전극패턴을 형성하는 공정, 상기 질화 규소막에는 텅스텐이 증착 되지 않도록 하고 노출된 실리콘 박막상에만 텅스텐을 선택적으로 증착시키기 위해 실리콘 박막을 이용한 게이트 전극 텅스텐의 선택적 화학 증착 공정, 상기 텅스텐 게이트 전극이 "T"형으로 형성되도록 성장시키는 화학 중착 공정, 상기 T형 텅스텐 게이트를 이용하여 게이트 전극과 주입될 n+층의 간격을 1000내지 2000Å으로 되도록 형성하는 n+층 이온 주입 공정, 상기 이온 주입 공정에 이용된 실리콘 박막과 질화 규소막을 이용한 n층과 n+층의 활성화 공정, 소자간을 분리하기 위하여 분리용 포토레지스트를 마스크로 하여 실리콘 박막과 질화규소막을 통해 B+또는 H+이온을 100 내지 200kev조건으로 이온 주입하는 공정, 소오스와 드레인을 형성하기 위해 포토레지스트를 마스크로 하여 실리콘 박막과 질화규소막을 부식히고, 저항금속(AuGe/Ni)을 증착한 후, 리프트 오프(lift-off)시킴으로써 소오스와 드레인 전극을 형성하는 공정으로 구성되는 것을 특징으로 하는 T형 게이트 형상을 가진 자기정합 MESFET의 제조방법.
  2. 제1항에 있어서, 텅스텐의 선택적 화학 증착공정은 기판 온도를 350 내지 450℃로 하고, 반응 압력을 0.2 내지 1 Torr로 하고, WF6와 아르곤(Ar) 가스의 흐름속도를 각각 5 내지 10 sccm, 1000sccm 으로 하여 이루어지는 것을 특징으로 하는 자기정합 MESFET의 제조방법.
  3. 제1항에 있어서, 이온 주입 공정을 위해 이용된 실리콘 박막과 질화규소막의 두께는 각각 100 내지 200Å 및 1000Å으로 하여 이루어진 것을 특징으로 하는 자기정합 MESFET의 제조방법.
  4. 제1항에 있어서, T형으로 성장시키는 화학 증착 공정은 기판온도를 350 내지 450℃로 하고, 반응 압력을 0.6 내지 2Torr로 하고, WF6, H2, Ar가스의 흐름속도를 각각 5 내지 10sccm, 100 내지 500sccm, 1000sccm으로 하여 형성하는 것을 특징으로 하는 자기정합 MESFET의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880015986A 1988-12-01 1988-12-01 T형 게이트 형상을 가진 자기 정합 mesfet의 제조방법 KR910006702B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019880015986A KR910006702B1 (ko) 1988-12-01 1988-12-01 T형 게이트 형상을 가진 자기 정합 mesfet의 제조방법
US07/443,750 US4929567A (en) 1988-12-01 1989-11-30 Method of manufacturing a self-aligned GaAs MESFET with T type tungsten gate
DE3939635A DE3939635A1 (de) 1988-12-01 1989-11-30 Verfahren zur herstellung eines sich selbst ausrichtenden gaas-mesfet mit t-foermigen wolfram-gatter
JP1310806A JPH0620081B2 (ja) 1988-12-01 1989-12-01 Ｔ型ゲート形状を有する自己整合ｍｅｓｆｅｔの製造方法
FR8915925A FR2640079B1 (fr) 1988-12-01 1989-12-01 Methode fabrication d'un transistor auto-aligne a semi-conducteur metallique (gaas) a effet de champ pourvu d'une grille en tungstene du type t

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Application Number Priority Date Filing Date Title
KR1019880015986A KR910006702B1 (ko) 1988-12-01 1988-12-01 T형 게이트 형상을 가진 자기 정합 mesfet의 제조방법

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US (1) US4929567A (ko)
JP (1) JPH0620081B2 (ko)
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DE (1) DE3939635A1 (ko)
FR (1) FR2640079B1 (ko)

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KR0130963B1 (ko) * 1992-06-09 1998-04-14 구자홍 T형 단면구조의 게이트 금속전극을 갖는 전계효과 트랜지스터의 제조방법
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DE19983773T1 (de) * 1998-12-07 2002-03-28 Intel Corp Transistor mit eingekerbtem Gate
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KR100299386B1 (ko) 1998-12-28 2001-11-02 박종섭 반도체 소자의 게이트 전극 형성방법
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US6797586B2 (en) * 2001-06-28 2004-09-28 Koninklijke Philips Electronics N.V. Silicon carbide schottky barrier diode and method of making
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KR101140285B1 (ko) * 2010-01-29 2012-04-27 서울대학교산학협력단 멀티 스텝형 티 게이트 제조방법
US8736276B2 (en) * 2011-06-20 2014-05-27 General Electric Company Ripple spring and diagnostic method therefor
KR102173638B1 (ko) 2014-10-01 2020-11-04 삼성전자주식회사 반도체 소자 및 그 형성방법
KR102097714B1 (ko) 2019-11-05 2020-04-06 곽성근 맥섬석 과립을 이용한 원적외선과 음이온 방사 실리콘 고무 조성물 및 그 제조 방법

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Also Published As

Publication number Publication date
JPH0620081B2 (ja) 1994-03-16
US4929567A (en) 1990-05-29
KR910006702B1 (ko) 1991-08-31
DE3939635C2 (ko) 1993-09-23
FR2640079B1 (fr) 1995-11-10
FR2640079A1 (fr) 1990-06-08
DE3939635A1 (de) 1990-06-07
JPH02192127A (ja) 1990-07-27

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