KR890012402A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

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Publication number
KR890012402A
KR890012402A KR1019890000787A KR890000787A KR890012402A KR 890012402 A KR890012402 A KR 890012402A KR 1019890000787 A KR1019890000787 A KR 1019890000787A KR 890000787 A KR890000787 A KR 890000787A KR 890012402 A KR890012402 A KR 890012402A
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South Korea
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layer
mask
silicon
semiconductor device
manufacturing
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KR1019890000787A
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English (en)
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오신스키 카지미에르쯔
부르스 인그리드
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이반 밀러 레르너
엔.브이.필립스 글로아이람펜파브리켄
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Publication of KR890012402A publication Critical patent/KR890012402A/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/147Silicides

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음.

Description

반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 3도는 본 발명에 따른 방법에 의해 얻어진 반도체 장치 제조의 몇가지 연속적인 단계의 단면도 및 개략도.

Claims (5)

  1. 단결정 실리콘의 반도체 기판면은 실리콘 산화물층에 제공되며 게이트 전극은 에칭처리를 받아들여 제공된 에칭 마스크후에, 도프된 다결정 실리콘의 층과 함께 실리콘 산화물 층으로 덮힌 것에 의해 형성되며, 마스크처럼 게이트 전극으로 사용되는 반면에, 소스 및 드레인 죤은 반도체 기판에서 형성되며 게이트 전극은 비등방성 에칭 처리를 받아들이고 실리콘 산화물의 층과 함께 면을 덮는 것에 의해 엣지 절연부분에 제공되며, 상기 게이트 전극의 다결정 실리콘 및 상기 소스 및 드레인 죤의 단결정 실리콘은 노출되며, 상기 면은 금속 합금층으로 덮혀 있으며, 상기 기판은 단결정 및 다결정 실리콘 금속 규화물 밑에 형성된 것과 함께 금속 합금층의 반작용에 의해 열처리를 받아들이며, 금속 규화물로 변환되지 않는 금속 합금층의 부분이 변환되는 절연 게이트 필드 효과 트랜지스터를 구비하는 반도체 장치 제조방법에 있어서, 상기 다결정 실리콘층에서 게이트 전극의 형성동안에 에칭 마스크처럼 사용된 실리콘 질화물 포함 마스크를 특징으로 하는 반도체 장치의 제조방법.
  2. 제 1 항에 있어서, 상기 실리콘 질화물 포함 에칭 마스크는 상기 소스 및 드레인 죤이 형성된 후에 오직 제거되는 것을 특징으로하는 반도체 장치의 제조방법.
  3. 제 1 항 또는 2항에 있어서, 상기 실리콘 질화물의 마스크는 실리콘 질화물 포함 마스크처럼 사용되는 것을 특징으로 하는 반도체 장치의 제조방법.
  4. 제 3 항 있어서, 에칭 처리에 의한 마스크와, 감광성 내식막 마스크에 의해 마스킹되는 반면에 거기에서 형성된 것과 실리콘 질화물층과 함께 다결정 실리콘층에 덮힌 것에 의해 형성된 실리콘 질화물의 마스크를 특징으로 하는 반도체 장치의 제조방법.
  5. 제 4항에 있어서, 실리콘 산화물의 층은 다결정 실리콘층과 실리콘 질화물의 층 사이에 제공되는 것을 특징으로 하는 반도체 장치의 제조방법.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890000787A 1988-01-29 1989-01-26 반도체 장치의 제조방법 KR890012402A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8800222A NL8800222A (nl) 1988-01-29 1988-01-29 Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op zelfregistrerende wijze metaalsilicide wordt aangebracht.
NL8800222 1988-01-29

Publications (1)

Publication Number Publication Date
KR890012402A true KR890012402A (ko) 1989-08-26

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Application Number Title Priority Date Filing Date
KR1019890000787A KR890012402A (ko) 1988-01-29 1989-01-26 반도체 장치의 제조방법

Country Status (6)

Country Link
US (1) US4885259A (ko)
EP (1) EP0327152B1 (ko)
JP (1) JPH025435A (ko)
KR (1) KR890012402A (ko)
DE (1) DE68910841T2 (ko)
NL (1) NL8800222A (ko)

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Also Published As

Publication number Publication date
EP0327152B1 (en) 1993-11-24
NL8800222A (nl) 1989-08-16
JPH025435A (ja) 1990-01-10
DE68910841T2 (de) 1994-05-19
US4885259A (en) 1989-12-05
DE68910841D1 (de) 1994-01-05
EP0327152A1 (en) 1989-08-09

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