KR890008957A - 절연장벽의 형성방법 - Google Patents

절연장벽의 형성방법 Download PDF

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KR890008957A
KR890008957A KR1019880015052A KR880015052A KR890008957A KR 890008957 A KR890008957 A KR 890008957A KR 1019880015052 A KR1019880015052 A KR 1019880015052A KR 880015052 A KR880015052 A KR 880015052A KR 890008957 A KR890008957 A KR 890008957A
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layer
trench
substrate
forming
opening
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KR1019880015052A
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지.나지 앤드류
제이.매톡스 로버트
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빈센트 죠셉 로너
모토로라 인코포레이티드
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Publication of KR890008957A publication Critical patent/KR890008957A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Weting (AREA)

Abstract

내용 없음

Description

절연장벽의 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1∼3도는 본 발명에 따른 다양한 공정단계동안에, 반도체 소자의 절연장벽 부분에 대한 간략화된 도식적 단면도.

Claims (3)

  1. 반도체 소자에서 절연장벽을 형성하는 방법에 있어서, 주 표면을 가지는 반도체 기판을 공급하고, 주 표면상에 절연층을 형성하고, 절연층상에 다결정 반도체층을 형성하고, 다결정층상에 개구를 가지는 마스크층을 형성하고, 다결정층 및 절연층 및 개구의 아랫부분의 기판부분을 제거하여 다결정층 및 절연층을 통해 기판내로 확장하는 트랜치를 형성하고, 실리콘 질산화물을 포함하는 제1물질을 트랜치 내에 용착시켜 최소한 다결정층으로 트랜치를 채우며, 다결정층위의 제1물질을 제거하며 트랜치에서 제1물질의 제1상부표면을 노출시키고, 트랜치내의 제1물질을 에칭 용매에 노출시키고, 트랜치내의 제1물질에서 형성된 캡을 다결정층위로 확장하는 실리콘 질화물을 포함하는 제2물질로 채우고, 제2물질을 에칭하여, 다결정층 및, 캡에서 제1물질의 제1상부 표면 및 제2물질의 제2상부 표면을 노출시키며, 다결정층을 제거하는 것으로 이루어지는 것을 특징으로 하는 절연장벽의 형성 방법.
  2. 반도체 기판내로 확장하며, 절연물로 채워진 트랜치를 형성하는 방법에 있어서, 주 표면을 가지는 반도체 기판을 공급하고, 기판의 표면상에 제1층을 형성하는데 상기 제1층은 기판에 대채 차별적으로 에칭기능하고, 제1층상에 제2층을 형성하는데, 제2층은 제1층에 대해 차별적으로 에칭 가능하고, 제2층 위로 마스크 물질을 공급하며 제2층으로 확장하는 제2개구를 형성하고, 제1개구를 통하여, 제1층 및 제1층의 하부를 에칭하여 기판의 하부를 노출시키고, 가판의 하부를 에칭하여 기판내로 확장하는 트랜치를 형성하고, 제2층 위로 확장하는 제3층을 트랜치내에 용착시키는데 제3층은 제2층에 대해 차별적으로 에칭가능하고, 트랜치내의 제3층의 일부를 남기고, 제2층 위로 확장하는 제3층을 제거하고, 트랜치내의 제3층으로 부분적으로 확장하는 제2개구를 형성하고, 제2층에 대해 차별적으로 에칭 가능하며 제2층 위로 확장하는 제4층으로 제2개구를 채우고, 제2개구에 제4층을 남기는 반면 제2층 위의 제4층을 제거하며, 제2층을 제거하는 것으로 이루어지는 것을 특징으로 하는 절연물로 채워진 트랜치 형성 방법.
  3. 반도체 장치에서 절연물로 채워진 트랜치를 형성하는 방법에 있어서, 주 표면을 가지는 기판을 공급하고, 주 표면에 에칭-중지층을 인가하고, 에칭-중지층에 마스크층을 인가하고, 에칭-중지층으로 확장하는 개구를 공급하기 위해 마스크층을 패턴화 시키고, 마스크층의 개구를 통해, 에칭-중지층의 하부를 제거하고, 에칭-중지층의 개구를 통해 기판의 일부를 제거하여 기판에서 트랜치를 형성하고, 트랜치내의 제1부분 및 주 표면 위로 확장하는 제2부분을 가지는 질산화물 절연물로 트랜치를 채우고, 질산화물층의 제1부분을 남기고 질산화물층의 제2부분을 제거하는데, 제1부분은 주 표면 위에 위치하는 노출된 표면을 가지며, 질산화물의 제1부분의 표면을 에칭 용매에 노출시키고, 상술한 단계에 의해, 캡에서의 제1부분 및 주 표면 위로 확장하는 제2부분을 가지며 질화물로, 질산화물의 제1부분에서 에칭된 캡을 채우며, 질산화물층의 제1부분을 제거하고, 에칭-중지층을 제거하는 것으로 이루어지는 것을 특징으로 하는 절연물로 채워진 트랜치 형성 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880015052A 1987-11-17 1988-11-16 절연장벽의 형성방법 KR890008957A (ko)

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US122,094 1987-11-17
US07/122,094 US4791073A (en) 1987-11-17 1987-11-17 Trench isolation method for semiconductor devices

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Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4960727A (en) * 1987-11-17 1990-10-02 Motorola, Inc. Method for forming a dielectric filled trench
US4982263A (en) * 1987-12-21 1991-01-01 Texas Instruments Incorporated Anodizable strain layer for SOI semiconductor structures
US5416354A (en) * 1989-01-06 1995-05-16 Unitrode Corporation Inverted epitaxial process semiconductor devices
US5017999A (en) * 1989-06-30 1991-05-21 Honeywell Inc. Method for forming variable width isolation structures
US6068784A (en) * 1989-10-03 2000-05-30 Applied Materials, Inc. Process used in an RF coupled plasma reactor
US5556501A (en) * 1989-10-03 1996-09-17 Applied Materials, Inc. Silicon scavenger in an inductively coupled RF plasma reactor
JP2932552B2 (ja) * 1989-12-29 1999-08-09 日本電気株式会社 半導体装置及びその製造方法
US5094972A (en) * 1990-06-14 1992-03-10 National Semiconductor Corp. Means of planarizing integrated circuits with fully recessed isolation dielectric
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
US5177028A (en) * 1991-10-22 1993-01-05 Micron Technology, Inc. Trench isolation method having a double polysilicon gate formed on mesas
US5190889A (en) * 1991-12-09 1993-03-02 Motorola, Inc. Method of forming trench isolation structure with germanium silicate filling
US5254873A (en) * 1991-12-09 1993-10-19 Motorola, Inc. Trench structure having a germanium silicate region
US5425845A (en) * 1993-06-09 1995-06-20 Texas Instruments Incorporated Method for selective removal of hard trench masks
US5387540A (en) * 1993-09-30 1995-02-07 Motorola Inc. Method of forming trench isolation structure in an integrated circuit
US6083852A (en) 1997-05-07 2000-07-04 Applied Materials, Inc. Method for applying films using reduced deposition rates
US6127262A (en) * 1996-06-28 2000-10-03 Applied Materials, Inc. Method and apparatus for depositing an etch stop layer
US5804490A (en) * 1997-04-14 1998-09-08 International Business Machines Corporation Method of filling shallow trenches
US6146970A (en) * 1998-05-26 2000-11-14 Motorola Inc. Capped shallow trench isolation and method of formation
US6001704A (en) * 1998-06-04 1999-12-14 Vanguard International Semiconductor Corporation Method of fabricating a shallow trench isolation by using oxide/oxynitride layers
US6599812B1 (en) * 1998-10-23 2003-07-29 Stmicroelectronics S.R.L. Manufacturing method for a thick oxide layer
KR100308793B1 (ko) * 1999-10-18 2001-11-02 윤종용 반도체 소자 제조방법
JP2002198525A (ja) 2000-12-27 2002-07-12 Toshiba Corp 半導体装置及びその製造方法
DE10138510B4 (de) * 2001-08-06 2006-08-10 Infineon Technologies Ag Grabenisolation mit selbstjustierender Oberflächenversiegelung und Verfahren zur Herstellung einer solchen Grabenisolation
DE10145724A1 (de) 2001-09-17 2003-04-10 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterstruktur unter Verwendung einer Schutzschicht und Halbleiterstruktur
ITTO20011038A1 (it) * 2001-10-30 2003-04-30 St Microelectronics Srl Procedimento per la fabbricazione di una fetta semiconduttrice integrante dispositivi elettronici e una struttura per il disaccoppiamento el
US20050023631A1 (en) * 2003-07-31 2005-02-03 Varghese Ronnie P. Controlled dry etch of a film
US7396769B2 (en) * 2004-08-02 2008-07-08 Lam Research Corporation Method for stripping photoresist from etched wafer
US8187481B1 (en) * 2005-05-05 2012-05-29 Coho Holdings, Llc Random texture anti-reflection optical surface treatment
US7442584B2 (en) * 2005-11-21 2008-10-28 Stmicroelectronics, Inc. Isolated vertical power device structure with both N-doped and P-doped trenches
US8124516B2 (en) * 2006-08-21 2012-02-28 Lam Research Corporation Trilayer resist organic layer etch
US8030215B1 (en) * 2008-02-19 2011-10-04 Marvell International Ltd. Method for creating ultra-high-density holes and metallization
FR2979750A1 (fr) * 2011-09-07 2013-03-08 St Microelectronics Crolles 2 Procede de realisation d'une tranchee d'isolation
US11120997B2 (en) * 2018-08-31 2021-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Surface treatment for etch tuning

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4307180A (en) * 1980-08-22 1981-12-22 International Business Machines Corp. Process of forming recessed dielectric regions in a monocrystalline silicon substrate
JPS5864044A (ja) * 1981-10-14 1983-04-16 Toshiba Corp 半導体装置の製造方法
JPS593946A (ja) * 1982-06-29 1984-01-10 Fujitsu Ltd 半導体装置の製造方法
JPS59182538A (ja) * 1983-04-01 1984-10-17 Hitachi Ltd 半導体装置およびその製造方法
JPS59193044A (ja) * 1983-04-15 1984-11-01 Matsushita Electric Ind Co Ltd 半導体基板の製造方法
JPS60124841A (ja) * 1983-12-09 1985-07-03 Fujitsu Ltd 半導体装置の製造方法
US4484979A (en) * 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
US4631219A (en) * 1985-01-31 1986-12-23 International Business Machines Corporation Growth of bird's beak free semi-rox
US4626317A (en) * 1985-04-03 1986-12-02 Advanced Micro Devices, Inc. Method for planarizing an isolation slot in an integrated circuit structure

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JPH01151245A (ja) 1989-06-14
EP0316550A2 (en) 1989-05-24
EP0316550A3 (en) 1991-01-16
US4791073A (en) 1988-12-13

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