KR900017220A - 다중 충전된 트렌치 구성 및 시드층으로부터의 트렌치 충전 처리 방법 - Google Patents
다중 충전된 트렌치 구성 및 시드층으로부터의 트렌치 충전 처리 방법 Download PDFInfo
- Publication number
- KR900017220A KR900017220A KR1019890004884A KR890004884A KR900017220A KR 900017220 A KR900017220 A KR 900017220A KR 1019890004884 A KR1019890004884 A KR 1019890004884A KR 890004884 A KR890004884 A KR 890004884A KR 900017220 A KR900017220 A KR 900017220A
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- Prior art keywords
- trench
- sidewalls
- multilayer
- processing method
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제7도는 다른 처리 단계로 본 발명에 따라 트렌치가 구성되고 채워진 반도체 기관을 통하여 간단하게 도시된 된단면도.
Claims (3)
- 다중으로 채워진 트렌치를 구성하기 위한 처리 방법에 있어서, 상기외 처리 방법이, 기판표면으로부터 기관으로 선정된 깊이를 연장시키는 측벽을 가진 트렌치를 에칭시키는 단계와, 최소한 유전체와 함게 측벽을 덮게하는 단계와, 제1두게를 가지고 있고, 기관 표멸 위로 연장하는 다중층을 유전체로 덮게 하는 단계와, 최소한 부분직으로 기판 료면에서부터 다중층을 제거시키고, 트랜치 측벽의 하부 부분 위의 유전체 위에 있는 다중층외 잔류부분이 남아 있는 트렌치 측벽의 상부부분위에 유전체로부터 다중층을완전히 제거시키는 단계와, 트렌치를 채우는 다중층의 잔류 부뚠위에 서 다중층을 침 착시 키는 단계를 포함하는 것을 툭징으로 하는 다줄 충전된 트켄치 구성 처리 방법.
- 제1항에 있어서. 트렌치 측벽의 하부부분 위에 있는 유전체상에 다중층의 잔류 부분이 제1두게보다 더 두걸고, 트렌치 깊이의 70퍼센트로다는 작은측벽에 따라높이를 가지는 것을 특징으로 하는 다중 충전 트렌치 구성용 처리 방법.
- 시드층으로부7·1 트렌치를 채우기 위한 처리 방법에 있어서, 상기의 처리 방법이, 중요한표면을 가진 기판율 제공하는 단계와, 중요한 표면으로부터 기판으로 선정된 깊이를 연장시키는 바닥과 측벽을 가진 트렌치를 에칭시키는 단계와, 제1두게를 가진 시드충을 루벽에 인가시키는 단계와, 실제로 트렌치를 채우고, 기판표면위로 연장하는 마스킹퐁을 틸착시키는 단계와. 트렌치의 상부 부분과 기판 표면 위의 마스킹충의 제1부분율 재거시키고,상기의 제1 두게로다 더 큰 높이로 트렌치의 하부 부분에서 시드층을 덮고 있는 마스킹층외 제2부분을 남겨두는 단계와. 트렌치의 상루 부틱에서 측벽으로부터 시드풍을 완전히 제거시키고, 트렌치의 하부 부분에서 측벽위에 시드풍의 잔류 루틱을 남겨 놓는 단계를 포함하며, 여기에서 시드층의 잔류부분이 트렌치 깊이의 약 70퍼센트 보다 작고, 제1두게토다 더 큰 측벽을 따라 측정된 높이를 가지며: 시드층의 잔류 부녁위에서 핵을 형성하는 추가 물질을 침착시킴으로써 트렌치를 채우는 단계를 포함하는 것을 특징으로 하는 시드층으로부터의 트렌치 충전 처리 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US182816 | 1988-04-18 | ||
US07/182,816 US4847214A (en) | 1988-04-18 | 1988-04-18 | Method for filling trenches from a seed layer |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900017220A true KR900017220A (ko) | 1990-11-15 |
KR0157403B1 KR0157403B1 (ko) | 1998-12-01 |
Family
ID=22670159
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890004884A KR0157403B1 (ko) | 1988-04-18 | 1989-04-13 | 다중 충전된 트렌치 형성방법 및 시드층으로부터의 트렌치 충전 방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4847214A (ko) |
EP (1) | EP0338480B1 (ko) |
JP (1) | JPH01312850A (ko) |
KR (1) | KR0157403B1 (ko) |
DE (1) | DE68927686T2 (ko) |
Families Citing this family (41)
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US5057443A (en) * | 1988-06-29 | 1991-10-15 | Texas Instruments Incorporated | Method for fabricating a trench bipolar transistor |
US4963506A (en) * | 1989-04-24 | 1990-10-16 | Motorola Inc. | Selective deposition of amorphous and polycrystalline silicon |
US4942137A (en) * | 1989-08-14 | 1990-07-17 | Motorola, Inc. | Self-aligned trench with selective trench fill |
US4992388A (en) * | 1989-12-10 | 1991-02-12 | Motorola, Inc. | Short channel IGFET process |
US5077228A (en) * | 1989-12-01 | 1991-12-31 | Texas Instruments Incorporated | Process for simultaneous formation of trench contact and vertical transistor gate and structure |
US5110410A (en) * | 1990-08-13 | 1992-05-05 | Texas Instruments Incorporated | Zinc sulfide planarization |
US5096849A (en) * | 1991-04-29 | 1992-03-17 | International Business Machines Corporation | Process for positioning a mask within a concave semiconductor structure |
US5262354A (en) * | 1992-02-26 | 1993-11-16 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5213989A (en) * | 1992-06-24 | 1993-05-25 | Motorola, Inc. | Method for forming a grown bipolar electrode contact using a sidewall seed |
US5270265A (en) * | 1992-09-01 | 1993-12-14 | Harris Corporation | Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure |
US5387538A (en) * | 1992-09-08 | 1995-02-07 | Texas Instruments, Incorporated | Method of fabrication of integrated circuit isolation structure |
DE59409300D1 (de) * | 1993-06-23 | 2000-05-31 | Siemens Ag | Verfahren zur Herstellung von einem Isolationsgraben in einem Substrat für Smart-Power-Technologien |
US5387540A (en) * | 1993-09-30 | 1995-02-07 | Motorola Inc. | Method of forming trench isolation structure in an integrated circuit |
JPH07183370A (ja) * | 1993-12-24 | 1995-07-21 | Nec Corp | 半導体装置の製造方法 |
US5994718A (en) * | 1994-04-15 | 1999-11-30 | National Semiconductor Corporation | Trench refill with selective polycrystalline materials |
US5963814A (en) * | 1997-10-28 | 1999-10-05 | Micron Technology, Inc. | Method of forming recessed container cells by wet etching conductive layer and dissimilar layer formed over conductive layer |
US6583457B1 (en) | 1997-10-28 | 2003-06-24 | Micron Technology, Inc. | Recessed container cells and method of forming the same |
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US6333274B2 (en) | 1998-03-31 | 2001-12-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device including a seamless shallow trench isolation step |
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US6156611A (en) * | 1998-07-20 | 2000-12-05 | Motorola, Inc. | Method of fabricating vertical FET with sidewall gate electrode |
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US6322953B1 (en) * | 1999-03-29 | 2001-11-27 | Winbond Electronics Corporation | Method for obtaining uniform photoresist coatings |
US6316331B1 (en) * | 2000-10-13 | 2001-11-13 | Vanguard International Semiconductor Corp. | Method of making dishing-free insulator in trench isolation |
US6436791B1 (en) | 2001-06-14 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing a very deep STI (shallow trench isolation) |
US6861334B2 (en) * | 2001-06-21 | 2005-03-01 | Asm International, N.V. | Method of fabricating trench isolation structures for integrated circuits using atomic layer deposition |
US6677205B2 (en) * | 2001-09-28 | 2004-01-13 | Infineon Technologies Ag | Integrated spacer for gate/source/drain isolation in a vertical array structure |
TW567560B (en) * | 2002-07-02 | 2003-12-21 | Mosel Vitelic Inc | Method of forming bottom oxide layer in trench |
US6888214B2 (en) * | 2002-11-12 | 2005-05-03 | Micron Technology, Inc. | Isolation techniques for reducing dark current in CMOS image sensors |
DE102005039667A1 (de) * | 2005-08-22 | 2007-03-01 | Infineon Technologies Ag | Verfahren zum Herstellen einer Struktur mit geringem Aspektverhältnis |
US7807536B2 (en) * | 2006-02-10 | 2010-10-05 | Fairchild Semiconductor Corporation | Low resistance gate for power MOSFET applications and method of manufacture |
US7795152B2 (en) * | 2006-05-10 | 2010-09-14 | Micron Technology, Inc. | Methods of making self-aligned nano-structures |
US8263474B2 (en) * | 2007-01-11 | 2012-09-11 | Tokyo Electron Limited | Reduced defect silicon or silicon germanium deposition in micro-features |
JP5490753B2 (ja) * | 2010-07-29 | 2014-05-14 | 東京エレクトロン株式会社 | トレンチの埋め込み方法および成膜システム |
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KR20180018510A (ko) * | 2015-06-18 | 2018-02-21 | 인텔 코포레이션 | 반도체 구조체들을 위한 금속 피처들의 BUF(Bottom-Up Fill) |
US10170305B1 (en) | 2017-08-30 | 2019-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective film growth for bottom-up gap filling |
DE102017126528A1 (de) * | 2017-09-29 | 2019-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium-Lückenfüllen durch selektives Wachstum von unten nach oben |
US10468501B2 (en) * | 2017-09-29 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gap-filling germanium through selective bottom-up growth |
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US32090A (en) * | 1861-04-16 | Clothes-wbiitgee | ||
US4476623A (en) * | 1979-10-22 | 1984-10-16 | International Business Machines Corporation | Method of fabricating a bipolar dynamic memory cell |
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GB2183090B (en) * | 1985-10-07 | 1989-09-13 | Canon Kk | Method for selective formation of deposited film |
-
1988
- 1988-04-18 US US07/182,816 patent/US4847214A/en not_active Expired - Lifetime
-
1989
- 1989-04-13 KR KR1019890004884A patent/KR0157403B1/ko not_active IP Right Cessation
- 1989-04-14 JP JP1093270A patent/JPH01312850A/ja active Pending
- 1989-04-17 DE DE68927686T patent/DE68927686T2/de not_active Expired - Fee Related
- 1989-04-17 EP EP89106844A patent/EP0338480B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE68927686D1 (de) | 1997-03-06 |
US4847214A (en) | 1989-07-11 |
EP0338480A1 (en) | 1989-10-25 |
EP0338480B1 (en) | 1997-01-22 |
KR0157403B1 (ko) | 1998-12-01 |
JPH01312850A (ja) | 1989-12-18 |
DE68927686T2 (de) | 1997-07-24 |
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