KR930001375A - 반도체 장치 제조방법 - Google Patents

반도체 장치 제조방법 Download PDF

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Publication number
KR930001375A
KR930001375A KR1019920009813A KR920009813A KR930001375A KR 930001375 A KR930001375 A KR 930001375A KR 1019920009813 A KR1019920009813 A KR 1019920009813A KR 920009813 A KR920009813 A KR 920009813A KR 930001375 A KR930001375 A KR 930001375A
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South Korea
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opening
layer
silicon nitride
silicon
semiconductor device
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KR1019920009813A
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KR100242396B1 (ko
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안토니우스 반 데르 플라스 파울루스
안 헬레나 프레디 빌스 니콜
후버투스 몬트리 안드레스
Original Assignee
프레데릭 얀 스미트
엔. 브이. 필립스 글로아이람펜파브리켄
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Publication of KR930001375A publication Critical patent/KR930001375A/ko
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Publication of KR100242396B1 publication Critical patent/KR100242396B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체 장치 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제6도는 본 발명에 따른 방법에 의한 반도체장치를 제조하는 연속 단계들을 도시한 개략 단면도.

Claims (6)

  1. 산화실리콘의 하부층, 다결정실리콘의 중간층과 질화실리콘을 포함하는 상부층을 포함하며, 실리콘기판의 표면상에 제공된 층상 구조에 형성하되, 개구를 상기 상부층에 식각하고 상기 중간층을 상기 개구의 내부와 상기 개구의 모서리 아래에서 식각으로 제거하여 상기 모서리에 동공부를 형성하고 질화실리콘을 포함하는 물질을 상기 동공부에 제공하여 형성한 산화마스크가 제공된 상기 실리콘 기판의 표면에 산화를 통해 필드산화물 영역을 형성하는 반도체 장치 제조방법에 있어서, 상기 개구 내부에 위치되어 있는 실리콘기판이 산화실리콘층으로 덮혀져 있는 상태에서 동공부에 질화실리콘을 포함하는 물질을 제공하는 겻을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 질화실리콘을 포함하는 상기 물질을 상기 동공부에 제공하는 동안 상기 개구 내부의 상기 실리콘기판의 산화마스크가 형성되는 상기 층상구조의 산화실리콘의 상기 하부층에 의해 계속 덮혀져 있는 것을 특징으로 하는 반도체 장치 제조방법.
  3. 제1항 또는 제2항에 있어서, 상기 동공부에 제공하는 질화실리콘을 포함하는 상기 물질이 질화실리콘인 것을 특징으로 하는 반도체 장치 제조방법.
  4. 제1항, 제2항 또는 제3항에 있어서, 질화실리콘을 포함하는 상기 물질은, 상기 개구를 상부층에 제공하고 상기 중간층을 개구의 내부와 개구의 모서리 아래에서 제거하며 질화실리콘을 포함하는 물질층을 침적한 후에 개구 내부의 실리콘기판 표면을 노출할 때까지 이방성 식각처리를 수행함으로써 제공되는 것을 특징으로 하는 반도체 장치 제조방법.
  5. 제4항에 있어서, 상기 층상 구조의 다결정실리콘의 중간층을 상기 상부층의 위, 상기 개구의 내부와 개구의 모서리 아래에 침적하는 질화 실리콘을 포함하는 상기 물질층의 두께와 실제로 동일한 두께로 제공하는 것을 특징으로 하는 반도체 장치 제조방법.
  6. 제5항에 있어서, 상기 필드산화물영역의 가로방향으로 존재하는 거대잠식 부분의 거리와 실제로 동일한 두께로 상기 상부층의 위, 상기 개부 내부와 상기 개구의 모서리 하부에 필화실리콘을 포함하는 상기 물질층을 침적하는 것을 특징으로 하는 반도체장치 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019920009813A 1991-06-10 1992-06-05 반도체 장치 제조방법 KR100242396B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP91201414 1991-06-10
EP91201414.9 1991-06-10

Publications (2)

Publication Number Publication Date
KR930001375A true KR930001375A (ko) 1993-01-16
KR100242396B1 KR100242396B1 (ko) 2000-03-02

Family

ID=8207705

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KR1019920009813A KR100242396B1 (ko) 1991-06-10 1992-06-05 반도체 장치 제조방법

Country Status (4)

Country Link
US (1) US5254494A (ko)
EP (1) EP0518418A1 (ko)
JP (1) JP2662143B2 (ko)
KR (1) KR100242396B1 (ko)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69228117T2 (de) * 1992-09-23 1999-05-20 Co.Ri.M.Me., Catania Verfahren zum Verhindern des "Bird's beak" während der selektiven Oxidation von elektronischen Halbleiteranordnungen
KR960011861B1 (ko) * 1993-06-10 1996-09-03 삼성전자 주식회사 반도체장치의 소자 분리 방법
DE4336869C2 (de) * 1993-10-28 2003-05-28 Gold Star Electronics Verfahren zum Herstellen eines MOS-Transistors
JPH07169759A (ja) * 1993-12-14 1995-07-04 Fujitsu Ltd 半導体装置の製造方法と半導体装置
JPH0897202A (ja) * 1994-09-22 1996-04-12 Fujitsu Ltd 半導体装置の製造方法
US5498556A (en) * 1995-01-10 1996-03-12 United Microelectronics Corp. Metal-oxide-semiconductor field-effect transistor and its method of fabrication
US5814186A (en) * 1995-08-28 1998-09-29 Advanced Micro Devices, Inc. SOG etchant gas and method for using same
US5612248A (en) * 1995-10-11 1997-03-18 Micron Technology, Inc. Method for forming field oxide or other insulators during the formation of a semiconductor device
US5891788A (en) * 1996-11-14 1999-04-06 Micron Technology, Inc. Locus isolation technique using high pressure oxidation (hipox) and protective spacers
US6133118A (en) * 1997-08-22 2000-10-17 Acer Semiconductor Manufacturing Inc. Edge polysilicon buffer LOCOS isolation
US6080676A (en) * 1998-09-17 2000-06-27 Advanced Micro Devices, Inc. Device and method for etching spacers formed upon an integrated circuit gate conductor
US6281132B1 (en) 1998-10-06 2001-08-28 Advanced Micro Devices, Inc. Device and method for etching nitride spacers formed upon an integrated circuit gate conductor
ITMI20042243A1 (it) * 2004-11-19 2005-02-19 St Microelectronics Srl Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione
US7875936B2 (en) 2004-11-19 2011-01-25 Stmicroelectronics, S.R.L. Power MOS electronic device and corresponding realizing method
TWI290739B (en) * 2006-02-13 2007-12-01 Touch Micro System Tech Method of edge bevel rinse

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US4318759A (en) * 1980-07-21 1982-03-09 Data General Corporation Retro-etch process for integrated circuits
US4407696A (en) * 1982-12-27 1983-10-04 Mostek Corporation Fabrication of isolation oxidation for MOS circuit
US4580330A (en) * 1984-06-15 1986-04-08 Texas Instruments Incorporated Integrated circuit isolation
JPS61296741A (ja) * 1985-06-25 1986-12-27 Nec Corp 半導体装置の製造方法
JPH079930B2 (ja) * 1985-07-10 1995-02-01 松下電子工業株式会社 半導体装置の製造方法
JPS62216246A (ja) * 1986-03-17 1987-09-22 Nippon Texas Instr Kk 半導体装置の製造方法
US4755477A (en) * 1987-03-24 1988-07-05 Industrial Technology Research Institute Overhang isolation technology
JPH0744214B2 (ja) * 1988-06-29 1995-05-15 三菱電機株式会社 半導体装置の製造方法
EP0424018A3 (en) * 1989-10-17 1991-07-31 American Telephone And Telegraph Company Integrated circuit field isolation process

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Publication number Publication date
EP0518418A1 (en) 1992-12-16
JPH05198590A (ja) 1993-08-06
KR100242396B1 (ko) 2000-03-02
US5254494A (en) 1993-10-19
JP2662143B2 (ja) 1997-10-08

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