KR970707571A - 축소 치수용 다마스크 공정(damascene process for reduced feature size) - Google Patents

축소 치수용 다마스크 공정(damascene process for reduced feature size)

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KR970707571A
KR970707571A KR1019970703177A KR19970703177A KR970707571A KR 970707571 A KR970707571 A KR 970707571A KR 1019970703177 A KR1019970703177 A KR 1019970703177A KR 19970703177 A KR19970703177 A KR 19970703177A KR 970707571 A KR970707571 A KR 970707571A
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South Korea
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dielectric material
dimension
semiconductor device
dielectric layer
opening
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KR1019970703177A
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밍-렌 린
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이시마루 미키오
어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Publication of KR970707571A publication Critical patent/KR970707571A/ko

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    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

초기치수를 가진 하나의 개구를 형성하고, 제2유전물질을 이 개구내에 증착시켜서 초기치수를 축소시킴으로써, 유전층내에 서브미크론의 점점/바이어 및 트렌치를 제공한다.

Description

축소 치수용 다마스크 공정(DAMASCENE PROCESS FOR REDUCED FEATURE SIZE)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 실시예에 의하여 형성된 바이어/접점 또는 트렌치를 도시하는 단면도, 제3도는 종래의 이중마스크기술에 의하여 형성된 상호접속을 도시한 개략도, 제4도는 상호접속을 제공하기 위한 본 발명의 또 다른 실시예를 도시한 개략도이다.

Claims (42)

  1. 제1유전물질로 구성되어있고, 상면, 하면 및 상면으로부터 하면까지 제1유전층을 거쳐 뻗어있는 제1개구가 제공되어 있는 제1유전층을 포함하는 반도체소자로서, 제1개구가 제2유전물질로 구성된 한정된 두께를 가진 제1측벽에 의하여 그 범위가 한정되는 제1치수를 가지는 반도체소자.
  2. 제1항에 있어서, 제2유전물질이 제1유전물질과 동일한 반도체 소자.
  3. 제1항에 있어서, 제2유전물질이 제1유전물질과 다른 반도체 소자.
  4. 제1항에 있어서, 제1치수가 약 0.30 미크론 이하인 반도체 소자.
  5. 제4항에 있어서, 제1치수가 약 0.15 내지 0.25 미크론인 반도체 소자.
  6. 제5항에 있어서, 제1치수가 약 0.18 내지 0.20 미크론인 반도체 소자.
  7. 제3항에 있어서, 제1측벽이 두께가 0.05 미크론 보다 더 작지 아니한 반도체 소자.
  8. 제6항에 있어서, 제1측벽이 두께가 0.1 미크론 보다 더 작지 아니한 반도체 소자.
  9. 제3항에 있어서, 제2유전물질이 제1유전물질보다 더 큰 경도 및 밀도를 가지는 반도체 소자.
  10. 제3항에 있어서, 제2유전물질이 제1유전물질보다 습기침투에 대한 더 큰 저항을 가지는 반도체 소자.
  11. 제1항에 있어서, 제2유전물질이 이산화규소, 질화규소 및 산소질화규소로 구성되는 그룹으로부터 선택되는 반도체 소자.
  12. 제11항에 있어서, 제2유전물질에, 증착오르토규산테트라에틸로부터 유도된 이산화규소가 포함되어 있는 반도체소자.
  13. 제1항에 있어서, 제3유전물질로 구성되어 있고, 제1유전층상에 형성되어 있는 제2유전층이 더 포함되어 있고, 이러한 제2유전층에 상면, 제1유전층상의 하면 및 제2유전층의 상면으로부터 하면까지 뻗어 있는 제2유전층을 통하고, 제1개구와 통하여 있으며, 제2유전물질로 구성된 한정된 두께를 가진 측벽에 의하여 그 범위가 한정되는 제2치수를 가지는 제2개구가 포함되어 있는 반도체 소자.
  14. 제13항에 있어서, 제2치수가 제1치수보다 더 작은 반도체 소자.
  15. 제13항에 있어서, 제2치수가 제1치수와 동일한 반도체 소자.
  16. 제13항에 있어서, 제2치수가 제1치수보다도 더 큰 반도체 소자.
  17. 제13항에 있어서, 제2치수가 약 0.30 미크론 이하인 반도체 소자.
  18. 제13항에 있어서, 제2치수가 약 0.15 내지 0.25 미크론인 반도체 소자.
  19. 제13항에 있어서, 제1유전층의 상면과 제2유전층의 하면 사이에 하나의 유저막이 더 포함되어 있고 하나의 개구가 이러한 유전막내에 형성되어 있고, 이 개구를 거쳐 제2개구가 제1개구와 통하여 있는 반도체소자.
  20. 제13항에 있어서, 제1유전물질이 제3유전물질과 동일한 반도체 소자.
  21. 반도체소자를 제조하는 방법으로서, －제1유전물질로 구성되어 있고, 상면과 하면이 제공되어 있는 제1유전층을 형성하는 스텝, －제1유전층을 거쳐 상면으로부터 하면까지 뻗어있고, 제1유전층내의 측면에 의하여 그 범위가 한정되는 제1초기치수를 가지는 제1개구를 형성하는 스텝, －제2유전물질을 제1개구내에 증착하여 제1측벽을 형성함으로써, 제1최종치수가 제1측벽에 의하여 한정되도록, 제1초기치수를 제1초기치수보다 더 작은 제1최종치수로 촉소하는 스텝, 등이 포함되어 있는 방법.
  22. 제21항에 있어서, 제2유전물질이 제1유전물질과 동일한 방법.
  23. 제21항에 있어서, 제2유전물질이 제1유전물질과 다른 방법.
  24. 제23항에 있어서, 제2유전물질의 경도와 밀도가 제1유전물질의 경도 및 밀도보다 더 큰 방법.
  25. 제23항에 있어서, 제2유전물질이 습기침투에 대하여 제1유전물질보다 더 큰 저항을 가지는 방법.
  26. 제21항에 있어서, 제2유전물질을 이산화규소, 질화규소 및 산화질화규소로 구성되는 그룹으로부터 선택하는 방법.
  27. 제26항에 있어서, 제2유전물질에 증착오르토규산테트라에틸로부터 유도된 이산화규소가 포함되어 있는 방법.
  28. 제21항에 있어서, 제2유전물질을 증착한 다음에, 블랫킹 비등방성 에칭이 더 포함되어 있는 방법.
  29. 반도체소자를 제조하는 방법으로서, －제1유전물질로 구성되고, 상면과 하면이 제공되어 있는 제1유전층을 형성하는 스텝, －제3유전물질로 구성되어 있고, 상면과 제1유전층상의 하면이 제공되어 있는 제2유전층을 제1유전층상에 형성하는 스텝, －제1유전층을 거쳐 상면으로부터 하면까지 뻗어있고, 제1유전층내의 측면에 의하여 한정되는 제1초기치수가 제공된 제1개구 및 제2유전층을 거쳐 상면으로부터 제2유전층의 하면까지 뻗어있고 제1개구와 통하여 있고, 제2유전층내에서 측면에 의하여 한정되는 제2초기치수가 제공되어 있는 제2개구를 포함하여, 제1 및 제2유전층을 통하는 개구를 형성하는 스텝, －제2유전물질을 제1 및 제2개구내에 증착시켜 하나의 측벽을 형성함으로써, 제1 및 제2최종치수가 측벽에 의하여 한정되도록, 제1 및 제2초기치수를 제1 및 제2초기치수보다 더 작은 제1 및 제2최종치수로 축소하는 스텝, 등이 포함되어 있는 방법.
  30. 제29항에 있어서, 제1유전물질이 제3유전물질과 동일한 방법.
  31. 제29항에 있어서, 제1유전물질이 제3유전물질과 다른 방법.
  32. 제29항에 있어서, 제2최종치수가 제1최종치수와 동일한 방법.
  33. 제29항에 있어서, 제2최종치수가 제1최종치수보다 더 작은 방법.
  34. 제29항에 있어서, 제2최종치수가 제1최종치수보다 더 큰 방법.
  35. 제29항에 있어서, 제2최종치수가 약 0.30 미크론보다 더 작은 방법.
  36. 제29항에 있어서, 제2최종치수가 약 0.15 내지 0.20 미크론인 방법.
  37. 제29항에 있어서, 제2유전층을 증착하기 전에, 하나의 유전막을 제1유전층의 상면상에 증착하는 스텝이 더 포함되어 있는 방법.
  38. 제29항에 있어서, 개구를 이중다마스크기술에 의하여 형성하는 스텝이 포함되어 있는 방법.
  39. 제29항에 있어서, 제1개구와 제2개구를 동시에 형성한 스텝이 포함되어 있는 방법.
  40. 제29항에 있어서, 제2개구를 형성하기 전에, 제1개구를 형성하는 스텝이 포함되어 있는 방법.
  41. 제29항에 있어서, 제1개구를 형성하기 전에, 제2개구를 형성하는 스텝이 포함되어 있는 방법.
  42. 제29항에 있어서, 제2유전층을 증착한 다음에, 블랭킷 비등방성 에칭을 행하는 스텝이 더 포함되어 있는 방법.
    ※ 참고사항：최초출원 내용에 의하여 공개하는 것임.
KR1019970703177A 1995-09-14 1996-08-08 축소 치수용 다마스크 공정(damascene process for reduced feature size) KR970707571A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52827995A 1995-09-14 1995-09-14
US08/528,279 1995-09-14

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KR970707571A true KR970707571A (ko) 1997-12-01

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JPH10509285A (ja) 1998-09-08
EP0792513A1 (en) 1997-09-03
US6077773A (en) 2000-06-20
WO1997010612A1 (en) 1997-03-20
US5753967A (en) 1998-05-19

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