DE69734871D1 - Verfahren zur Herstellung eines Germanium-implantierten bipolaren Heteroübergangtransistors - Google Patents

Verfahren zur Herstellung eines Germanium-implantierten bipolaren Heteroübergangtransistors

Info

Publication number
DE69734871D1
DE69734871D1 DE69734871T DE69734871T DE69734871D1 DE 69734871 D1 DE69734871 D1 DE 69734871D1 DE 69734871 T DE69734871 T DE 69734871T DE 69734871 T DE69734871 T DE 69734871T DE 69734871 D1 DE69734871 D1 DE 69734871D1
Authority
DE
Germany
Prior art keywords
germanium
making
heterojunction transistor
bipolar heterojunction
implanted bipolar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69734871T
Other languages
English (en)
Inventor
Salvatore Lombardo
Angelo Pinto
Maria Concetta Nicotra
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Original Assignee
STMicroelectronics SRL
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69734871D1 publication Critical patent/DE69734871D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
DE69734871T 1997-05-30 1997-05-30 Verfahren zur Herstellung eines Germanium-implantierten bipolaren Heteroübergangtransistors Expired - Lifetime DE69734871D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP97830259A EP0881669B1 (de) 1997-05-30 1997-05-30 Verfahren zur Herstellung eines Germanium-implantierten bipolaren Heteroübergangtransistors

Publications (1)

Publication Number Publication Date
DE69734871D1 true DE69734871D1 (de) 2006-01-19

Family

ID=8230652

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69734871T Expired - Lifetime DE69734871D1 (de) 1997-05-30 1997-05-30 Verfahren zur Herstellung eines Germanium-implantierten bipolaren Heteroübergangtransistors

Country Status (4)

Country Link
US (2) US6624017B1 (de)
EP (1) EP0881669B1 (de)
JP (1) JPH1187364A (de)
DE (1) DE69734871D1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6693033B2 (en) 2000-02-10 2004-02-17 Motorola, Inc. Method of removing an amorphous oxide from a monocrystalline surface
US6638838B1 (en) 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US6667196B2 (en) 2001-07-25 2003-12-23 Motorola, Inc. Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method
US6639249B2 (en) 2001-08-06 2003-10-28 Motorola, Inc. Structure and method for fabrication for a solid-state lighting device
US6673667B2 (en) 2001-08-15 2004-01-06 Motorola, Inc. Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
KR100400327B1 (ko) * 2001-12-29 2003-10-01 주식회사 하이닉스반도체 반도체소자의 캐패시터 형성방법
JP2003347399A (ja) * 2002-05-23 2003-12-05 Sharp Corp 半導体基板の製造方法
DE10324065A1 (de) * 2003-05-27 2004-12-30 Texas Instruments Deutschland Gmbh Verfahren zur Herstellung eines integrierten Silizium-Germanium-Heterobipolartranistors und ein integrierter Silizium-Germanium Heterobipolartransitor
JP5393027B2 (ja) * 2004-03-10 2014-01-22 アギア システムズ インコーポレーテッド シリコン・ゲルマニウム層中に高濃度のゲルマニウムを有するバイポーラ接合トランジスタおよびその形成方法
US8227319B2 (en) 2004-03-10 2012-07-24 Agere Systems Inc. Bipolar junction transistor having a high germanium concentration in a silicon-germanium layer and a method for forming the bipolar junction transistor
EP1610371A1 (de) * 2004-06-24 2005-12-28 STMicroelectronics S.r.l. SIGe Heteroübergang-Bipolartransistoren
US8120014B2 (en) * 2004-12-15 2012-02-21 Drexel University Nanowire based plasmonics
CN102142457A (zh) * 2011-03-15 2011-08-03 上海宏力半导体制造有限公司 异质结双极型晶体管及其制备方法
CN114335234A (zh) * 2022-01-07 2022-04-12 重庆邮电大学 一种硅锗异质结光电晶体管及其制造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS588139B2 (ja) 1979-05-31 1983-02-14 富士通株式会社 半導体装置の製造方法
US5296391A (en) * 1982-03-24 1994-03-22 Nec Corporation Method of manufacturing a bipolar transistor having thin base region
JPH0797590B2 (ja) 1989-11-21 1995-10-18 株式会社東芝 バイポーラトランジスタの製造方法
JPH03292740A (ja) * 1990-04-11 1991-12-24 Hitachi Ltd バイポーラトランジスタ及びその製造方法
US5028557A (en) 1990-08-27 1991-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a reverse self-aligned BIMOS transistor integrated circuit
JP2551364B2 (ja) * 1993-11-26 1996-11-06 日本電気株式会社 半導体装置
US5712177A (en) 1994-08-01 1998-01-27 Motorola, Inc. Method for forming a reverse dielectric stack
US5665620A (en) 1994-08-01 1997-09-09 Motorola, Inc. Method for forming concurrent top oxides using reoxidized silicon in an EPROM
US5635423A (en) 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5643825A (en) * 1994-12-29 1997-07-01 Advanced Micro Devices, Inc. Integrated circuit isolation process
US5659201A (en) 1995-06-05 1997-08-19 Advanced Micro Devices, Inc. High conductivity interconnection line
WO1997010612A1 (en) 1995-09-14 1997-03-20 Advanced Micro Devices, Inc. Damascene process for reduced feature size
US5847460A (en) 1995-12-19 1998-12-08 Stmicroelectronics, Inc. Submicron contacts and vias in an integrated circuit
DE19609933A1 (de) * 1996-03-14 1997-09-18 Daimler Benz Ag Verfahren zur Herstellung eines Heterobipolartransistors
US5814555A (en) * 1996-06-05 1998-09-29 Advanced Micro Devices, Inc. Interlevel dielectric with air gaps to lessen capacitive coupling
US5960297A (en) * 1997-07-02 1999-09-28 Kabushiki Kaisha Toshiba Shallow trench isolation structure and method of forming the same
TWI329112B (en) * 2002-07-19 2010-08-21 Bristol Myers Squibb Co Novel inhibitors of kinases

Also Published As

Publication number Publication date
EP0881669A1 (de) 1998-12-02
JPH1187364A (ja) 1999-03-30
US20040004270A1 (en) 2004-01-08
US6624017B1 (en) 2003-09-23
EP0881669B1 (de) 2005-12-14

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