KR840007202A - 클럭 펄스 성형회로 - Google Patents
클럭 펄스 성형회로 Download PDFInfo
- Publication number
- KR840007202A KR840007202A KR1019830006045A KR830006045A KR840007202A KR 840007202 A KR840007202 A KR 840007202A KR 1019830006045 A KR1019830006045 A KR 1019830006045A KR 830006045 A KR830006045 A KR 830006045A KR 840007202 A KR840007202 A KR 840007202A
- Authority
- KR
- South Korea
- Prior art keywords
- clock
- clock pulse
- circuit
- control
- input
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3,4,5도는 시험적인 충력계수의 다른 입력 클럭 신호에 대한 실제적인 클럭신호 출력의 전압대 시간의 도표.
Claims (5)
- 제1시간 분리에서 나타나는 전이를 지닌 클럭-아웃신호를 상기 출려에서 발생하도록 입력(11) 및 출력(12)과 평균전압을 가지고, 상기 클럭-아웃신호는 제2시간 분리에서 나타나는 전이를 가지는 상기 입력에 인가된 클럭-인 신호에 응답하여 나타나는 클럭 펄스 성형회로에 있어서, 가변지연수단(15-18)은 상기 입력과 상기 출력사이에서 연결되고, 상기 지연수단은 상기 평균전압을 변화시키는 방법으로 상기 단에서의 지연을 변화시키기 위한 제어신호를 수신하는 제어입력(트랜지스터 게이트전극)을 가지고, 제어수단(22)은 상기 가변지연단에 상기 제어신호를 인가하기 위한 상기 평균전압의 변화에 응답하는 것을 특징으로 하는 클럭펄스 성형회로.
- 제1항에 따른 회로에 있어서, 상기 제어수단은 상기 평균전압과 상기 제어신호를 공급하기 위한 기준전압 ½VDD를 비교하는 연산증폭기(22)를 구비하는 것을 특징으로 하는 클럭펄스 성형회로.
- 제2항에 따른 회로에 있어서, 상기 지연수단은 상기 클럭-아웃신호의 상승단 및 하강단의 타이밍을 독립적으로 조정하는 수단(170,171)을 구비하는 것을 특징으로 하는 클럭펄스 성형회로.
- 제2항에 따른 회로에 있어서, 상기 연산증폭기는 높은 이득을 가지는 것을 특징으로 하는 클럭펄스 성형회로.
- 제1항에 따른 회로에 있어서, 상기 제1 및 제2입력에 인가되어진 제1과 제2평균전압의 차에 의해 결정되어진 값인 상기 제어신호를 공급하기 위한 제1 및 제2제어입력(+,-)을 가지고, 상기 회로는 또한 상기 제1제어입력에 연결된 제1평균기준전압을 발생시키는 수단(VDD,25)과, 상기 클럭-아웃출력과 상기 제2제어입력사이에 연결된 제2평균전압을 발생시키는 수단(23,24)을 구비하고, 상기 회로는 상기 제1 및 제2 평균전압사이의 차의 함수로서 상기 클럭-인 입력에 인가되어진 상기 클럭펄스의 지연을 조정하도록 동작되는 것을 특징으로 하는 클럭펄스 성형회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US452157 | 1982-12-22 | ||
US06/452,157 US4479216A (en) | 1982-12-22 | 1982-12-22 | Skew-free clock circuit for integrated circuit chip |
Publications (1)
Publication Number | Publication Date |
---|---|
KR840007202A true KR840007202A (ko) | 1984-12-05 |
Family
ID=23795288
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019830006045A KR840007202A (ko) | 1982-12-22 | 1983-12-20 | 클럭 펄스 성형회로 |
Country Status (7)
Country | Link |
---|---|
US (1) | US4479216A (ko) |
EP (1) | EP0129580A4 (ko) |
JP (1) | JPS60500115A (ko) |
KR (1) | KR840007202A (ko) |
GB (1) | GB2133645B (ko) |
IT (1) | IT1173688B (ko) |
WO (1) | WO1984002621A1 (ko) |
Families Citing this family (50)
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US4508983A (en) * | 1983-02-10 | 1985-04-02 | Motorola, Inc. | MOS Analog switch driven by complementary, minimally skewed clock signals |
US4527075A (en) * | 1983-07-11 | 1985-07-02 | Sperry Corporation | Clock source with automatic duty cycle correction |
US4639615A (en) * | 1983-12-28 | 1987-01-27 | At&T Bell Laboratories | Trimmable loading elements to control clock skew |
US4782253A (en) * | 1984-02-15 | 1988-11-01 | American Telephone & Telegraph Company, At&T Bell Laboratories | High speed MOS circuits |
US4754164A (en) * | 1984-06-30 | 1988-06-28 | Unisys Corp. | Method for providing automatic clock de-skewing on a circuit board |
EP0390226A1 (en) * | 1984-07-31 | 1990-10-03 | Yamaha Corporation | Jitter absorption circuit |
US4633226A (en) * | 1984-12-17 | 1986-12-30 | Black Jr William C | Multiple channel analog-to-digital converters |
US4714924A (en) * | 1985-12-30 | 1987-12-22 | Eta Systems, Inc. | Electronic clock tuning system |
JPS62230221A (ja) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | バツフア回路 |
US4769558A (en) * | 1986-07-09 | 1988-09-06 | Eta Systems, Inc. | Integrated circuit clock bus layout delay system |
EP0469634A1 (en) * | 1986-08-27 | 1992-02-05 | Ohmatoi Naoyuki | Pulse phase adjusting circuit for use with an electrostatic capacitor type sensor |
US4755704A (en) * | 1987-06-30 | 1988-07-05 | Unisys Corporation | Automatic clock de-skewing apparatus |
US4860288A (en) * | 1987-10-23 | 1989-08-22 | Control Data Corporation | Clock monitor for use with VLSI chips |
US4868514A (en) * | 1987-11-17 | 1989-09-19 | International Business Machines Corporation | Apparatus and method for digital compensation of oscillator drift |
US4839907A (en) * | 1988-02-26 | 1989-06-13 | American Telephone And Telegraph Company, At&T Bell Laboratories | Clock skew correction arrangement |
US4926066A (en) * | 1988-09-12 | 1990-05-15 | Motorola Inc. | Clock distribution circuit having minimal skew |
JP2756325B2 (ja) * | 1989-12-07 | 1998-05-25 | 株式会社日立製作所 | クロック供給回路 |
US5118975A (en) * | 1990-03-05 | 1992-06-02 | Thinking Machines Corporation | Digital clock buffer circuit providing controllable delay |
US5159205A (en) * | 1990-10-24 | 1992-10-27 | Burr-Brown Corporation | Timing generator circuit including adjustable tapped delay line within phase lock loop to control timing of signals in the tapped delay line |
FR2681992A1 (fr) * | 1991-09-30 | 1993-04-02 | Bull Sa | Circuit a retard a commande numerique. |
US5640112A (en) * | 1994-02-28 | 1997-06-17 | Rikagaku Kenkyusho | Clock signal distributing system |
US5477180A (en) * | 1994-10-11 | 1995-12-19 | At&T Global Information Solutions Company | Circuit and method for generating a clock signal |
US5525914A (en) * | 1995-01-23 | 1996-06-11 | International Business Machines Corporation | CMOS driver circuit |
US5539333A (en) * | 1995-01-23 | 1996-07-23 | International Business Machines Corporation | CMOS receiver circuit |
US5548237A (en) * | 1995-03-10 | 1996-08-20 | International Business Machines Corporation | Process tolerant delay circuit |
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US6064707A (en) | 1995-12-22 | 2000-05-16 | Zilog, Inc. | Apparatus and method for data synchronizing and tracking |
US5856753A (en) * | 1996-03-29 | 1999-01-05 | Cypress Semiconductor Corp. | Output circuit for 3V/5V clock chip duty cycle adjustments |
US5990716A (en) * | 1996-06-27 | 1999-11-23 | Lsi Logic Corporation | Method and system for recovering digital data from a transmitted balanced signal |
US6060922A (en) * | 1998-02-20 | 2000-05-09 | Industrial Technology Research Institute | Duty cycle control buffer circuit with selective frequency dividing function |
DE19822373C2 (de) | 1998-02-20 | 2001-05-31 | Ind Technology Res Inst Hsinch | Frequenzvervielfachungsschaltung und -verfahren |
US6084452A (en) * | 1998-06-30 | 2000-07-04 | Sun Microsystems, Inc | Clock duty cycle control technique |
DE19927903A1 (de) * | 1999-06-18 | 2000-12-28 | Bosch Gmbh Robert | Vorrichtung zum Betreiben einer Last |
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US7571359B2 (en) * | 2000-07-31 | 2009-08-04 | Massachusetts Institute Of Technology | Clock distribution circuits and methods of operating same that use multiple clock circuits connected by phase detector circuits to generate and synchronize local clock signals |
DE10131635B4 (de) * | 2001-06-29 | 2004-09-30 | Infineon Technologies Ag | Vorrichtung und Verfahren zur Kalibrierung der Pulsdauer einer Signalquelle |
US6518809B1 (en) | 2001-08-01 | 2003-02-11 | Cypress Semiconductor Corp. | Clock circuit with self correcting duty cycle |
US6771136B1 (en) | 2001-12-10 | 2004-08-03 | Cypress Semiconductor Corp. | System and method for restoring the mark and space ratio of a clocking signal output from an oscillator |
US7461304B1 (en) * | 2003-07-07 | 2008-12-02 | Marvell Israel (M.I.S.L.) Ltd. | Integrated circuit test using clock signal modification |
JP2005064701A (ja) * | 2003-08-08 | 2005-03-10 | Rohm Co Ltd | クロック入出力装置 |
JP4556648B2 (ja) * | 2004-12-03 | 2010-10-06 | ヤマハ株式会社 | デューティ比補正回路 |
DE102005028173B4 (de) * | 2005-06-17 | 2007-03-08 | Texas Instruments Deutschland Gmbh | Integrierte CMOS-Tastverhältnis-Korrekturschaltung für ein Taktsignal |
US8035455B1 (en) | 2005-12-21 | 2011-10-11 | Cypress Semiconductor Corporation | Oscillator amplitude control network |
DE102006011448B4 (de) * | 2006-03-13 | 2013-08-01 | Austriamicrosystems Ag | Schaltungsanordnung und Verfahren zum Bereitstellen eines Taktsignals mit einem einstellbaren Tastverhältnis |
DE102006061649A1 (de) * | 2006-12-27 | 2008-07-03 | Infineon Technologies Ag | Einrichtung zum Einstellen eines Tastverhältnisses, Tastverhältnis-Einstellschaltung und Verfahren zum Einstellen eines Tastverhältnisses |
JP4412508B2 (ja) * | 2007-10-04 | 2010-02-10 | Necエレクトロニクス株式会社 | 半導体回路 |
JP2010183284A (ja) * | 2009-02-04 | 2010-08-19 | Toshiba Corp | 発振回路、及びメモリシステム |
US8384457B2 (en) * | 2011-04-06 | 2013-02-26 | Icera Inc. | Duty cycle correction |
US8954017B2 (en) | 2011-08-17 | 2015-02-10 | Broadcom Corporation | Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device |
ITUB20159405A1 (it) * | 2015-12-23 | 2017-06-23 | St Microelectronics Srl | Circuito e metodo di generazione di un segnale di clock con regolazione del duty cycle |
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US3646370A (en) * | 1970-07-06 | 1972-02-29 | Honeywell Inc | Stabilized monostable delay multivibrator or one-shot apparatus |
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US4241418A (en) * | 1977-11-23 | 1980-12-23 | Honeywell Information Systems Inc. | Clock system having a dynamically selectable clock period |
US4239992A (en) * | 1978-09-14 | 1980-12-16 | Telex Computer Products, Inc. | Frequency tracking adjustable duty cycle ratio pulse generator |
US4277697A (en) * | 1979-01-15 | 1981-07-07 | Norlin Industries, Inc. | Duty cycle control apparatus |
US4355283A (en) * | 1980-11-28 | 1982-10-19 | Rca Corporation | Circuit and method for duty cycle control |
-
1982
- 1982-12-22 US US06/452,157 patent/US4479216A/en not_active Expired - Lifetime
-
1983
- 1983-12-05 EP EP19840900231 patent/EP0129580A4/en not_active Withdrawn
- 1983-12-05 WO PCT/US1983/001897 patent/WO1984002621A1/en not_active Application Discontinuation
- 1983-12-05 JP JP84500267A patent/JPS60500115A/ja active Pending
- 1983-12-09 GB GB08332966A patent/GB2133645B/en not_active Expired
- 1983-12-19 IT IT24249/83A patent/IT1173688B/it active
- 1983-12-20 KR KR1019830006045A patent/KR840007202A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
US4479216A (en) | 1984-10-23 |
WO1984002621A1 (en) | 1984-07-05 |
IT8324249A0 (it) | 1983-12-19 |
EP0129580A1 (en) | 1985-01-02 |
GB2133645A (en) | 1984-07-25 |
IT1173688B (it) | 1987-06-24 |
EP0129580A4 (en) | 1987-09-02 |
GB2133645B (en) | 1986-07-02 |
JPS60500115A (ja) | 1985-01-24 |
GB8332966D0 (en) | 1984-01-18 |
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Legal Events
Date | Code | Title | Description |
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WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |