KR20210018887A - Semiconductor device - Google Patents

Abstract

The present invention provides a memory device capable of realizing high-speed operation or a memory device capable of reducing the frequency of refresh operations. A potential is supplied inside the cell array from the driving circuit to the wiring connected to the memory cell. In addition, a cell array is installed on the driving circuit, and each of the memory cells of the cell array includes a switching element, and a capacitive element in which supply, holding, and discharge of electric charge are controlled by the switching element. In addition, the transistor used as the switching element has a wider bandgap than silicon, and includes a semiconductor having an intrinsic carrier density lower than that of silicon and included in the channel formation region.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a memory device and a semiconductor device using the memory device.

In portable electronic devices such as mobile phones, smartphones, and e-books, semiconductor memory such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) with fast writing and reading operations for temporary storage of image data Devices (hereinafter, also simply referred to as storage devices) are being used. In order to realize a further high-speed operation of the storage device, in the case of SRAM, data is stored by flip-flops composed of a plurality of transistors, so it is effective to increase the switching speed of the transistors by miniaturization. However, in the case of DRAM, since data is stored by supplying electric charges to a capacitor (hereinafter, also referred to as a capacitor), even if the switching speed of the transistor controlling the supply of electric charges is increased, operations such as writing and reading are performed. The effect on speed is not great.

In the following Patent Document 1, a semiconductor memory device is described in which two word lines are connected to each other at word line parallel connection points, thereby reducing line resistance compared to conventional circuits, thereby eliminating delays in word lines.

Patent Document 1: Japanese Patent Laid-Open No. 05-266670

As described in Patent Document 1, the speed of writing or reading can be increased by lowering the resistance of wiring such as a word line. However, in the semiconductor memory device described in Patent Document 1, it is necessary to increase the ratio of the number of wirings such as bit lines and word lines to the number of memory cells for that purpose. Therefore, the yield is liable to decrease due to defects such as disconnection and short circuit due to dust or etching problems. Also, as the number of wirings increases, the area of the cell array increases.

In addition, although DRAM is advantageous in increasing its capacity compared to other memory devices, in order to further increase the degree of integration of LSI while suppressing an increase in chip size, it is necessary to increase the storage capacity per unit area like other memory devices. However, when the area of the memory cell is reduced, the capacitance value of the capacitor element decreases, so that the difference in the amount of charge between the digital values decreases, and it is necessary to increase the frequency of the refresh operation. Further, if the number of refresh operations is increased, power consumption of the memory device increases, resulting in a decrease in reliability due to deterioration of the transistor. Particularly, when the transistor is miniaturized in order to reduce the area of the memory cell, the reduction in reliability becomes significant.

One of the problems of the present invention is to provide a storage device capable of realizing high-speed operation. Alternatively, in the present invention, one of the problems is to provide a storage device capable of reducing the frequency of the refresh operation.

Alternatively, in the present invention, one of the problems is to provide a semiconductor device capable of realizing high-speed operation. Alternatively, in the present invention, one of the problems is to provide a semiconductor device capable of preventing a decrease in reliability while increasing a storage capacity per unit area of the memory device.

In the memory device according to an aspect of the present invention, any of a plurality of memory cells among a plurality of memory cells of a cell array is connected to one wiring such as a word line or a data line. Further, in one aspect of the present invention, the supply of a potential from the driving circuit to the wiring such as a word line or a data line is not performed outside the cell array, but inside the cell array or to one wiring. It is performed between any two memory cells among the plurality of connected memory cells.

Accordingly, in one aspect of the present invention, when paying attention to one wiring, a potential is applied from the wiring to a location (feeding point) where a potential is supplied from a driving circuit to the wiring, and a memory cell located at the end of the cell array. It is possible to narrow the spacing of the supplied points (feeding points). Accordingly, even if a potential drop occurs in the wiring due to the resistance of the wiring, the potential difference occurring between the two locations can be suppressed to be small.

Further, when the wiring is a word line, a potential of a signal for selecting a memory cell from a driving circuit is supplied to the word line. Alternatively, when the wiring is a data line, a potential of a signal including data is supplied from a driving circuit to the data line.

In one aspect of the present invention, a cell array is provided on the driving circuit, and each of the plurality of memory cells of the cell array includes a switching element, and the supply, maintenance, and discharge of electric charges are controlled by the switching element. It has a capacitive element. In addition, the transistor used as the switching element includes a semiconductor in a channel formation region having a wider band gap than silicon and a lower intrinsic carrier density than silicon. Examples of such semiconductors include oxide semiconductors, silicon carbide, gallium nitride, and the like having a band gap that is twice as large as that of silicon. The transistor having the semiconductor can have an off current very low compared to a transistor formed of a conventional semiconductor such as silicon or germanium. Therefore, by using the transistor having the above-described configuration as a switching element for holding the electric charge introduced into the capacitor element, leakage of electric charge from the capacitor element can be prevented.

The highly purified oxide semiconductor (purified OS) is infinitely close to i-type (intrinsic semiconductor) or i-type by reducing impurities such as moisture or hydrogen, which are electron donors (donors), and reducing oxygen vacancies. Therefore, the transistor using the oxide semiconductor has a characteristic that the off current is remarkably low. Specifically, the highly purified oxide semiconductor has a hydrogen concentration measured by secondary ion mass spectrometry (SIMS) of less than 5×10 ¹⁸ /cm ³ , more preferably 5×10 ¹⁷ /cm ³ or less, more preferably 1×10 ¹⁶ /cm ³ or less. In addition, the carrier density of the oxide semiconductor film that can be measured by Hall effect measurement is less than 1×10 ¹⁴ /cm ³ , preferably less than 1×10 ¹² /cm ³ , and more preferably less than 1×10 ¹¹ /cm ³ To do. Further, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By using an oxide semiconductor film that has been sufficiently reduced in the concentration of impurities such as moisture or hydrogen to be highly purified, the off current of the transistor can be reduced.

Here, the analysis of the hydrogen concentration in the oxide semiconductor film is mentioned. The hydrogen concentration in the semiconductor film is measured by SIMS. In the SIMS, it is known that it is difficult to accurately obtain data in the vicinity of the sample surface or in the vicinity of the lamination interface with films of different materials in principle. Therefore, when the distribution of the hydrogen concentration in the film in the thickness direction is analyzed by SIMS, the average value in the region where there is no extreme fluctuation in the value within the range of the target film, and an almost constant value is adopted as the hydrogen concentration. do. In addition, when the thickness of the film to be measured is small, it is affected by the hydrogen concentration in the vertically adjoining film, so that a region in which a substantially constant value is obtained may not be found. In this case, the maximum or minimum value of the hydrogen concentration in the region where the film is present is adopted as the hydrogen concentration in the film. In addition, in the region where the film is present, when there are no peaks in the shape of an mountain having a maximum value or a peak in the shape of a curve having a minimum value, the value of the inflection point is adopted as the hydrogen concentration.

Specifically, it can be proved by various experiments that the off-current of a transistor using a highly purified oxide semiconductor film as an active layer is low. For example, even in a device with a channel width of 1×10 ⁶ μm and a channel length of 10 μm, the off current is the measurement limit of the semiconductor parameter analyzer in the range of 1 V to 10 V between the source electrode and the drain electrode (drain voltage). In other words, a characteristic of 1 × 10 ^-13 A or less can be obtained. In this case, it can be seen that the off current density corresponding to the value obtained by dividing the off current by the channel width of the transistor is 100zA/μm or less. In addition, the off-current density was measured using a circuit that connects the capacitor and the transistor and controls the charge supplied to or discharged from the capacitor by the transistor. In this measurement, the oxide semiconductor film made highly purified in the transistor was used as a channel formation region, and the off-current density of the transistor was measured from the change in the amount of charge per unit time of the capacitor element. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor was 3 V, a lower off-current density of several tens of yA/μm was obtained. Therefore, a transistor using a highly purified oxide semiconductor film as an active layer has a significantly lower off current than a transistor using silicon having crystallinity.

In addition, unless otherwise noted, in the present specification, the off current refers to an n-channel transistor, in a state in which the drain electrode is at a higher potential than that of the source electrode and the gate electrode. When the potential is 0 or less, it means a current flowing between the source electrode and the drain electrode. Alternatively, in the present specification, the off current is, in a p-channel transistor, when the potential of the gate electrode is 0 or more when the potential of the source electrode is set to a lower potential than that of the source electrode and the gate electrode, It means a current flowing between the source electrode and the drain electrode.

For example, indium oxide, tin oxide, zinc oxide as oxide semiconductors, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide as an oxide semiconductor Oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also referred to as IGZO), an oxide of ternary metal, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In- Pr-Zn type oxide, In-Nd-Zn type oxide, In-Sm-Zn type oxide, In-Eu-Zn type oxide, In-Gd-Zn type oxide, In-Tb-Zn type oxide, In-Dy- Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, quaternary metal oxide In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxides can be used. In addition, the oxide semiconductor may contain silicon.

In addition, for example, an In-Ga-Zn-based oxide means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is irrelevant. Moreover, metal elements other than In, Ga, and Zn may be included. The In-Ga-Zn-based oxide is suitable as a semiconductor material for use in a semiconductor device because its resistance is sufficiently high at the time of non-electric field, and the off current can be sufficiently low and its mobility is also high.

In one aspect of the present invention, since the difference in electric potential supplied between a plurality of memory cells connected to one wiring can be suppressed in a shorter time, operation speed such as writing or reading data can be increased.

Further, in one aspect of the present invention, since the cell array is provided on the driving circuit, the size of the entire memory device including the driving circuit and the cell array can be reduced. And, as described above, since the transistor having a remarkably low off current is used for the switching element, leakage of charge from the capacitor element can be prevented, and the frequency of the refresh operation can be suppressed to a low level. Accordingly, the power consumption of the memory device can be suppressed to be small, and a decrease in reliability due to deterioration of the transistor can be prevented. Further, by suppressing the frequency of the refresh operation to be low, high-speed operation of the memory device and the semiconductor device can be realized.

1 is a diagram showing a configuration of a storage device.
2 is a circuit diagram of a cell array.
3 is a timing chart showing the operation of the cell array.
Fig. 4 is a block diagram showing the configuration of a storage device.
Fig. 5 is a diagram showing the configuration of a read circuit.
6A to 6D are diagrams showing a method of manufacturing a storage device.
7A to 7C are diagrams showing a method of manufacturing a storage device.
8A to 8C are diagrams showing a method of manufacturing a storage device.
9A to 9D are diagrams showing the configuration of a transistor.
10A to 10D are diagrams showing the configuration of a transistor.
11A to 11C are diagrams of an electronic device.
12 is a cross-sectional view of a memory device.
13A to 13E are examples of oxide semiconductors.
14A to 14C are examples of an oxide semiconductor.
15A to 15C are examples of an oxide semiconductor.
16 is a relationship between gate voltage and mobility.
17A to 17C show the relationship between the gate voltage and the drain current.
18A to 18C show the relationship between the gate voltage and the drain current.
19A to 19C show the relationship between the gate voltage and the drain current.
20A to 20C are characteristics of a transistor.
21 (a) and (b) are transistor characteristics.
Figure 22 (a) and (b) are the characteristics of the transistor.
Fig. 23 is a temperature dependence of the transistor off current.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, it is easily understood by those skilled in the art that the present invention is not limited to the following description, and that the form and detail can be variously changed without departing from the spirit and scope of the present invention. Therefore, this invention is not interpreted as being limited to the description content of the embodiment described below.

In addition, various semiconductor devices that can use a storage device such as a microprocessor, an image processing circuit, a digital signal processor (DSP), an integrated circuit such as a microcontroller, a storage medium such as an RF tag, a memory card, and a semiconductor display device are provided. Are included in the category of. In addition, in the semiconductor display device, a light emitting device including a light emitting device represented by a liquid crystal display device, an organic light emitting device (OLED) in each pixel, electronic paper, a digital micromirror device (DMD), a plasma display panel (PDP), and a FED ( Field Emission Display), etc., and other semiconductor display devices having circuit elements using a semiconductor film in a driving circuit are included in the category.

(Embodiment 1)

1 shows a configuration of a storage device according to an aspect of the present invention. The memory device shown in FIG. 1 has a cell array 101 in which a plurality of memory cells 100 are arranged in a matrix, and a driving circuit 102 provided below the cell array 101.

Further, the cell array 101 is provided with a plurality of wirings for supplying various potentials to each memory cell 100. Specifically, a plurality of word lines WL and a plurality of data lines DL are provided in the cell array 101 shown in FIG. 1.

In addition, the number of wires can be determined by the number and arrangement of the memory cells 100 in the cell array 101. Specifically, in FIG. 1, the memory cells 100 of x columns x y rows are connected in a matrix, and word lines WL1 to WLy and data lines DL1 to DLx are arranged in the cell array 101. The case is illustrated. Further, each memory cell 100 is connected to one of the plurality of data lines DL1 to DLx and to one of the plurality of word lines WL1 to WLy.

Further, the driving circuit 102 includes a word line driving circuit 103 that selects a word line WL by supplying at least a potential to the word line WL, and a memory connected to the selected word line WL. It has a data line driving circuit 104 that controls data writing in the cell 100. Further, the data line drive circuit 104 may have a read circuit for reading data.

The word line driving circuit 103 and the data line driving circuit 104 write data to the cell array 101, read data from the cell array 101, hold data in the cell array 101, etc. The various operations of can be controlled according to signals from the control circuit. In addition, in Fig. 1, a case where the control circuit for supplying signals to the word line driving circuit 103 and the data line driving circuit 104 is not included in the driving circuit 102 and is provided outside the memory device. Although assumed, the control circuit may be included in the constituent elements of the drive circuit 102.

The potential of the signal from the driving circuit 102 is supplied to each memory cell 100 through a plurality of word lines WL and a plurality of data lines DL. Specifically, the potential of the signal from the word line driving circuit 103 is supplied to each of the plurality of word lines WL. Further, the potential supplied to one word line WL is supplied to a plurality of memory cells 100 for one row connected to the one word line WL. Further, specifically, the potential of the signal from the data line driving circuit 104 is supplied to each of the plurality of data lines DL. In addition, a potential supplied to one data line DL is supplied to one selected memory cell 100 among a plurality of memory cells 100 for one row connected to the one data line DL.

In one aspect of the present invention, the supply of potentials from the driving circuit 102 to various wirings such as the word line WL or the data line DL is not external to the cell array 101 but the cell array 101 ) Inside or between the memory cells 100. Specifically, in FIG. 1, a signal from the word line driving circuit 103 between the memory cell 100 connected to the data line DL4 and the memory cell 100 connected to the data line DLx-3 The case where the potential of is supplied to the word lines WL1 to WLy is illustrated. In addition, in FIG. 1 specifically, between the memory cell 100 connected to the word line WL4 and the memory cell 100 connected to the word line WLy-3, the data line driving circuit 104 The case where the potential of the signal is supplied to the data lines DL1 to DLx is illustrated.

In Fig. 1, a power supply point 105, which is a location where a potential is supplied from the word line driving circuit 103 to the word lines WL1 to WLy, is indicated by a white circle. In addition, a power supply point 106, which is a location where a potential is supplied from the data line driving circuit 104 to the data lines DL1 to DLx, is indicated by a white circle.

In addition, although FIG. 1 illustrates the case where the power supply point 105 and the power supply point 106 are provided between the memory cells 100, in one aspect of the present invention, at least inside the cell array 101 The feeding point 105 or the feeding point 106 may be provided.

In addition, although FIG. 1 illustrates the case where the feeding point 105 and the feeding point 106 are installed inside the cell array 101, in one aspect of the present invention, the feeding point 105 and the feeding point Any one of (106) may be provided inside the cell array 101.

In addition, there are cases in which a plurality of conductive films in contact with each other function as one wiring, or a case in which one conductive film has a function as a wiring and a function as an electrode of a semiconductor element. Therefore, it is difficult to completely separate one wiring from another component. In this specification, the position of the power supply point where the electric potential is supplied from the driving circuit to the wiring is an insulating film provided between the layer in which the driving circuit 102 is formed and the layer in which the cell array 101 is formed, the driving circuit It can be regarded as the location of the contact hole where the connection between the wire and the wire is made.

For example, of the memory cells 100 connected to the word line WL1, a potential from the word line WL1 to the first or x-row memory cell 100 located at the end of the cell array 101 The points to which are supplied are referred to as a feeding point 107 and a feeding point 108, respectively. In the case of a general configuration in which a potential is supplied to the word line WL or the data line DL from the outside of the cell array 101, a power supply point at which a potential is supplied from the word line driving circuit 103 to the word line WL1 (X) (not shown) exists at the end of the cell array 101. Therefore, the spacing between the feeding point X and the feeding point 107 and the spacing between the feeding point X and the feeding point 108 have a large difference. On the other hand, in the case of one aspect of the present invention, the supply of the potential to the word line WL or the data line DL is not performed outside the cell array 101, but inside the cell array 101 or the memory It is done between the cells 100. Therefore, paying attention to the word line WL1, the power supply point 105 to which a potential is supplied from the word line driving circuit 103 to the word line WL1 exists inside the cell array 101, and thus power is supplied. The difference between the spacing between the point 105 and the feeding point 107 and the spacing between the feeding point 105 and the feeding point 108 is smaller than that of the general configuration. Therefore, even if a potential drop occurs in the word line WL1 due to the resistance of the word line WL1, the potential difference between the feeding point 107 and the feeding point 108 is compared with the case of the general configuration. I can suppress it small.

In the case of the word line WL other than the word line WL1 or the data line DL, similarly, a feed point at which a potential is supplied from the driving circuit 102 to the wiring, and the end of the cell array 101 A potential difference between feeding points to which a potential is supplied from the wiring to the memory cell 100 positioned at may be suppressed to be small. Accordingly, the potential difference between the memory cells 100 located at the ends at the feeding points can be suppressed to be small.

Therefore, between the plurality of memory cells 100 connected to one word line WL or data line DL, the difference in the supplied potential can be suppressed in a shorter time, so that data writing or reading, etc. Can increase the speed of operation.

Further, in one aspect of the present invention, since the cell array 101 is provided on the driving circuit 102, the size of the entire memory device including the driving circuit 102 and the cell array 101 can be reduced. have.

Next, Fig. 2 shows an example of a specific circuit diagram of the cell array 101 shown in Fig. 1. In the cell array 101 shown in FIG. 2, various wirings such as a plurality of word lines WL, a plurality of data lines DL, and a plurality of capacitor lines CL are provided, and signals from the driving circuit are A potential or a power source potential is supplied to each memory cell 100 through these wirings.

Specifically, in Fig. 2, the power supply point 105, which is a location where a potential is supplied from the word line driving circuit to the word lines WL1 to WLy, is indicated by a white circle. In addition, a power supply point 106, which is a location where a potential is supplied from the data line driving circuit to the data lines DL1 to DLx, is indicated by a white circle.

The memory cell 100 has a transistor 109 and a capacitor 110 functioning as a switching element. In the memory cell 100 shown in FIG. 2, data is stored by accumulating electric charges in the capacitor element 110.

In addition, the method of designating the source terminal and the drain terminal of the transistor changes depending on the polarity of the transistor and the level of the potential supplied to each electrode. In general, in an n-channel transistor, an electrode to which a low potential is supplied is called a source terminal, and an electrode to which a high potential is supplied is called a drain terminal. In a p-channel transistor, an electrode to which a low potential is supplied is called a drain terminal, and an electrode to which a high potential is supplied is called a source terminal. Hereinafter, a connection relationship between the transistor 109 and the capacitor 110 included in the memory cell 100 will be described with one of the source terminal and the drain terminal as a first terminal and the other as a second terminal.

Specifically, the first terminal of the transistor 109 is connected to one of the plurality of data lines DL. The gate electrode of the transistor 109 is connected to one of a plurality of word lines WL. Among the pair of electrodes of the capacitor element 110, one electrode different from the electrode connected to the second terminal of the transistor 109 is connected to one of the plurality of capacitor lines CL.

The memory cell 100 may further include other circuit elements such as a transistor, a diode, a resistance element, a capacitor element, and an inductor as necessary.

In addition, the number of wires may be determined by the number and arrangement of the memory cells 100. Specifically, in the case of the cell array 101 shown in Fig. 2, the memory cells 100 in x columns x y rows are connected in a matrix shape, and word lines WL1 to WLy and data lines DL1 to DLx , The case where the capacitor lines CL1 to CLy are arranged in the cell array 101 is illustrated.

In addition, the source terminal of the transistor means a source region or a source electrode. Similarly, the drain terminal of the transistor means a drain region or a drain electrode.

In this specification, the connection means an electrical connection, and corresponds to a state in which current, voltage, or potential can be supplied or transmitted. Therefore, the connected state does not necessarily refer to the state that is directly connected, but is indirectly connected through elements such as wiring, conductive films, resistors, diodes, and transistors so that current, voltage, or potential can be supplied or transmitted. The state that you are doing is also included in that category.

In addition, even when independent constituent elements are connected on the circuit diagram, in practice, one conductive film may have functions of a plurality of constituent elements together, for example, when a part of the wiring functions as an electrode. . In the present specification, connection is also included in the category when such one conductive film has functions of a plurality of constituent elements.

In addition, although FIG. 2 illustrates a case in which the transistor 109 has a single gate structure, the transistor 109 may have a multi-gate structure having a plurality of channel formation regions by having a plurality of gate electrodes electrically connected. .

In one aspect of the present invention, a semiconductor material having a wider band gap than silicon and a lower intrinsic carrier density than silicon is included in the channel formation region of the transistor 109 functioning as the switching element. By including the semiconductor material having the above-described characteristics in the channel formation region, it is possible to realize the transistor 109 having a very low off current.

As in the memory cell 100 shown in Fig. 2, when data is stored by controlling the amount of electric charge, the supply of electric charge to the memory cell 100, discharge of electric charge from the memory cell 100, and memory The retention of charge in the cell 100 is controlled by the transistor 109 functioning as a switching element. Accordingly, the length of the data retention time depends on the amount of charge accumulated in the memory cell 100 leaks through the transistor 109. In one aspect of the present invention, since the off current of the transistor 109 can be significantly reduced as described above, the charge leakage can be prevented and the data retention time can be long. Therefore, since the frequency of the refresh operation can be suppressed low, the power consumption of the memory device can be suppressed to be small, and a decrease in reliability due to deterioration of the transistor can be prevented. Further, by suppressing the frequency of the refresh operation to be low, high-speed operation of the memory device and the semiconductor device can be realized.

In addition, as an example of a semiconductor having a wider band gap than a silicon semiconductor and a lower intrinsic carrier density than silicon, a compound semiconductor such as silicon carbide (SiC) and gallium nitride (GaN), and an oxide made of a metal oxide such as zinc oxide (ZnO). Semiconductors and the like can be applied. Compound semiconductors such as silicon carbide or gallium nitride are essential to be single crystals, and in order to obtain a single crystal material, crystal growth at a temperature significantly higher than the process temperature of the oxide semiconductor or epitaxial growth on a special substrate is required, or manufacturing conditions are required. It is strict, and it is difficult to form a film on a silicon wafer or glass substrate having low heat resistance. However, oxide semiconductors can be produced by a sputtering method or a wet method (such as a printing method), and thus have an advantage in that they are excellent in mass production. Further, since the oxide semiconductor can be formed even at room temperature, it is possible to form a film on a glass substrate or an integrated circuit using a semiconductor element, so that the substrate can be enlarged. Therefore, among the above-described wide gap semiconductors, particularly, oxide semiconductors have an advantage of high mass production. In addition, even when obtaining a crystalline oxide semiconductor in order to improve the performance (for example, mobility) of a transistor, a crystalline oxide semiconductor can be obtained by heat treatment at 200°C to 800°C.

In the following description, as the semiconductor film of the transistor 109, a case where an oxide semiconductor having the above advantages is used is taken as an example.

In addition, although FIG. 2 shows a configuration in which the memory cell 100 has only one transistor 109 functioning as a switching element, the present invention is not limited to this configuration. In one aspect of the present invention, at least one transistor functioning as a switching element may be provided in each memory cell, and the number of the transistors may be plural. When the memory cell 100 has a switching element composed of a plurality of transistors, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in combination in series and parallel.

In addition, in the present specification, the state in which the transistors are connected in series means, for example, that only one of the first terminal and the second terminal of the first transistor is one of the first terminal and the second terminal of the second transistor. It means that it is connected to only one side. In addition, the state in which the transistors are connected in parallel means that the first terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the first transistor is connected to the second terminal of the second transistor. Means state.

In addition, the transistor 109 needs to have at least the gate electrode on one side of the active layer, but may have a pair of gate electrodes present through the active layer. When the transistor 109 has a pair of gate electrodes present with an active layer therebetween, a signal for controlling switching is supplied to one gate electrode, and the other gate electrode (back gate electrode) is electrically It may be in a floating state that is insulated from the other, or a state in which a potential is supplied from another. In the latter case, a potential of the same height may be supplied to the pair of electrodes, or a fixed potential such as a ground potential may be supplied only to the back gate electrode. By controlling the height of the potential applied to the back gate electrode, the threshold voltage of the transistor 109 can be controlled.

In addition, in one aspect of the present invention, at least the transistor 109 functioning as a switching element should have a wide gap semiconductor material such as the oxide semiconductor described above in the active layer. On the other hand, as the transistor included in the driving circuit, an oxide semiconductor may be used for its active layer, or a semiconductor other than an oxide semiconductor, such as amorphous, microcrystalline, polycrystalline or single crystal silicon or germanium, may be used. By using an oxide semiconductor film for the active layers of all transistors in the memory device, the process can be simplified. Further, by using a semiconductor material having a higher mobility than an oxide semiconductor, such as polycrystalline or single crystal silicon, for the active layer of the transistor included in the driving circuit, the operation of the memory device can be performed at high speed.

Next, a typical operation of the cell array 101 shown in FIG. 2 will be described using the timing chart of FIG. 3. 3, the memory cell 100 in the first column and the first row, the memory cell 100 in the first row of the x-column, the memory cell 100 in the first column and the y-th row, and the memory cell in the y-th row of the x-column ( In 100), the case of writing, holding, and reading data is taken as an example.

The operation of the cell array 101 in the writing period Ta will be described. Data is written for each row. In FIG. 3, data is first written to the memory cell 100 in the first row in the first column and the memory cell 100 in the first row in the first column, and then, the memory cell 100 in the first column y and the x column y A case of writing data to the memory cell 100 in the row is illustrated.

Further, in the writing period Ta, the ground potential is supplied to all the capacitor lines CL.

First, the word line WL1 connected to the memory cell 100 in the first row to be written is selected. Specifically, in FIG. 3, a high-level potential VH is supplied to the word line WL1, and a ground potential GND is supplied to the other word lines WL including the word line WLy. Therefore, only the transistor 109 to which the gate electrode is connected to the word line WL1 is selectively turned on.

Then, in the period in which the word line WL1 is selected, a potential of a signal including data is supplied to the data line DL1 and the data line DLx. The level of the potential supplied to the data line DL1 and the data line DLx naturally differs depending on the contents of the data. In FIG. 3, a case where the high level potential VDD is supplied to the data line DL1 and the ground potential GND is supplied to the data line DLx is illustrated. Potentials supplied to the data line DL1 and the data line DLx are supplied to one of the electrodes of the capacitor element 110 through the ON transistor 109.

In addition, the potential VH is assumed to be equal to or higher than the potential VDD. Specifically, it is assumed that the potential difference between the potential VH and the potential VDD is equal to or greater than the threshold voltage of the transistor 109.

Assuming that one electrode of the capacitive element 110 is a node FG, the potential of the node FG is the memory cell of the first column and the first row according to the potential supplied to the data line DL1 and the data line DLx. It becomes a potential VDD at 100) and a ground potential GND at the memory cell 100 in the first row of column x. Further, by controlling the amount of charge supplied to the capacitor 110 according to the potential of the node FG, writing of data to the memory cell 100 in the first column and the first row in the first column and the memory cell 100 in the first row of the x column is performed. Done.

Next, the ground potential GND is supplied to the word line WL1. Accordingly, the transistor 109 to which the gate electrode is connected to the word line WL1 is turned off, and charge is held in the capacitor element 110.

In addition, when an oxide semiconductor is used for the semiconductor film of the transistor 109, the transistor 109 has a characteristic that the off current is very low. Accordingly, leakage of charges held in the capacitor 110 can be prevented, and data can be retained over a longer period of time compared to the case where a semiconductor such as silicon is used for the transistor 109.

Next, the word line WLy connected to the y-th memory cell 100 for writing is selected. Specifically, in FIG. 3, a high-level potential VH is supplied to the word line WLy, and a ground potential GND is supplied to other word lines WL including the word line WL1. Therefore, only the transistor 109 to which the gate electrode is connected to the word line WLy is selectively turned on.

Then, in the period in which the word line WLy is selected, a potential of a signal including data is supplied to the data line DL1 and the data line DLx. The level of the potential supplied to the data line DL1 and the data line DLx naturally differs depending on the contents of the data. In FIG. 3, a case where the ground potential GND is supplied to the data line DL1 and the high level potential VDD is supplied to the data line DLx is illustrated. Potentials supplied to the data line DL1 and the data line DLx are supplied to one of the electrodes of the capacitor element 110 through the ON transistor 109. Depending on the potential supplied to the data line DL1 and the data line DLx, the potential of the node FG becomes the ground potential GND in the memory cell 100 in the y-th row in the first column, and the memory in the y-th row in the x column. In the cell 100, it becomes a potential VDD. Further, by controlling the amount of charge supplied to the capacitor element 110 according to the potential of the node FG, writing of data to the memory cell 100 in the y-th row in the first column and the memory cell 100 in the y-th row in the first column is performed. Done.

Next, the ground potential GND is supplied to the word line WLy. Accordingly, the transistor 109 to which the gate electrode is connected to the word line WLy is turned off, and charge is retained in the capacitor element 110.

In addition, in order to prevent erroneous data from being written to the memory cell 100, it is preferable to stop supplying the potential including data to the data line DL after selection of each word line WL is finished. Do.

Next, the operation of the cell array 101 in the data retention period Ts will be described.

In the sustain period Ts, the ground potential is supplied to all the capacitor lines CL.

Further, in the sustain period Ts, a potential at a level at which the transistor 109 is turned off, specifically a ground potential GND, is supplied to all word lines WL. Thus, data is maintained while the charge supplied to the capacitive element 110 is maintained.

Next, the operation of the cell array 101 in the data reading period Tr will be described.

In the read period Tr, the ground potential is supplied to all the capacitor lines CL.

Then, in the read period Tr, the potential VR of the intermediate level is supplied to the data line DL connected to the memory cell 100 for reading. Specifically, in FIG. 3, an intermediate potential VR is supplied to the data line DL1 connected to the memory cell 100 in the first column and the data line DLx connected to the memory cell 100 in the x column. do. Further, the potential VR is assumed to be the same as the potential VDD or lower than the potential VDD and higher than the ground potential GND. Then, after the potential VR is supplied, both the data line DL1 and the data line DLx are in a floating state.

Next, the word line WL1 connected to the memory cell 100 in the first row to be read is selected. Specifically, in FIG. 3, a high-level potential VH is supplied to the word line WL1, and a ground potential GND is supplied to other word lines including the word line WLy. Therefore, only the transistor 109 to which the gate electrode is connected to the word line WL1 is selectively turned on.

When the transistor 109 is turned on, the charge held in the capacitor 110 is discharged to the data line DL for reading, or the charge is transferred to the capacitor 110 from the data line DL for reading. Is supplied. This operation is determined according to the potential of the node FG in the sustain period.

Specifically, in the case of the timing chart shown in Fig. 3, in the immediately preceding sustain period, the node FG in the memory cell 100 in the first column and first row is the potential VDD. Accordingly, when the transistor 109 is turned on in the read period, electric charges are discharged from the capacitor 110 in the memory cell 100 in the first column and first row to the data line DL1. The potential increases and becomes the potential VR + α. Further, in the immediately preceding sustain period, the node FG in the memory cell 100 in the first row of the x-column is the ground potential GND. Accordingly, when the transistor 109 is turned on in the read period, electric charges are supplied from the data line DLx to the capacitor 110 in the memory cell 100 in the first row of column x, so that the data line DLx is The potential is lowered and becomes a potential (VR)-β.

Accordingly, the potentials of the data line DL1 and the data line DLx are based on the amount of electric charge held in the capacitor 110 of the memory cell 100 in the first column and the first row and the memory cell 100 in the first row of the x column. It becomes the height according to it. Further, data can be read from the memory cell 100 in the first column and the first row and the memory cell 100 in the first row of the x-column by reading the difference in the amount of charge from the potential.

Next, when reading of data from the memory cell 100 in the first column and the first row and the memory cell 100 in the first row of column x is finished, the potential of the intermediate level is again applied to the data line DL1 and the data line DLx. After (VR) is assigned, the data line DL1 and the data line DLx are in a floating state.

Then, the word line WLy connected to the memory cell 100 in the first row to be read is selected. Specifically, in FIG. 3, a high-level potential VH is supplied to the word line WLy, and a ground potential GND is supplied to other word lines including the word line WL1. Therefore, only the transistor 109 to which the gate electrode is connected to the word line WLy is selectively turned on.

When the transistor 109 is turned on, the charge held in the capacitor 110 is discharged to the data line DL for reading, or the charge from the data line DL for reading is transferred to the capacitor 110 Is supplied to. This operation is determined by the potential of the node FG in the sustain period.

Specifically, in the case of the timing chart shown in Fig. 3, in the immediately preceding sustain period, the node FG in the memory cell 100 in the first column and y row is the ground potential GND. Therefore, when the transistor 109 is turned on in the read period, since the charge from the data line DL1 is supplied to the capacitor 110 in the memory cell 100 in the first column and y-th row, the data line DL1 The potential of is lowered to become a potential (VR)-β. Further, in the immediately preceding sustain period, the node FG in the memory cell 100 in the x-column y-th row is the potential VDD. Therefore, when the transistor 109 is turned on in the read period, electric charges are discharged from the capacitor 110 in the memory cell 100 in the x-column y-th row to the data line DLx. The potential increases and becomes the potential VR + α.

Accordingly, the potentials of the data line DL1 and the data line DLx depend on the amount of electric charge held in the capacitor 110 of the memory cell 100 in the y-th row in the first column and the memory cell 100 in the y-th row in the x column. It becomes the height according to it. Further, data can be read from the memory cell 100 in the y-th row in the first column and the memory cell 100 in the y-th row in the first column by reading the difference in the amount of charge from the potential.

In front of each data line DL, a read circuit included in the data line driving circuit is connected, and the output signal of the read circuit includes data read from the cell array 101.

(Embodiment 2)

An example of a specific configuration of a drive circuit of a memory device will be described.

In Fig. 4, a block diagram is shown as an example of a specific configuration of a storage device. In addition, in the block diagram shown in Fig. 4, circuits in the memory device are classified for each function and shown as independent blocks from each other, but it is difficult to completely separate the actual circuit for each function, and one circuit may be related to a plurality of functions. have.

The memory device 800 shown in FIG. 4 has a cell array 801 and a drive circuit 802. The driving circuit 802 includes an input/output buffer 803, a word line driving circuit 804 for controlling a potential of a word line, a data line driving circuit 805 for controlling writing and reading of data in a memory cell, and It has an input/output buffer 803, a word line driving circuit 804, and a control circuit 806 that controls the operation of the data line driving circuit 805.

Further, in the memory device 800 shown in FIG. 4, the word line driving circuit 804 has a row decoder 807, a level shifter 808, and a buffer 809. The data line driving circuit 805 has a column decoder 810, a level shifter 811, a selector 812, and a read circuit 813.

In addition, the cell array 801, the input/output buffer 803, the word line driving circuit 804, the data line driving circuit 805, and the control circuit 806 may all be formed using a single substrate. One or all of them may be formed using different substrates.

When different boards are used, electrical connection between different boards can be secured through FPC (Flexible Printed Circuit) or the like. In this case, a part of the drive circuit 802 may be connected to the FPC using a chip on film (COF) method. Alternatively, electrical connection can be secured using the COG (Chip On Glass) method.

When a signal AD including the address Ax and the address Ay of the cell array 801 as information is input to the memory device 800, the control circuit 806 returns the address Ax in the column direction. It is sent to the data line driving circuit 805, and an address Ay in the row direction is sent to the word line driving circuit 804. Further, the control circuit 806 sends a signal DATA including data input to the storage device 800 via the input/output buffer 803 to the data line driving circuit 805.

Selection of the data writing operation and the reading operation in the cell array 801 is selected by a signal RE (Read enable), a signal WE (Write enable), or the like supplied to the control circuit 806. Further, when a plurality of cell arrays 801 exist, a signal CE (Chip enable) for selecting the cell array 801 may be input to the control circuit 806. In this case, the operation selected by the signal RE and the signal WE is executed in the cell array 801 selected by the signal CE.

In the cell array 801, when the write operation is selected by the signal WE, in accordance with the instruction from the control circuit 806, the row decoder 807 of the word line driving circuit 804 receives the address Ay. A signal is generated for selecting the corresponding memory cell. The corresponding signal is input to the cell array 801 through the buffer 809 after the amplitude is adjusted by the level shifter 808. On the other hand, in the data line driving circuit 805, in response to an instruction from the control circuit 806, a signal for selecting a memory cell corresponding to the address Ax from among the memory cells selected by the column decoder 810 is generated. do. The signal is input to the selector 812 after the amplitude is adjusted by the level shifter 811. The selector 812 samples the signal DATA according to the input signal, and inputs the sampled signal into the memory cells corresponding to the addresses Ax and Ay.

Further, in the cell array 801, when the read operation is selected by the signal RE, in accordance with the instruction from the control circuit 806, in the row decoder 807 of the word line driving circuit 804, the address (Ay A signal for selecting a memory cell corresponding to) is generated. The corresponding signal is input to the cell array 801 through the buffer 809 after the amplitude is adjusted by the level shifter 808. On the other hand, the read circuit 813 selects a memory cell corresponding to the address Ax from among the memory cells selected by the row decoder 807 in accordance with an instruction from the control circuit 806. Then, data stored in the memory cells corresponding to the addresses Ax and Ay are read, and a signal including the data is generated.

Further, the data line driving circuit 805 may have a page buffer capable of temporarily storing signal DATA, a precharge circuit that applies a potential VR to the data line in advance when reading data, or the like.

This embodiment can be implemented in appropriate combination with the above embodiment.

(Embodiment 3)

Next, a specific configuration example of the read circuit will be described.

The level of the potential read from the cell array is determined according to the data written to the memory cell. Therefore, ideally, if data of the same digital value is stored in a plurality of memory cells, all potentials read from the plurality of memory cells are at the same level. However, in practice, the characteristics of a transistor functioning as a capacitor or a switching device may fluctuate between memory cells. In this case, even if all of the data to be read are the same digital value, since a variation occurs in the potential actually read, the distribution has a width. However, the readout circuit contains accurate data even if a slight fluctuation occurs in the potential read from the cell array, and can form a signal whose amplitude and waveform are processed according to a desired specification.

5 is a circuit diagram showing a configuration example of a read circuit. The read circuit shown in Fig. 5 has a transistor 260 that functions as a switching element for controlling the input of the potential Vdata read from the cell array to the read circuit. Further, the read circuit shown in Fig. 5 has an operational amplifier 262.

The transistor 260 functioning as a switching element controls the supply of a potential Vdata to the non-inverting input terminal (+) of the operational amplifier 262 in accordance with the potential of the signal Sig supplied to its gate electrode. . For example, when the transistor 260 is turned on, the potential Vdata is supplied to the non-inverting input terminal (+) of the operational amplifier 262. On the other hand, the reference potential Vref is supplied to the inverting input terminal (-) of the operational amplifier 262. And, depending on whether the potential supplied to the non-inverting input terminal (+) is high or low with respect to the reference potential (Vref), the level of the potential (Vout) of the output terminal can be different, and accordingly, data is indirectly included. You can get a signal to do.

In addition, even in the case of a memory cell in which data of the same value is stored, the level of the read potential Vdata also fluctuates due to fluctuations in characteristics between memory cells, and the distribution may have a width. Accordingly, the level of the reference potential Vref is determined in consideration of the variation of the potential Vdata in order to accurately read the data value.

In Fig. 5, since it is an example of a read circuit in the case of handling a binary digital value, one operational amplifier used for reading data is used for each node to which the potential (Vdata) is supplied. The number is not limited to this. In the case of handling data of n values (n is a natural number of 2 or more), the number of operational amplifiers per node to which the potential Vdata is supplied is set to n-1.

This embodiment can be implemented in appropriate combination with the above embodiment.

(Embodiment 4)

In the present embodiment, in the memory cell 100 shown in Fig. 2, an oxide semiconductor is used for the active layer of the transistor 109, and silicon is used for the active layer of the transistor included in the driving circuit. The manufacturing method will be described.

However, as the transistor included in the driving circuit, semiconductor materials such as germanium, silicon germanium, single crystal silicon carbide, etc. may be used in addition to silicon. Further, for example, a transistor using silicon can be formed using a single crystal semiconductor substrate such as a silicon wafer, a silicon thin film produced by an SOI method, a silicon thin film produced by a vapor phase growth method, or the like. Alternatively, in one aspect of the present invention, an oxide semiconductor may be used for all transistors constituting the memory cell.

In this embodiment, first, an insulating film 701 and a single crystal semiconductor film 702 are formed on the substrate 700 as shown in Fig. 6A.

Although there is no great limitation on the material that can be used as the substrate 700, it is necessary to have heat resistance at least to a degree that can withstand the subsequent heat treatment. For example, as the substrate 700, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or the like manufactured by a fusion method or a float method can be used. As the glass substrate, when the temperature of the subsequent heat treatment is high, a distortion point of 730°C or higher may be used.

In addition, in the present embodiment, taking a case where the semiconductor film 702 is single crystal silicon as an example, a method of manufacturing a transistor included in the driving circuit will be described below. Further, an example of a specific method of manufacturing the single crystal semiconductor film 702 will be briefly described. First, an ion beam made of ions accelerated by an electric field is implanted into a bond substrate, which is a single crystal semiconductor substrate, to form a locally fragile embrittlement layer by disturbing the crystal structure in a region of a certain depth from the surface of the bond substrate. do. The depth of the region where the embrittlement layer is formed can be adjusted by the acceleration energy of the ion beam and the incident angle of the ion beam. Then, the bond substrate and the substrate 700 on which the insulating film 701 is formed are bonded so that the insulating film 701 is sandwiched therebetween. Junction, and then the bonded substrate and the substrate 700 overlap with each other, a portion of the bonded substrate and the substrate 700, 1N / cm ² at least 500N / cm ² or less, preferably 11N / cm ² more than 20N / cm ² or less Apply enough pressure. When pressure is applied, the bond substrate and the insulating film 701 start bonding from that portion, and finally, bonding is performed on the entire adhered surface. Next, by performing heat treatment, the minute voids existing in the embrittlement layer are bonded to each other, and the volume of the microvoids is increased. As a result, the single crystal semiconductor film, which is a part of the bond substrate in the embrittlement layer, is separated from the bond substrate. The temperature of the heat treatment is a temperature that does not exceed the distortion point of the substrate 700. Further, the semiconductor film 702 can be formed by processing the single crystal semiconductor film into a desired shape by etching or the like.

In order to control the threshold voltage, an impurity element imparting p-type conductivity such as boron, aluminum, and gallium, or an impurity element imparting n-type conductivity such as phosphorus and arsenic may be added to the semiconductor film 702. do. The addition of the impurity element for controlling the threshold voltage may be performed on the semiconductor film before patterning or on the semiconductor film 702 formed after patterning. Further, an impurity element for controlling the threshold voltage may be added to the bonded substrate. Alternatively, the impurity element is added to the bonded substrate to approximately adjust the threshold voltage, and then to the semiconductor film before patterning or to the semiconductor film 702 formed by patterning in order to finely adjust the threshold voltage. You may do it against.

In addition, in this embodiment, an example using a single crystal semiconductor film has been described, but the present invention is not limited to this configuration. For example, a polycrystalline, microcrystalline, or amorphous semiconductor film formed on the insulating film 701 by a vapor phase growth method may be used, and the semiconductor film may be crystallized by a known technique. Known crystallization methods include laser crystallization using laser light and crystallization using catalytic elements. Alternatively, a combination of a crystallization method using a catalytic element and a laser crystallization method may be used. In addition, when using a substrate with excellent heat resistance such as quartz, a crystallization method that combines a thermal crystallization method using an electric heating furnace, a lamp annealing crystallization method using infrared light, a crystallization method using a catalytic element, and a high temperature annealing method of about 950°C is used. You may use it.

Next, as shown in FIG. 6B, after forming a gate insulating film 703 on the semiconductor film 702, a gate electrode 704 is formed on the gate insulating film 703.

The gate insulating film 703 can be formed by oxidizing or nitriding the surface of the semiconductor film 702 by performing high-density plasma treatment, heat treatment, or the like. The high-density plasma treatment is performed using, for example, a rare gas such as He, Ar, Kr, and Xe, and a mixed gas such as oxygen, nitrogen oxide, ammonia, nitrogen and hydrogen. In this case, by performing plasma excitation by introducing microwaves, high-density plasma can be generated at a low electron temperature. By oxidizing or nitriding the surface of the semiconductor film by oxygen radicals (in some cases containing OH radicals) or nitrogen radicals (in some cases containing NH radicals) generated in such a high-density plasma, 1 to 20 nm, preferably May be formed such that an insulating film of 5 to 10 nm is in contact with the semiconductor film. For example, nitrogen oxide (N ₂ O) is diluted 1 to 3 times (flow rate) with Ar, and microwave (2.45 GHz) power of 3 kW to 5 kW is applied at a pressure of 10 Pa to 30 Pa, and the semiconductor film 702 is Oxidize or nitrify the surface. An insulating film of 1 nm to 10 nm (preferably 2 nm to 6 nm) is formed by this treatment. In addition, nitrogen oxide (N ₂ O) and silane (SiH ₄ ) were introduced, and a 3 kW to 5 kW microwave (2.45 GHz) power was applied at a pressure of 10 Pa to 30 Pa to form a silicon oxynitride film by a vapor phase growth method. An insulating film is formed. By combining the solid-phase reaction and the reaction by the vapor phase growth method, it is possible to form a gate insulating film having a low interface state density and excellent dielectric breakdown voltage.

Since the oxidation or nitridation of the semiconductor film by the high-density plasma treatment described above proceeds in a solid phase reaction, the density of the interface states between the gate insulating film 703 and the semiconductor film 702 can be made very low. Further, by directly oxidizing or nitriding the semiconductor film 702 by high-density plasma treatment, it is possible to suppress variations in the thickness of the formed insulating film. In addition, when the semiconductor film has crystallinity, the surface of the semiconductor film is oxidized by a solid-phase reaction using high-density plasma treatment, thereby suppressing rapid oxidation only at the grain boundary, and thus a gate with good uniformity and low density of interfacial states. An insulating film can be formed. A transistor formed by including an insulating film formed by high-density plasma processing in a part or all of the gate insulating film can suppress variations in characteristics.

In addition, by using a plasma CVD method or a sputtering method, silicon oxide, silicon nitride oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide or tantalum oxide, yttrium oxide, hafnium silicate [HfSi _x O _y (x>0 , y>0)], nitrogen-added hafnium silicate [HfSi _x O _y (x>0, y>0)], nitrogen-added hafnium aluminate [HfAl _x O _y (x>0, y>0) ] Or the like may be formed in a single layer or stacked to form the gate insulating film 703.

In the present specification, oxynitride refers to a substance having a higher content of oxygen than nitrogen as its composition, and a nitride oxide refers to a substance having a higher content of nitrogen than oxygen as its composition.

The thickness of the gate insulating film 703 can be, for example, 1 nm or more and 100 nm or less, and preferably 10 nm or more and 50 nm or less. In this embodiment, a single-layer insulating film containing silicon oxynitride having a thickness of about 20 nm is formed by using the plasma CVD method, and is used as the gate insulating film 703.

The gate electrode 704 can be formed by forming a conductive film to cover the gate insulating film 703 and then processing (patterning) the conductive film into a predetermined shape. For the formation of the conductive film, a CVD method, a sputtering method, a vapor deposition method, a spin coating method, or the like can be used. Further, as the conductive film, tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), or the like can be used. An alloy containing the metal as a main component may be used, or a compound containing the metal may be used. Alternatively, it may be formed using a semiconductor such as polycrystalline silicon doped with an impurity element such as phosphorus that imparts conductivity to the semiconductor film.

Further, the gate electrode 704 may be formed of a single-layered conductive film, or may be formed of a plurality of stacked conductive films.

As a combination of the two conductive films, tantalum nitride or tantalum may be used for the first layer and tungsten may be used for the second layer. In addition to the above examples, tungsten nitride and tungsten, molybdenum nitride and molybdenum, aluminum and tantalum, aluminum and titanium, and the like may be mentioned. Since tungsten and tantalum nitride have high heat resistance, heat treatment for the purpose of thermal activation can be performed in the step after forming the two-layer conductive film. In addition, as a combination of the two layers of conductive films, for example, silicon and nickel silicide doped with an impurity element imparting n-type conductivity, silicon and tungsten silicide doped with an impurity element imparting n-type conductivity can also be used. .

In the case of a three-layer structure in which three or more conductive films are laminated, a laminated structure of a molybdenum film, an aluminum film, and a molybdenum film may be employed.

In addition, for the gate electrode 704, a light-transmitting oxide conductive film such as indium oxide, indium oxide tin oxide mixture, indium zinc oxide mixture, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, or zinc gallium oxide may be used. .

In this embodiment, a gate electrode 704 in which tungsten having a thickness of about 170 nm is stacked on tantalum nitride having a thickness of about 30 nm is used.

Further, the gate electrode 704 may be selectively formed using a droplet discharge method without using a mask. The droplet ejection method refers to a method of forming a predetermined pattern by ejecting or ejecting droplets containing a predetermined composition through a fine hole, and the ink jet method and the like are included in its category.

In addition, the gate electrode 704 uses an ICP (Inductively Coupled Plasma: Inductively Coupled Plasma) etching method after forming a conductive film, and etching conditions (amount of power applied to the coil-type electrode layer, applied to the electrode layer on the substrate side) By appropriately adjusting the amount of electric power to be applied, the electrode temperature on the substrate side, etc.), etching can be performed to have a desired tapered shape. In addition, the tapered shape can control the angle and the like also depending on the shape of the mask. In addition, as the etching gas, a chlorine-based gas such as chlorine, boron chloride, silicon chloride or carbon tetrachloride, a fluorine-based gas such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride, or oxygen can be appropriately used.

Next, as shown in (c) of FIG. 6, an impurity element imparting one conductivity is added to the semiconductor film 702 by using the gate electrode 704 as a mask to form a channel overlapping the gate electrode 704. A region 705 and a pair of impurity regions 706 interposed between the channel formation region 705 are formed in the semiconductor film 702.

In this embodiment, the case of adding an n-type impurity element (for example, phosphorus) to the semiconductor film 702 is taken as an example.

Next, as shown in Fig. 6D, an insulating film 707, an insulating film 708, and an insulating film 709 are formed to cover the gate insulating film 703 and the gate electrode 704. Specifically, as the insulating film 707, the insulating film 708, and the insulating film 709, an inorganic insulating film such as silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, and aluminum nitride oxide may be used. In particular, by using a material having a low dielectric constant (low-k) for the insulating film 707, the insulating film 708, and the insulating film 709, it is possible to sufficiently reduce the capacitance caused by overlapping of various electrodes or wiring, which is preferable . Further, for the insulating film 707, the insulating film 708, and the insulating film 709, a porous insulating film made of the above material may be applied. In the porous insulating film, since the dielectric constant is lowered compared to the high-density insulating film, it is possible to further reduce the parasitic capacitance caused by the electrode or wiring.

In this embodiment, a case where a silicon oxynitride film having a thickness of 50 nm is used as the insulating film 707, a silicon nitride oxide film having a thickness of about 100 nm as the insulating film 708, and a silicon oxynitride film having a thickness of 450 nm as the insulating film 709 is used. Take an example. In addition, in this embodiment, the case in which the insulating film 707, the insulating film 708, and the insulating film 709 are formed on the gate electrode 704 is illustrated, but in the present invention, an insulating film is formed on the gate electrode 704. Only one layer may be formed, or a plurality of insulating films other than three layers may be laminated.

Next, as shown in Fig. 7(a), openings are formed in the gate insulating film 703, the insulating film 707, the insulating film 708, and the insulating film 709 by etching or the like, and a pair of impurity regions After exposing a part of 706 and a part of the gate electrode 704, the conductive film 710 and the conductive film 711 in contact with each pair of impurity regions 706, and the conductive film 711 in contact with the gate electrode 704 A film 712 is formed. Then, an insulating film 713 is formed on the insulating film 709 to cover the conductive film 710 to the conductive film 712.

The conductive film to be the conductive film 710 to the conductive film 712 is an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described elements, or a combination of the above-described elements. Alloy films, etc. are mentioned. Further, a high melting point metal film such as chromium, tantalum, titanium, molybdenum or tungsten may be laminated on the lower or upper side of a metal film such as aluminum or copper. In addition, aluminum or copper may be used in combination with a high melting point metal material in order to avoid problems of heat resistance or corrosion. As the high melting point metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, yttrium, and the like can be used.

Further, the conductive films to be the conductive films 710 to 712 may have a single layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a titanium film, and a three-layer structure in which an aluminum film is stacked over the titanium film, and a titanium film is formed thereon. And the like.

Further, as the conductive films used as the conductive films 710 to 712, you may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide, tin oxide, zinc oxide, indium oxide tin oxide mixture, indium zinc oxide mixture, or the metal oxide material containing silicon or silicon oxide may be used.

In this embodiment, a conductive film in which a titanium film having a thickness of about 50 nm, an aluminum film having a thickness of about 200 nm, and a titanium film having a thickness of about 100 nm are laminated is used as the conductive films 710 to 712.

Although the insulating film 713 may have a single layer structure or a stacked structure of two or more layers, it is preferable that the surface thereof has high flatness. As the insulating film 713, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used. In addition, the insulating film 713 can be formed by a CVD method such as a plasma CVD method, a photo CVD method, or a thermal CVD method.

Further, as the insulating film 713, a silicon oxide film produced by a chemical vapor deposition method using an organic silane may be used. As an organosilane, ethyl silicate [TEOS:Si(OC ₂ H ₅ ) ₄ ], trimethyl silane [TMS:(CH ₃ ) ₃ SiH], tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS) , Hexamethyldisilazane (HMDS), triethoxysilane [SiH(OC ₂ H ₅ ) ₃ ], trisdimethylaminosilane [SiH(N(CH ₃ ) ₂ ) ₃ ] and the like can be used. Of course, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, or the like may be formed by using an inorganic silane such as monosilane, disilane or trisilane.

In this embodiment, the insulating film 713 containing silicon oxide having a thickness of about 1.5 μm is formed using TEOS.

Through the above process, the transistor 230 included in the driving circuit can be formed. The transistor 230 includes a semiconductor film 702, a gate insulating film 703 on the semiconductor film 702, a gate electrode 704 formed on the gate insulating film 703 at a position overlapping the semiconductor film 702, and a semiconductor. A conductive film 710 and a conductive film 711 functioning as a source electrode or a drain electrode are connected to the impurity region 706 of the film 702.

Next, as shown in FIG. 7B, the insulating film 713 is subjected to a CMP (chemical mechanical polishing) treatment or an etching treatment to expose the surface of the conductive film 712. In addition, in order to improve the characteristics of the transistor 109 to be formed later, it is preferable to make the surface of the insulating film 713 as flat as possible.

Next, a method of manufacturing the transistor 109 will be described. First, as shown in (c) of FIG. 7, an insulating film 714 is formed on the insulating film 713 and the conductive film 712, and then an oxide semiconductor film 715 is formed on the insulating film 714. .

The insulating film 714 can be formed using the same material as the insulating film 707 to the insulating film 709. In this embodiment, a silicon oxynitride film having a thickness of about 300 nm is used as the insulating film 714.

The oxide semiconductor film 715 can be formed by processing the oxide semiconductor film formed on the insulating film 714 into a desired shape. The thickness of the oxide semiconductor film is 2 nm or more and 200 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 3 nm or more and 20 nm or less. An oxide semiconductor film is formed by a sputtering method using an oxide semiconductor as a target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (eg, argon) atmosphere, an oxygen atmosphere, or a rare gas (eg, argon) and oxygen mixed atmosphere.

In addition, before forming the oxide semiconductor film by sputtering, it is preferable to perform reverse sputtering in which plasma is generated by introducing argon gas to remove dust adhering to the surface of the insulating film 714. Reverse sputtering is a method in which a voltage is not applied to the target side, but a voltage is applied to the substrate side using an RF power source in an argon atmosphere, and plasma is formed in the vicinity of the substrate to modify the surface. Moreover, you may use nitrogen, helium, etc. instead of an argon atmosphere. Further, it may be performed in an atmosphere in which oxygen, nitrogen oxide, or the like is added to an argon atmosphere. Further, it may be carried out in an atmosphere in which chlorine, carbon tetrafluoride, or the like is added to an argon atmosphere.

For example, indium oxide, tin oxide, zinc oxide as oxide semiconductors, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide as an oxide semiconductor Oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also referred to as IGZO), an oxide of ternary metal, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In- Pr-Zn type oxide, In-Nd-Zn type oxide, In-Sm-Zn type oxide, In-Eu-Zn type oxide, In-Gd-Zn type oxide, In-Tb-Zn type oxide, In-Dy- Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, quaternary metal oxide In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxides can be used. In addition, the oxide semiconductor may contain silicon.

In this embodiment, a thin film of an In-Ga-Zn-based oxide semiconductor having a film thickness of 30 nm obtained by a sputtering method using a target containing In (indium), Ga (gallium) and Zn (zinc) is used as an oxide semiconductor film. Use. As the target, preferably, the atomic ratio is In:Ga:Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3 or 3:1: The target represented by 4 is used. In addition, the filling rate of the target containing In, Ga, and Zn is 90% or more and 100% or less, and preferably 95% or more and less than 100%. By using a target with a high filling rate, the formed oxide semiconductor film becomes a dense film.

In addition, when an In-Zn-based material is used as the oxide semiconductor film, the composition ratio of the target to be used is In:Zn=50:1 to 1:2 in terms of atomic number ratio (in terms of the molar ratio, In ₂ O ₃ :ZnO=25: 1 to 1:4), preferably In:Zn=20:1 to 1:1 (in terms of molar ratio, In ₂ O ₃ :ZnO=10:1 to 1:2), more preferably In:Zn= 1.5:1 to 15:1 (in terms of molar ratio, In ₂ O ₃ :ZnO=3:4 to 15:2). For example, a target used for formation of an In-Zn-based oxide semiconductor is set to Z>1.5X+Y when the atomic ratio is In:Zn:O=X:Y:Z. By making the ratio of Zn within the above range, the mobility can be improved.

Further, in the case of forming an In-Sn-Zn-based oxide semiconductor film as an oxide semiconductor film by sputtering, the atomic ratio is preferably In:Sn:Zn=1:1:1, 2:1:3, 1:2: The In-Sn-Zn-O target represented by 2 or 20:45:35 is used.

In this embodiment, the substrate is held in a processing chamber maintained in a reduced pressure state, and a sputter gas from which hydrogen and moisture have been removed is introduced while removing residual moisture in the processing chamber, and an oxide semiconductor film is formed using the target. During film formation, the substrate temperature may be 100°C or more and 600°C or less, and preferably 200°C or more and 400°C or less. By forming a film while heating the substrate, the concentration of impurities contained in the formed oxide semiconductor film can be reduced. In addition, damage caused by sputtering is alleviated. In order to remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, and a titanium sublimation pump. Further, as the exhaust means, a cold trap may be applied to the turbo pump. When the treatment chamber is exhausted using a cryopump, compounds containing hydrogen atoms, such as hydrogen atoms and water (H ₂ O) (more preferably, compounds containing carbon atoms) are exhausted. The concentration of impurities contained in the oxide semiconductor film formed in the processing chamber can be reduced.

As an example of the film forming conditions, the distance between the substrate and the target is 100 mm, a pressure of 0.6 Pa, a direct current (DC) power supply of 0.5 kW, and a condition under an atmosphere of oxygen (oxygen flow rate of 100%) are applied. Further, the use of a pulsed direct current (DC) power supply is preferable because dust generated during film formation can be reduced and the film thickness distribution becomes uniform.

In addition, by setting the leak rate in the processing chamber of the sputtering device to 1 × 10 ^-10 Pa·m ³ /sec or less, the incorporation of impurities such as alkali metals and hydrides into the oxide semiconductor film during film formation by the sputtering method can be reduced. I can. Further, by using the above-described adsorption type vacuum pump as the exhaust system, it is possible to reduce backflow of impurities such as alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, or hydrides from the exhaust system.

Further, by setting the purity of the target to 99.99% or more, it is possible to reduce alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, hydrides, and the like mixed in the oxide semiconductor film. Further, by using the target, the concentration of alkali metals such as lithium, sodium, and potassium in the oxide semiconductor film can be reduced.

In addition, in order to prevent the oxide semiconductor film from containing hydrogen, hydroxyl groups, and moisture as much as possible, as a pretreatment for film formation, the substrate 700 on which the insulating film 714 is formed in the preheating chamber of the sputtering apparatus is preheated, and the substrate ( It is preferable to exhaust the impurities such as moisture or hydrogen adsorbed on 700). Further, the preheating temperature is 100°C or more and 400°C or less, and preferably 150°C or more and 300°C or less. In addition, a cryopump is preferable as the exhaust means provided in the preheating chamber. Further, the preheating treatment may be omitted. In addition, the preheating may be similarly performed on the substrate 700 in which the conductive film 716, the conductive film 717, and the conductive film 718 are formed before the gate insulating film 719 is formed later.

In addition, the etching for forming the oxide semiconductor film 715 may be dry etching or wet etching, or both may be used. As the etching gas used for dry etching, a gas containing chlorine (such as chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ), etc.) is preferable. Do. In addition, fluorine-containing gases [fluorine-based gases such as carbon tetrafluoride (CF ₄ ), sulfur hexafluoride (SF ₆ ), nitrogen trifluorogen (NF ₃ ), trifluoromethane (CHF ₃ ), etc.] , Hydrogen bromide (HBr), oxygen (O ₂ ), a gas in which noble gases such as helium (He) or argon (Ar) are added to these gases can be used.

As a dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma: Inductively Coupled Plasma) etching method can be used. Etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted so that etching can be performed in a desired shape.

As an etching solution used for wet etching, a solution of phosphoric acid, acetic acid, and nitric acid, or organic acids such as citric acid or oxalic acid can be used. In this embodiment, ITO-07N (manufactured by Kanto Chemical Co., Ltd.) is used.

A resist mask for forming the oxide semiconductor film 715 may be formed by an ink jet method. When the resist mask is formed by the ink jet method, the manufacturing cost can be reduced because a photomask is not used.

Further, it is preferable to perform reverse sputtering before forming the conductive film in the next step to remove resist residues and the like adhering to the surfaces of the oxide semiconductor film 715 and the insulating film 714.

In addition, the oxide semiconductor film formed by sputtering or the like may contain a large amount of water or hydrogen (including hydroxyl groups) as impurities. Moisture or hydrogen is an impurity in an oxide semiconductor because it is easy to form a donor level. Accordingly, in one aspect of the present invention, in order to reduce (dehydrate or dehydrogenate) impurities such as moisture or hydrogen in the oxide semiconductor film, the oxide semiconductor film 715 is In an inert gas atmosphere, an oxygen gas atmosphere, or an ultra-dry air (when measured using a dew point meter of CRDS (cavity ring down laser spectroscopy) method, the moisture content is 20 ppm (in terms of dew point) or less), preferably 1 ppm or less, preferably 10 ppb or less air], the oxide semiconductor film 715 is subjected to heat treatment.

By performing heat treatment on the oxide semiconductor film 715, moisture or hydrogen in the oxide semiconductor film 715 can be released. Specifically, heat treatment may be performed at a temperature of 250° C. or more and 750° C. or less, preferably 400° C. or more and less than the distortion point of the substrate. For example, it may be performed at 500°C for 3 minutes or more and 6 minutes or less. When the RTA method is used for the heat treatment, dehydration or dehydrogenation can be performed in a short time, and thus the treatment can be performed even at a temperature exceeding the distortion point of the glass substrate.

In this embodiment, an electric furnace which is one of the heat treatment devices is used.

Further, the heat treatment device is not limited to an electric furnace, and may include a device that heats an object to be processed by heat conduction or heat radiation from a heat generating element such as a resistance heat generating element. For example, a Rapid Thermal Anneal (RTA) device such as a Gas Rapid Thermal Anneal (GRTA) device or a Lamp Rapid Thermal Anneal (LRTA) device can be used. The LRTA device is a device that heats a target object by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. The GRTA device is a device that performs heat treatment using a high-temperature gas. As the gas, a rare gas such as argon or an inert gas that does not react with the object to be treated by heat treatment such as nitrogen is used.

In the heat treatment, it is preferable that no moisture or hydrogen is contained in nitrogen or a noble gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or noble gas such as helium, neon, argon, etc. to be introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) is preferable.

In addition, it has been pointed out that oxide semiconductors are insensitive to impurities, so there is no problem even if significant metal impurities are contained in the film, and inexpensive soda-lime glass containing a large amount of alkali metals such as sodium can also be used (Kamiya, Nomura, Hosono, "Physical properties of amorphous oxide semiconductors and the phenomenon of device development", Solid State Physics, September 2009, Vol.44, pp.621-633.). However, this point is not appropriate. Alkali metal is an impurity because it is not an element constituting an oxide semiconductor. Alkaline earth metals also become impurities when they are not elements constituting the oxide semiconductor. Particularly, Na in the alkali metal diffuses into the insulating film and becomes Na ⁺ when the insulating film in contact with the oxide semiconductor film is an oxide. In addition, Na breaks the bond between the metal and oxygen constituting the oxide semiconductor in the oxide semiconductor film, or interrupts the bond during the bond. As a result, for example, deterioration of the characteristics of the transistor such as normally on and a decrease in mobility occurs as the threshold voltage shifts in the negative direction, and further variations in characteristics occur. The deterioration of the characteristics of the transistor and fluctuations in characteristics caused by this impurity appear remarkably when the hydrogen concentration in the oxide semiconductor film is sufficiently low. Therefore, when the hydrogen concentration in the oxide semiconductor film is 1×10 ¹⁸ /cm ³ or less, more preferably 1×10 ¹⁷ /cm ³ or less, it is preferable to reduce the concentration of the impurity. Specifically, the measured value of the Na concentration by secondary ion mass spectrometry is 5×10 ¹⁶ /cm ³ or less, preferably 1×10 ¹⁶ /cm ³ or less, more preferably 1×10 ¹⁵ /cm ³ or less. Good to do. Similarly, the measured value of the Li concentration is 5×10 ¹⁵ /cm ³ or less, preferably 1×10 ¹⁵ /cm ³ or less. Similarly, the measured value of the K concentration is 5×10 ¹⁵ /cm ³ or less, preferably 1×10 ¹⁵ /cm ³ or less.

By the above process, the concentration of hydrogen in the oxide semiconductor film 715 can be reduced to achieve high purity. Accordingly, the oxide semiconductor film can be stabilized. Further, by heat treatment below the glass transition temperature, an oxide semiconductor film having an extremely small carrier density and a wide band gap can be formed. For this reason, a transistor can be manufactured using a large-area substrate, and mass production can be improved. In addition, by using the oxide semiconductor film whose hydrogen concentration has been reduced and has become highly purified, a transistor having high withstand voltage and remarkably low off current can be manufactured. The heat treatment can be performed at any time after the oxide semiconductor film is formed.

Further, although the oxide semiconductor film may be amorphous, it may have crystallinity. As an oxide semiconductor film having crystallinity, even a CAAC-OS (C Axis Aligned Crystal Oxide Semiconductor) film containing a crystal (CAAC) having a c-axis orientation can obtain an effect of increasing the reliability of the transistor, and is therefore preferable. .

An oxide semiconductor film composed of a CAAC-OS film can also be produced by a sputtering method. In order to obtain the CAAC-OS film by sputtering, it is important to form a hexagonal crystal in the initial stage of deposition of the oxide semiconductor film and to grow the crystal using the crystal as a species. To do so, take a wide distance between the target and the substrate (for example, about 150mm to 200mm), and the substrate heating temperature is 100°C to 500°C, suitably 200°C to 400°C, more preferably 250°C to 300°C. It is preferable to use. In addition, by heat-treating the oxide semiconductor film deposited at a temperature higher than the substrate heating temperature at the time of film formation, micro-defects contained in the film or defects at the lamination interface can be repaired.

The CAAC-OS film is not completely single crystal and is not completely amorphous. The CAAC-OS film is an oxide semiconductor film having a crystalline-amorphous mixed phase structure having a crystal portion in an amorphous phase. In addition, the crystal part is often sized to fit in a cube whose one side is less than 100 nm. In addition, the boundary between the amorphous portion and the crystalline portion contained in the CAAC-OS film is not clear on observation by a transmission electron microscope (TEM). In addition, grain boundaries (also referred to as grain boundaries) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, a decrease in electron mobility due to grain boundaries is suppressed.

The crystal part included in the CAAC-OS film is aligned in a direction in which the c-axis is parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and at the same time, it is triangular or hexagonal when viewed from a direction perpendicular to the ab It has an atomic arrangement of the shape, and when viewed from a direction perpendicular to the c-axis, metal atoms are arranged in a layer shape or metal atoms and oxygen atoms are arranged in a layer shape. Further, the directions of the a-axis and the b-axis may be different between different crystal parts. In the present specification, when simply described as vertical, the range of 85° or more and 95° or less is also included. In addition, when simply described as parallel, the range of -5° or more and 5° or less is also included.

In addition, in the CAAC-OS film, the distribution of crystal portions does not need to be uniform. For example, in the process of forming the CAAC-OS film, when crystals are grown on the surface side of the oxide semiconductor film, the ratio of the crystal portion occupied in the vicinity of the surface to the vicinity of the surface to be formed may increase.

Since the c-axis of the crystal part contained in the CAAC-OS film is aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface to be formed of the CAAC-OS film, the shape of the CAAC-OS film (cross-sectional shape or surface Depending on the cross-sectional shape), they may face different directions. In addition, the c-axis direction of the crystal part is a normal direction of the surface to be formed when the CAAC-OS film is formed or a direction parallel to the normal direction of the surface. The crystal portion is formed by forming a film or by performing a crystallization treatment such as heat treatment after film formation.

A transistor using a CAAC-OS film can reduce fluctuations in electrical characteristics due to irradiation of visible light or ultraviolet light. Therefore, the transistor has high reliability.

Next, as shown in Fig. 8A, after forming openings in the insulating film 713 and the insulating film 714 by etching or the like to expose a part of the conductive film 710, the conductive film ( A conductive film 716 in contact with 710, a conductive film 717 and a conductive film 718 in contact with the oxide semiconductor film 715 are formed. The conductive film 717 and the conductive film 718 function as a source electrode or a drain electrode.

Specifically, for the conductive film 716, the conductive film 717, and the conductive film 718, a conductive film is formed on the insulating film 714 by sputtering or vacuum evaporation to cover the openings, and then the conductive film is formed in a predetermined shape. It can be formed by processing (patterning) with.

The conductive film 716, the conductive film 717, and the conductive film used as the conductive film 718 is an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described elements as a component, And alloy films in which the above-described elements are combined. Further, a high melting point metal film such as chromium, tantalum, titanium, molybdenum or tungsten may be laminated on the lower or upper side of a metal film such as aluminum or copper. In addition, aluminum or copper may be used in combination with a high melting point metal material in order to avoid problems of heat resistance or corrosion. As the high melting point metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, yttrium, and the like can be used.

Further, the conductive film 716, the conductive film 717, and the conductive film used as the conductive film 718 may have a single layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a titanium film, and a three-layer structure in which an aluminum film is stacked over the titanium film, and a titanium film is formed thereon. And the like. Further, the Cu-Mg-Al alloy, Mo-Ti alloy, Ti, and Mo have high adhesion to the oxide film. Accordingly, a conductive film composed of Cu-Mg-Al alloy, Mo-Ti alloy, Ti or Mo is stacked on the lower layer, and a conductive film composed of Cu is stacked on the upper layer, and the stacked conductive film is a conductive film 716 and a conductive film ( By using it for the 717) and the conductive film 718, the adhesion between the insulating film 714 which is an oxide film, the conductive film 716, the conductive film 717, and the conductive film 718 can be improved.

Further, the conductive film 716, the conductive film 717, and the conductive film 718 may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide, tin oxide, zinc oxide, indium oxide tin oxide mixture, indium zinc oxide mixture, or the metal oxide material containing silicon or silicon oxide may be used.

In the case of performing heat treatment after formation of the conductive film, it is preferable to impart heat resistance to the heat treatment to the conductive film.

In this embodiment, a 150 nm-thick tungsten film is used as the conductive film 716, the conductive film 717, and the conductive film 718.

In addition, when etching the conductive film, each material and etching conditions are appropriately adjusted so that the oxide semiconductor film 715 is not removed as much as possible. Depending on the etching conditions, a portion of the exposed portion of the oxide semiconductor film 715 may be partially etched to form a groove (recess).

In the present embodiment, a tungsten film is used for the conductive film 716, the conductive film 717, and the conductive film used as the conductive film 718. Therefore, it is possible to wet-etch the conductive film selectively using a solution containing ammonia and hydrogen peroxide solution (ammonia fruit water). Specifically, ammonia fruit water obtained by mixing 31% by weight of hydrogen peroxide solution, 28% by weight of ammonia solution, and water in a volume ratio of 5:2:2 is used. Alternatively, the conductive film may be dry etched using a gas containing carbon tetrafluorocarbon (CF ₄ ), chlorine (Cl ₂ ), and oxygen.

Further, in order to reduce the number of photomasks used in the photolithography process and the number of steps, an etching process may be performed using a resist mask formed of a multi-gradation mask that imparts multi-level intensity to transmitted light. A resist mask formed using a multi-gradation mask has a shape having a plurality of film thicknesses, and can be further deformed by performing etching, and thus can be used in a plurality of etching steps for processing into different patterns. Therefore, it is possible to form a resist mask corresponding to at least two or more different patterns by using one multi-gradation mask. Accordingly, since the number of exposure masks can be reduced and the corresponding photolithography process can be reduced, the process can be simplified.

Further, an oxide conductive film serving as a source region and a drain region may be provided between the oxide semiconductor film 715 and the conductive film 717 and the conductive film 718 functioning as a source or drain electrode. As the material of the oxide conductive film, it is preferable that zinc oxide is included as a component, and it is preferable that indium oxide is not included. As such an oxide conductive film, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, or the like can be applied.

For example, when forming the oxide conductive film, patterning for forming the oxide conductive film and patterning for forming the conductive film 717 and the conductive film 718 may be performed collectively.

By providing an oxide conductive film that functions as a source region and a drain region, the resistance between the oxide semiconductor film 715 and the conductive film 717 and the conductive film 718 can be lowered, so that high-speed operation of the transistor can be realized. . Further, by providing an oxide conductive film serving as a source region and a drain region, the breakdown voltage of the transistor can be increased.

Next, plasma treatment using a gas such as N ₂ O, N ₂ or Ar may be performed. Water or the like adhering to the surface of the oxide semiconductor film exposed by the plasma treatment is removed. Further, plasma treatment may be performed using a mixed gas of oxygen and argon.

In addition, after plasma treatment, as shown in Fig. 8B, a gate insulating film is applied to cover the conductive film 716, the conductive film 717, and the conductive film 718, and the oxide semiconductor film 715. Form (719). Then, on the gate insulating film 719, a gate electrode 720 is formed at a position overlapping the oxide semiconductor film 715, and a conductive film 721 is formed at a position overlapping the conductive film 717.

The gate insulating film 719 can be formed using the same material as the gate insulating film 703 and the same laminated structure. In addition, it is preferable that the gate insulating film 719 does not contain impurities such as moisture or hydrogen as much as possible, and may be a single-layer insulating film, or may be composed of a plurality of stacked insulating films. When hydrogen is contained in the gate insulating film 719, the hydrogen penetrates into the oxide semiconductor film 715, or the hydrogen releases oxygen in the oxide semiconductor film 715, so that the oxide semiconductor film 715 is reduced in resistance ( n-type), there is a risk of forming a parasitic channel. Therefore, it is important not to use hydrogen in the film formation method so that the gate insulating film 719 is a film that does not contain hydrogen as much as possible. It is preferable to use a material having high barrier properties for the gate insulating film 719. For example, as an insulating film having high barrier properties, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like can be used. In the case of using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxide film having a low nitrogen content is formed on the side closer to the oxide semiconductor film 715 than the insulating film having high barrier properties. Then, an insulating film having high barrier properties is formed so as to overlap the conductive film 716, the conductive film 717, the conductive film 718, and the oxide semiconductor film 715 with an insulating film having a low nitrogen content therebetween. By using an insulating film having a high barrier property, impurities such as moisture or hydrogen are prevented from entering the oxide semiconductor film 715, the gate insulating film 719, or the interface between the oxide semiconductor film 715 and another insulating film and the vicinity thereof. Can be prevented. In addition, by forming an insulating film such as a silicon oxide film and a silicon oxynitride film having a low nitrogen ratio so as to contact the oxide semiconductor film 715, the insulating film made of a material having high barrier properties is prevented from directly contacting the oxide semiconductor film 715. Can be prevented.

In this embodiment, a silicon oxynitride film having a thickness of 30 nm formed by a sputtering method is used as the gate insulating film 719. The substrate temperature at the time of film formation may be room temperature or more and 400°C or less, and in the present embodiment, it is 300°C.

Further, heat treatment may be performed after the gate insulating film 719 is formed. The heat treatment is performed in an atmosphere of nitrogen, ultra-dry air or rare gas (argon, helium, etc.), preferably at 200°C or more and 400°C or less, for example, 250°C or more and 350°C or less. The gas preferably has a water content of 20 ppm or less, preferably 1 ppm or less, and more preferably 10 ppb or less. In this embodiment, for example, heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. Alternatively, prior to forming the conductive film 716, the conductive film 717, and the conductive film 718, a high-temperature, short-time RTA treatment is performed similarly to the previous heat treatment performed on the oxide semiconductor film for reducing moisture or hydrogen. Also good. By heating treatment after the gate insulating film 719 containing oxygen is installed, even if oxygen vacancies occur in the oxide semiconductor film 715 due to the previous heat treatment performed on the oxide semiconductor film 715, the gate insulating film 719 Oxygen is donated to the oxide semiconductor film 715. In addition, by donating oxygen to the oxide semiconductor film 715, oxygen vacancies serving as donors in the oxide semiconductor film 715 can be reduced and the stoichiometric composition ratio can be satisfied. As a result, the oxide semiconductor film 715 can be made close to the i-type, and variations in the electrical characteristics of the transistor due to oxygen vacancies can be reduced, and the electrical characteristics can be improved. The timing for performing the heat treatment is not particularly limited as long as it is after the formation of the gate insulating film 719, and may be combined with other processes such as heat treatment at the time of formation of the resin film or heat treatment to reduce the resistance of the transparent conductive film. , The oxide semiconductor film 715 can be made close to the i-type without increasing the number of steps.

Further, by subjecting the oxide semiconductor film 715 to heat treatment in an oxygen atmosphere, oxygen may be added to the oxide semiconductor to reduce oxygen vacancies serving as donors in the oxide semiconductor film 715. The temperature of the heat treatment is, for example, 100°C or more and less than 350°C, and preferably 150°C or more and less than 250°C. It is preferable that water, hydrogen, or the like is not contained in the oxygen gas used for the heat treatment under the oxygen atmosphere. Alternatively, it is preferable that the purity of the oxygen gas introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration in oxygen is 1 ppm or less, preferably 0.1 ppm or less). Do.

Alternatively, oxygen vacancies serving as donors may be reduced by adding oxygen to the oxide semiconductor film 715 using an ion implantation method or an ion doping method. For example, oxygen converted into plasma with a microwave of 2.45 GHz may be added to the oxide semiconductor film 715.

In addition, the gate electrode 720 and the conductive film 721 can be formed by forming a conductive film on the gate insulating film 719 and then patterning the conductive film. The gate electrode 720 and the conductive film 721 can be formed using the same material as the gate electrode 704 or the conductive film 716, the conductive film 717 and the conductive film 718.

The thickness of the gate electrode 720 and the conductive film 721 is 10 nm to 400 nm, preferably 100 nm to 300 nm. In this embodiment, after forming a conductive film for a gate electrode of 150 nm by a sputtering method using a tungsten target, the conductive film is processed (patterned) into a desired shape by etching, so that the gate electrode 720 and the conductive film 721 are formed. ) To form. Further, a resist mask may be formed by an ink jet method. When the resist mask is formed by the ink jet method, the manufacturing cost can be reduced because a photomask is not used.

The transistor 109 is formed by the above process.

In addition, the portion where the conductive film 717 and the conductive film 721 overlap with the gate insulating film 719 therebetween corresponds to the capacitor element 110.

In the present embodiment, an example of the parallel plate type capacitor 110 has been shown, but in the memory device according to an aspect of the present invention, a stack type capacitor element may be used.

Further, although the transistor 109 has been described using a transistor having a single gate structure, a multi-gate structure transistor having a plurality of channel formation regions can also be formed by having a plurality of gate electrodes electrically connected as necessary.

In addition, as the insulating film in contact with the oxide semiconductor film 715 (in this embodiment, the insulating film 714 and the gate insulating film 719 correspond), an insulating material containing a group 13 element and oxygen may be used. Oxide semiconductor materials often contain an element of Group 13, and an insulating material containing an element of Group 13 has good compatibility with an oxide semiconductor. By using this for an insulating film in contact with the oxide semiconductor film, the interface with the oxide semiconductor film It can maintain a good condition.

The insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of the insulating material containing the Group 13 element include gallium oxide, aluminum oxide, gallium aluminum oxide, and gallium aluminum oxide. Here, gallium aluminum oxide indicates that the content of aluminum (atomic%) is greater than that of gallium (atomic%), and gallium aluminum indicates that the gallium content (atomic%) is greater than or equal to the content of aluminum (atomic%). .

For example, in the case of forming an insulating film in contact with an oxide semiconductor film containing gallium, the interface characteristics between the oxide semiconductor film and the insulating film can be maintained satisfactorily by using a material containing gallium oxide for the insulating film. For example, by providing an oxide semiconductor film and an insulating film containing gallium oxide in contact with each other, hydrogen pile-up at the interface between the oxide semiconductor film and the insulating film can be reduced. Moreover, when an element of the same group as the component element of the oxide semiconductor is used for the insulating film, the same effect can be obtained. For example, it is also effective to form an insulating film using a material containing aluminum oxide. Further, since aluminum oxide has a characteristic that makes it difficult to permeate water, the use of the material is also preferable in terms of preventing water from entering the oxide semiconductor film.

In addition, the insulating film in contact with the oxide semiconductor film 715 is preferably in a state in which the insulating material contains more oxygen than the stoichiometric composition ratio by heat treatment under an oxygen atmosphere or oxygen doping. Oxygen dope refers to adding oxygen to the bulk. In addition, the term of the bulk is used to make it clear that oxygen is added not only to the surface of the thin film but also inside the thin film. In addition, oxygen plasma dope which adds plasma-formed oxygen to the bulk is included in the oxygen dope. In addition, oxygen doping may be performed using an ion implantation method or an ion doping method.

For example, when gallium oxide is used as the insulating film in contact with the oxide semiconductor film 715, by performing heat treatment or oxygen doping under an oxygen atmosphere, the composition of gallium oxide is Ga ₂ O _X (X=3+α, 0<α). It can be done with <1).

In addition, when aluminum oxide is used as the insulating film in contact with the oxide semiconductor film 715, the composition of aluminum oxide is changed to Al ₂ O _X (X=3+α, 0<α<1) by performing heat treatment or oxygen doping in an oxygen atmosphere. ).

Further, when an insulating film in contact with the oxide semiconductor film 715 using the gallium aluminum oxide (aluminum gallium oxide), the composition of the by performing heat treatment and oxygen doping due under the oxygen atmosphere, the gallium aluminum oxide (aluminum gallium oxide) Ga _X Al _{2 -X} O _3+α (0<X<2, 0<α<1).

By performing the oxygen doping treatment, an insulating film having a region containing more oxygen than the stoichiometric composition ratio can be formed. When the insulating film having such a region and the oxide semiconductor film come into contact with each other, excess oxygen in the insulating film is supplied to the oxide semiconductor film, reducing oxygen defects in the oxide semiconductor film or at the interface between the oxide semiconductor film and the insulating film, thereby forming i It can be infinitely close to type or i type.

In addition, the insulating film having a region containing more oxygen than the stoichiometric composition ratio may be used only in either one of the insulating film located in the upper layer or the insulating film located in the lower layer among the insulating films in contact with the oxide semiconductor film 715, but both insulating films It is preferable to use it. An insulating film having a region containing more oxygen than the stoichiometric composition ratio is used for the insulating film positioned above and below the insulating film in contact with the oxide semiconductor film 715, and the oxide semiconductor film 715 is sandwiched therebetween. You can increase the effect.

In addition, the insulating film used for the upper or lower layer of the oxide semiconductor film 715 may be an insulating film having the same constituent elements in the upper and lower layers, or may be an insulating film having different constituent elements. For example, gallium oxide having a composition of Ga ₂ O _X (X=3+α, 0<α<1) in both the upper layer and the lower layer may be used, and one of the upper and lower layers has a composition of Ga ₂ O _X (X=3 +α, 0<α<1) may be used as gallium oxide, and the other may be used as aluminum oxide having a composition of Al ₂ O _X (X=3+α, 0<α<1).

In addition, the insulating film in contact with the oxide semiconductor film 715 may be a stack of insulating films having a region containing more oxygen than the stoichiometric composition ratio. For example, gallium oxide having a composition of Ga ₂ O _X (X=3+α, 0<α<1) is formed on the upper layer of the oxide semiconductor film 715, and the composition is Ga _X Al _2-X O _3+α (0<X<2, 0<α<1) gallium aluminum oxide (gallium aluminum oxide) may be formed. In addition, the lower layer of the oxide semiconductor film 715 may be laminated with an insulating film having a region containing more oxygen than the stoichiometric composition ratio, and both the upper and lower layers of the oxide semiconductor film 715 have oxygen rather than the stoichiometric composition ratio. An insulating film having many regions may be laminated.

Next, as shown in FIG. 8C, an insulating film 722 is formed to cover the gate insulating film 719, the conductive film 721, and the gate electrode 720. The insulating film 722 can be formed using a PVD method, a CVD method, or the like. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, and aluminum oxide. In addition, it is preferable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 722. This is because, by lowering the dielectric constant of the insulating film 722, the parasitic capacitance generated between wirings, electrodes, etc. can be reduced, and the operation can be accelerated. In addition, in this embodiment, although the insulating film 722 is made into a single-layer structure, one aspect of this invention is not limited to this, It may be a laminated structure of two or more layers.

Next, openings 725 are formed in the gate insulating film 719 and the insulating film 722, and a part of the conductive film 718 is exposed. Thereafter, a wiring 726 in contact with the conductive film 718 in the opening 725 is formed on the insulating film 722.

The wiring 726 is formed by forming a conductive film using a PVD method or a CVD method, and then patterning the conductive film. Further, as the material of the conductive film, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing the above-described elements, or the like can be used. Any one of manganese, magnesium, zirconium, beryllium, neodymium, and scandium, or a combination of a plurality of these materials may be used.

In this embodiment, a conductive film formed by sequentially laminating a titanium film having a thickness of about 50 nm, an aluminum film having a thickness of about 200 nm, and a titanium film having a thickness of about 50 nm by sputtering is used as the wiring 726. The titanium film has a function of reducing an oxide film (such as a natural oxide film) on a surface to be formed to reduce contact resistance with a lower electrode or the like (here, the conductive film 718). In addition, hillock of the aluminum film can be prevented. Further, after forming a barrier film made of titanium, titanium nitride, or the like, a copper film may be formed by a plating method.

Next, an insulating film 727 is formed so as to cover the wiring 726. The memory device can be manufactured by the series of steps described above.

Further, in the above manufacturing method, a conductive film 717 and a conductive film 718 functioning as a source electrode and a drain electrode are formed behind the oxide semiconductor film 715. Therefore, as shown in FIG. 8B, in the transistor 109 obtained by the above manufacturing method, a conductive film 717 and a conductive film 718 are formed on the oxide semiconductor film 715. However, in the transistor 109, a conductive film functioning as a source electrode and a drain electrode may be provided under the oxide semiconductor film 715, that is, between the oxide semiconductor film 715 and the insulating film 714.

This embodiment can be implemented in appropriate combination with the above embodiment.

(Embodiment 5)

In this embodiment, a transistor using an oxide semiconductor film having a structure different from that of the fourth embodiment will be described.

The transistor 601 shown in Fig. 9A is a bottom gate type having a channel etch structure.

The transistor 601 includes a gate electrode 602 formed on an insulating surface, a gate insulating film 603 on the gate electrode 602, and an oxide semiconductor film 604 overlapping the gate electrode 602 on the gate insulating film 603. ), and a conductive film 605 and a conductive film 606 formed on the oxide semiconductor film 604. In addition, the transistor 601 may include an oxide semiconductor film 604, a conductive film 605, and an insulating film 607 formed on the conductive film 606 as its constituent elements.

Further, the transistor 601 shown in FIG. 9A may further have a back gate electrode formed on the insulating film 607 at a position overlapping with the oxide semiconductor film 604.

The transistor 611 shown in Fig. 9B is a bottom gate type with a channel protection structure.

The transistor 611 includes a gate electrode 612 formed on an insulating surface, a gate insulating film 613 on the gate electrode 612, and an oxide semiconductor film 614 overlapping the gate electrode 612 on the gate insulating film 613. ), a channel protective film 618 formed on the oxide semiconductor film 614, a conductive film 615 and a conductive film 616 formed on the oxide semiconductor film 614. Further, the transistor 611 may include a channel protective film 618, a conductive film 615, and an insulating film 617 formed on the conductive film 616 as its constituent elements.

Further, the transistor 611 shown in FIG. 9B may further include a back gate electrode formed on the insulating film 617 at a position overlapping the oxide semiconductor film 614.

By providing the channel protection film 618, damage to the portion of the oxide semiconductor film 614 that becomes a channel formation region can be prevented from being damaged by plasma or an etchant during etching in a later step. Therefore, the reliability of the transistor 611 can be improved.

The transistor 621 shown in Fig. 9C is a bottom gate type having a bottom contact structure.

The transistor 621 includes a gate electrode 622 formed on an insulating surface, a gate insulating film 623 on the gate electrode 622, a conductive film 625 and a conductive film 626 on the gate insulating film 623, It overlaps the gate electrode 622 on the gate insulating film 623, and has a conductive film 625 and an oxide semiconductor film 624 formed on the conductive film 626. In addition, the transistor 621 may include a conductive film 625, a conductive film 626, and an insulating film 627 formed on the oxide semiconductor film 624 as its constituent elements.

In addition, the transistor 621 shown in FIG. 9C may further include a back gate electrode formed on the insulating film 627 at a position overlapping the oxide semiconductor film 624.

The transistor 641 shown in Fig. 9D is a top gate type having a bottom contact structure.

The transistor 641 includes a conductive film 645 and a conductive film 646 formed on an insulating surface, an oxide semiconductor film 644 formed on the conductive film 645 and the conductive film 646, and an oxide semiconductor film ( 644, a gate insulating film 643 formed on the conductive film 645 and the conductive film 646, and a gate electrode 642 overlapping the oxide semiconductor film 644 on the gate insulating film 643. In addition, the transistor 641 may include an insulating film 647 formed on the gate electrode 642 as its constituent element.

This embodiment can be implemented in combination with the above embodiment.

(Embodiment 6)

In this embodiment, a transistor using an oxide semiconductor film having a structure different from that of the fourth or fifth embodiment will be described.

The transistor 901 shown in FIG. 10A includes an oxide semiconductor film 903 formed on the insulating film 902 and functioning as an active layer, a source electrode 904 formed on the oxide semiconductor film 903, and The drain electrode 905, the oxide semiconductor film 903, the gate insulating film 906 on the source electrode 904 and the drain electrode 905, and the oxide semiconductor film 903 on the gate insulating film 906 It has a gate electrode 907.

The transistor 901 shown in FIG. 10A is a top gate type in which a gate electrode 907 is formed on an oxide semiconductor film 903, and a source electrode 904 and a drain electrode 905 are formed. It is a top contact type formed on the oxide semiconductor film 903. In the transistor 901, the source electrode 904 and the drain electrode 905 and the gate electrode 907 do not overlap. That is, a gap larger than the thickness of the gate insulating film 906 is formed between the source electrode 904 and the drain electrode 905 and the gate electrode 907. Accordingly, the transistor 901 can reduce the parasitic capacitance formed between the source electrode 904 and the drain electrode 905 and the gate electrode 907 to a small extent, thereby realizing a high-speed operation.

Further, the oxide semiconductor film 903 has a pair of high concentration regions 908 obtained by adding a dopant that imparts n-type conductivity to the oxide semiconductor film 903 after the gate electrode 907 is formed. Further, of the oxide semiconductor film 903, a region overlapping the gate electrode 907 with the gate insulating film 906 therebetween is a channel formation region 909. In the oxide semiconductor film 903, a channel formation region 909 is formed between a pair of high concentration regions 908. An ion implantation method may be used to add a dopant for forming the high concentration region 908. As the dopant, for example, rare gases such as helium, argon, and xenon, and Group 15 atoms such as nitrogen, phosphorus, arsenic, and antimony can be used.

For example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the high concentration region 908 is preferably 5×10 ¹⁹ /cm ³ or more and 1×10 ²² /cm ³ or less.

The high-concentration region 908 to which a dopant imparting n-type conductivity is added has higher conductivity than other regions in the oxide semiconductor film 903. Therefore, by forming the high concentration region 908 in the oxide semiconductor film 903, the resistance between the source electrode 904 and the drain electrode 905 can be lowered.

In addition, when an In-Ga-Zn-based oxide semiconductor is used for the oxide semiconductor film 903, after nitrogen is added, the oxide in the high-concentration region 908 is subjected to heat treatment at 300°C to 600°C for about 1 hour. The semiconductor has a wurtzite crystal structure. Since the oxide semiconductor in the high concentration region 908 has a urtzite-type crystal structure, the conductivity of the high concentration region 908 can be further increased, and the resistance between the source electrode 904 and the drain electrode 905 can be lowered. In addition, in order to form an oxide semiconductor having a urtzite-type crystal structure and to effectively lower the resistance between the source electrode 904 and the drain electrode 905, when nitrogen is used as a dopant, in the high concentration region 908 It is preferable that the concentration of nitrogen atoms be 1×10 ²⁰ /cm ³ or more and 7 atoms% or less. However, even if the nitrogen atom is at a concentration lower than the above range, an oxide semiconductor having a urtzite crystal structure may be obtained.

Further, the oxide semiconductor film 903 may be formed of a CAAC-OS film. When the oxide semiconductor film 903 is composed of a CAAC-OS film, the conductivity of the oxide semiconductor film 903 can be increased compared to the case of amorphous, so that the resistance between the source electrode 904 and the drain electrode 905 Can lower.

Further, by lowering the resistance between the source electrode 904 and the drain electrode 905, even if the transistor 901 is miniaturized, a high ON current and high speed operation can be ensured. Further, by miniaturizing the transistor 901, the area occupied by the memory cell can be reduced, and the storage capacity per unit area of the cell array can be increased.

The transistor 911 shown in FIG. 10B is a source electrode 914 and a drain electrode 915 formed on the insulating film 912, and an active layer formed on the source electrode 914 and the drain electrode 915. The oxide semiconductor film 913 functioning as, the oxide semiconductor film 913, the gate insulating film 916 on the source electrode 914 and the drain electrode 915, and the oxide semiconductor film 913 on the gate insulating film 916 It has a gate electrode 917 provided in an overlapping position.

The transistor 911 shown in FIG. 10B is a top gate type in which a gate electrode 917 is formed on an oxide semiconductor film 913, and in addition, a source electrode 914 and a drain electrode 915 are formed. It is a bottom contact type formed under the oxide semiconductor film 913. Also, in the transistor 911, like the transistor 901, the source electrode 914, the drain electrode 915, and the gate electrode 917 do not overlap, so the source electrode 914, the drain electrode 915 and the gate The parasitic capacitance formed between the electrodes 917 can be suppressed to be small, and high-speed operation can be realized.

Further, the oxide semiconductor film 913 has a pair of high concentration regions 918 obtained by adding a dopant that imparts n-type conductivity to the oxide semiconductor film 913 after the gate electrode 917 is formed. Further, of the oxide semiconductor film 913, a region overlapping the gate electrode 917 with the gate insulating film 916 therebetween is the channel formation region 919. In the oxide semiconductor film 913, a channel formation region 919 is formed between a pair of high concentration regions 918.

The high concentration region 918 can be formed using an ion implantation method, similarly to the case of the high concentration region 908 of the transistor 901 described above. In addition, for the type of the dopant for forming the high concentration region 918, the case of the high concentration region 908 may be referred to.

For example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the high concentration region 918 is preferably 5×10 ¹⁹ /cm ³ or more and 1×10 ²² /cm ³ or less.

The high-concentration region 918 to which a dopant imparting n-type conductivity is added has higher conductivity than other regions in the oxide semiconductor film 913. Accordingly, by forming the high concentration region 918 in the oxide semiconductor film 913, the resistance between the source electrode 914 and the drain electrode 915 can be lowered.

In addition, when an In-Ga-Zn-based oxide semiconductor is used for the oxide semiconductor film 913, after nitrogen is added, heat treatment is performed at about 300°C to 600°C, so that the oxide semiconductor in the high concentration region 918 is It has a chite-shaped crystal structure. Since the oxide semiconductor in the high concentration region 918 has a urtzite crystal structure, the conductivity of the high concentration region 918 can be further increased, and the resistance between the source electrode 914 and the drain electrode 915 can be lowered. In addition, in order to form an oxide semiconductor having a urtzite-type crystal structure and effectively lower the resistance between the source electrode 914 and the drain electrode 915, when nitrogen is used as a dopant, the high concentration region 918 It is preferable that the concentration of nitrogen atoms be 1×10 ²⁰ /cm ³ or more and 7 atoms% or less. However, even if the nitrogen atom is at a concentration lower than the above range, an oxide semiconductor having a urtzite crystal structure may be obtained.

Further, the oxide semiconductor film 913 may be formed of a CAAC-OS film. When the oxide semiconductor film 913 is composed of a CAAC-OS film, the conductivity of the oxide semiconductor film 913 can be increased compared to the case of amorphous, and thus the resistance between the source electrode 914 and the drain electrode 915 Can lower.

Further, by lowering the resistance between the source electrode 914 and the drain electrode 915, even if the transistor 911 is miniaturized, a high ON current and high speed operation can be ensured. Further, by miniaturizing the transistor 911, the area occupied by the memory cell can be reduced, and the storage capacity per unit area of the cell array can be increased.

The transistor 921 shown in FIG. 10C includes an oxide semiconductor film 923 formed on the insulating film 922 and functioning as an active layer, a source electrode 924 formed on the oxide semiconductor film 923, and The drain electrode 925, the oxide semiconductor film 923, the gate insulating film 926 on the source electrode 924 and the drain electrode 925, and the gate insulating film 926 are provided at a position overlapping the oxide semiconductor film 923 It has a gate electrode 927. Further, the transistor 921 has a side wall 930 formed of an insulating film provided on the side of the gate electrode 927.

The transistor 921 shown in FIG. 10C is a top gate type in which a gate electrode 927 is formed on an oxide semiconductor film 923, and in addition, a source electrode 924 and a drain electrode 925 are formed. It is a top contact type formed on the oxide semiconductor film 923. In addition, in the transistor 921, like the transistor 901, the source electrode 924, the drain electrode 925, and the gate electrode 927 do not overlap, so the source electrode 924, the drain electrode 925, and the gate The parasitic capacitance formed between the electrodes 927 can be suppressed to be small, and high-speed operation can be realized.

In addition, the oxide semiconductor film 923 includes a pair of high concentration regions 928 obtained by adding a dopant that imparts n-type conductivity to the oxide semiconductor film 923 after the gate electrode 927 is formed, and a pair of Has a low concentration region 929 of. In addition, of the oxide semiconductor film 923, a region overlapping the gate electrode 927 with the gate insulating film 926 therebetween is the channel formation region 931. In the oxide semiconductor film 923, a pair of low concentration regions 929 is formed between a pair of high concentration regions 928, and a channel formation region 931 is formed between the pair of low concentration regions 929. Has been. The pair of low-concentration regions 929 are formed in a region of the oxide semiconductor film 923 that overlaps the sidewall 930 with the gate insulating film 926 therebetween.

The high concentration region 928 and the low concentration region 929 can be formed using an ion implantation method, similarly to the case of the high concentration region 908 of the transistor 901 described above. In addition, for the type of the dopant for forming the high concentration region 928, reference may be made to the case of the high concentration region 908.

For example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the high concentration region 928 is preferably 5×10 ¹⁹ /cm ³ or more and 1×10 ²² /cm ³ or less. Further, for example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the low concentration region 929 is preferably 5×10 ¹⁸ /cm ³ or more and less than 5×10 ¹⁹ /cm ³ .

The high-concentration region 928 to which a dopant imparting n-type conductivity is added has higher conductivity than other regions in the oxide semiconductor film 923. Accordingly, by providing the high-concentration region 928 in the oxide semiconductor film 923, the resistance between the source electrode 924 and the drain electrode 925 can be lowered. Further, by forming the low concentration region 929 between the channel formation region 931 and the high concentration region 928, the negative shift of the threshold voltage due to the short channel effect can be reduced.

In addition, when an In-Ga-Zn-based oxide semiconductor is used for the oxide semiconductor film 923, after nitrogen is added, heat treatment is performed at about 300°C to 600°C, so that the oxide semiconductor in the high concentration region 928 is It has a chite-shaped crystal structure. In addition, the low-concentration region 929 may also have a urachite-type crystal structure by the heat treatment, depending on the concentration of nitrogen. When the oxide semiconductor in the high concentration region 928 has a urtzite crystal structure, the conductivity of the high concentration region 928 can be further increased, and the resistance between the source electrode 924 and the drain electrode 925 can be lowered. In addition, in order to form an oxide semiconductor having a urtzite-type crystal structure and effectively lower the resistance between the source electrode 924 and the drain electrode 925, when nitrogen is used as a dopant, the concentration in the high concentration region 928 It is preferable that the concentration of nitrogen atoms be 1×10 ²⁰ /cm ³ or more and 7 atoms% or less. However, even if the nitrogen atom is at a concentration lower than the above range, an oxide semiconductor having a urtzite crystal structure may be obtained.

Further, the oxide semiconductor film 923 may be formed of a CAAC-OS film. When the oxide semiconductor film 923 is composed of a CAAC-OS film, the conductivity of the oxide semiconductor film 923 can be increased compared to the case of amorphous, so that the resistance between the source electrode 924 and the drain electrode 925 Can lower.

Further, by lowering the resistance between the source electrode 924 and the drain electrode 925, even if the transistor 921 is miniaturized, a high ON current and high speed operation can be ensured. Further, by miniaturizing the transistor 921, the area occupied by the memory cell can be reduced, and the storage capacity per unit area of the cell array can be increased.

The transistor 941 shown in FIG. 10D is a source electrode 944 and a drain electrode 945 formed on the insulating film 942, and an active layer formed on the source electrode 944 and the drain electrode 945. The oxide semiconductor film 943 functioning as, the oxide semiconductor film 943, the gate insulating film 946 on the source electrode 944 and the drain electrode 945, and the oxide semiconductor film 943 on the gate insulating film 946 It has a gate electrode 947 provided at an overlapping position. Further, the transistor 941 has a side wall 950 formed of an insulating film provided on the side of the gate electrode 947.

The transistor 941 shown in FIG. 10D is a top gate type in which a gate electrode 947 is formed on an oxide semiconductor film 943, and a source electrode 944 and a drain electrode 945 are It is a bottom contact type formed under the oxide semiconductor film 943. Also, in the transistor 941, like the transistor 901, the source electrode 944, the drain electrode 945, and the gate electrode 947 do not overlap, so the source electrode 944, the drain electrode 945, and the gate The parasitic capacitance formed between the electrodes 947 can be suppressed to be small, and high-speed operation can be realized.

Further, the oxide semiconductor film 943 includes a pair of high-concentration regions 948 obtained by adding a dopant that imparts n-type conductivity to the oxide semiconductor film 943 after the gate electrode 947 is formed, and a pair of Has a low concentration region 949 of. In addition, of the oxide semiconductor film 943, a region overlapping the gate electrode 947 with the gate insulating film 946 therebetween is a channel formation region 951. In the oxide semiconductor film 943, a pair of low concentration regions 949 are formed between a pair of high concentration regions 948, and a channel formation region 951 is formed between the pair of low concentration regions 949. Has been. The pair of low-concentration regions 949 are formed in a region of the oxide semiconductor film 943 that overlaps the sidewall 950 with the gate insulating film 946 therebetween.

The high concentration region 948 and the low concentration region 949 can be formed using an ion implantation method, similarly to the case of the high concentration region 908 of the transistor 901 described above. Further, for the type of the dopant for forming the high concentration region 948, the case of the high concentration region 908 may be referred to.

For example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the high concentration region 948 is preferably 5×10 ¹⁹ /cm ³ or more and 1×10 ²² /cm ³ or less. Further, for example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the low concentration region 949 is preferably 5×10 ¹⁸ /cm ³ or more and less than 5×10 ¹⁹ /cm ³ .

The high-concentration region 948 to which a dopant imparting n-type conductivity is added has higher conductivity than other regions in the oxide semiconductor film 943. Accordingly, by forming the high concentration region 948 in the oxide semiconductor film 943, the resistance between the source electrode 944 and the drain electrode 945 can be lowered. Further, by forming the low concentration region 949 between the channel formation region 951 and the high concentration region 948, the negative shift of the threshold voltage due to the short channel effect can be reduced.

In addition, when an In-Ga-Zn-based oxide semiconductor is used for the oxide semiconductor film 943, after nitrogen is added, heat treatment is performed at about 300°C to 600°C, so that the oxide semiconductor in the high concentration region 948 is It has a chite-shaped crystal structure. In addition, the low-concentration region 949 may also have a urachite-type crystal structure by the heat treatment, depending on the concentration of nitrogen. Since the oxide semiconductor in the high concentration region 948 has a urtzite crystal structure, the conductivity of the high concentration region 948 can be further increased and the resistance between the source electrode 944 and the drain electrode 945 can be lowered. In addition, in order to form an oxide semiconductor having a urtzite-type crystal structure and to effectively lower the resistance between the source electrode 944 and the drain electrode 945, when nitrogen is used as a dopant, in the high concentration region 948 It is preferable that the concentration of nitrogen atoms be 1×10 ²⁰ /cm ³ or more and 7 atoms% or less. However, even if the nitrogen atom is at a concentration lower than the above range, an oxide semiconductor having a urtzite crystal structure may be obtained.

Further, the oxide semiconductor film 943 may be formed of a CAAC-OS film. When the oxide semiconductor film 943 is composed of a CAAC-OS film, the conductivity of the oxide semiconductor film 943 can be increased compared to the case of amorphous, so the resistance between the source electrode 944 and the drain electrode 945 Can lower.

Further, by lowering the resistance between the source electrode 944 and the drain electrode 945, even if the transistor 941 is miniaturized, a high ON current and high speed operation can be ensured. Further, by miniaturizing the transistor 941, the area occupied by the memory cell can be reduced, and the storage capacity per unit area of the cell array can be increased.

In addition, in a transistor using an oxide semiconductor, as one of the methods of fabricating a high-concentration region functioning as a source region or a drain region by a self-aligning process, argon plasma treatment is performed by exposing the surface of the oxide semiconductor film to the plasma of the oxide semiconductor film. A method of reducing the resistivity of the exposed area is disclosed (S. Jeon et al. "180nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application", IEDM Tech. Dig., p.504, 2010.).

However, in the above fabrication method, after forming the gate insulating film, it is necessary to partially remove the gate insulating film in order to expose the portion that should become the source region or the drain region. Accordingly, when the gate insulating film is removed, the oxide semiconductor film of the lower layer is also partially over-etched, so that the film thickness of the portion which should become the source region or the drain region decreases. As a result, the resistance of the source region or the drain region is increased, and a defect in transistor characteristics due to over-etching is liable to occur.

In order to advance the miniaturization of the transistor, it is necessary to employ a dry etching method with high processing precision. However, the over-etching is likely to occur remarkably when a dry etching method in which the selectivity between the oxide semiconductor film and the gate insulating film cannot be sufficiently secured is employed.

For example, if the oxide semiconductor film is of sufficient thickness, over-etching is also not a problem, but when the channel length is set to 200 nm or less, the thickness of the oxide semiconductor film at the portion serving as the channel formation region is 20 nm or less, preferably in order to prevent the short channel effect. Preferably, it is required to be 10 nm or less. In the case of handling such a thin oxide semiconductor film, over-etching of the oxide semiconductor film is not preferable because it causes poor characteristics of the transistor.

However, as in one aspect of the present invention, the addition of the dopant to the oxide semiconductor film is performed without exposing the oxide semiconductor film and leaving the gate insulating film, thereby preventing over-etching of the oxide semiconductor film, thereby preventing excessive oxidation of the oxide semiconductor film. Damage can be alleviated. In addition, the interface between the oxide semiconductor film and the gate insulating film is kept clean. Therefore, the characteristics and reliability of the transistor can be improved.

This embodiment can be implemented in appropriate combination with the above embodiment.

(Embodiment 7)

In the memory device according to an aspect of the present invention, a transistor manufactured using a bulk single crystal semiconductor substrate may be used for a driving circuit. In Fig. 12, a cross-sectional view of a memory device in which a transistor using an oxide semiconductor and a capacitor element are formed on a transistor formed using a bulk single crystal semiconductor substrate is shown as an example.

The memory device shown in FIG. 12 covers an n-channel transistor 661 and a p-channel transistor 662 formed on a semiconductor substrate 660, and an n-channel transistor 661 and a p-channel transistor 662. A transistor 664 using an oxide semiconductor and a capacitor 665 formed on the insulating film 663 that is present are provided.

The transistor 664 is a transistor using an oxide semiconductor in its channel formation region, and illustrates a case in which it has the structure shown in the fourth embodiment, but may have the configuration shown in the fifth or sixth embodiment.

The semiconductor substrate 660 includes, for example, a single crystal silicon substrate having an n-type or p-type conductivity type, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, etc.). Can be used. In Fig. 12, a case in which a single crystal silicon substrate having n-type conductivity is used is illustrated.

Further, the n-channel transistor 661 and the p-channel transistor 662 are electrically separated by an insulating film 666 for element isolation. For the formation of the insulating film 666 for element isolation, a selective oxidation method (LOCOS (Local Oxidation of Silicon) method), a trench isolation method, or the like can be used.

In the region where the p-channel transistor 662 is formed, a region called a p-well 667 is formed by selectively introducing an impurity element imparting p-type conductivity. When using a semiconductor substrate having p-type conductivity, n-wells may be formed by selectively introducing an impurity element imparting n-type conductivity to a region in which the n-channel transistor 661 is formed.

This embodiment can be implemented in appropriate combination with the above embodiment.

(Embodiment 8)

It is preferable that the oxide semiconductor contains at least indium (In) or zinc (Zn). In particular, it is preferable to include In and Zn.

In addition, as a stabilizer for reducing fluctuations in the electrical characteristics of a transistor using an oxide semiconductor, one or more types selected from gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), or lanthanoids. It is preferable to have.

As lanthanoids, lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

For example, as an oxide semiconductor of a one-element metal containing indium (In) or zinc (Zn), indium oxide, zinc oxide, or the like can be used.

In addition, for example, as an oxide semiconductor of a binary metal containing indium (In) or zinc (Zn), In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, or the like can be used.

In addition, for example, as an oxide semiconductor of a ternary metal containing indium (In) or zinc (Zn), In-Ga-Zn oxide (also referred to as IZO), In-Sn-Zn oxide, Sn- Ga-Zn oxide, In-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd- Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide Oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, etc. You can use

In addition, for example, as an oxide semiconductor of a quaternary metal containing indium (In) or zinc (Zn), In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al- Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide, or the like can be used.

In addition, for example, an In-Ga-Zn-based oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is irrelevant. Further, metal elements other than In, Ga, and Zn may be contained.

For example, In:Ga:Zn=1:1:1(=1/3:1/3:1/3) or In:Ga:Zn=2:2:1(=2/5:2/5 An In-Ga-Zn-based oxide having an atomic ratio of :1/5) or an oxide near its composition can be used.

Or, In:Sn:Zn=1:1:1(=1/3:1/3:1/3), In:Sn:Zn=2:1:3(=1/3:1/6:1 /2) Alternatively, an In-Sn-Zn oxide having an atomic ratio of In:Sn:Zn=2:1:5 (=1/4:1/8:5/8) or an oxide near its composition may be used. .

However, the present invention is not limited to these, and a composition having an appropriate composition may be used according to the required semiconductor characteristics (mobility, threshold, gap, etc.). In addition, in order to obtain the required semiconductor properties, it is preferable that the carrier concentration or impurity concentration, the defect density, the atomic number ratio of the metal element and oxygen, the bonding distance between atoms, the density, etc. be appropriate.

The oxide semiconductor may be single crystal or non-single crystal. In the case of non-single crystal, it may be amorphous or polycrystalline. Further, a structure including a portion having crystallinity in the amorphous material may be used. Further, since amorphous has many defects, via morphous is preferable.

Some or all of the content of this embodiment can be implemented in combination with all other embodiments or examples.

(Embodiment 9)

In this embodiment, the c-axis is oriented, and at the same time, it has a triangular or hexagonal atomic arrangement when viewed from the ab plane, the surface or the interface, and in the c-axis, metal atoms are arranged in a layer shape or metal atoms and oxygen atoms are arranged in a layer shape. In the ab plane, an oxide containing a crystal (also referred to as CAAC: C Axis Aligned Crystal) in which the directions of the a-axis or the b-axis are different (rotated around the c-axis) will be described.

The oxide containing CAAC is a non-single crystal in a broad sense, and has an atomic arrangement of a triangle, a hexagonal, an equilateral triangle, or a regular hexagon when viewed from a direction perpendicular to the ab plane, and when viewed from a direction perpendicular to the c-axis direction, It refers to an oxide including a metal valence layer or a phase in which metal atoms and oxygen atoms are arranged in a layer shape.

CAAC is not a single crystal, but is not formed only of amorphous. In addition, although CAAC includes a crystallized portion (crystal portion), the boundary between one crystal portion and another crystal portion cannot be clearly discriminated in some cases.

Some of the oxygen constituting CAAC may be substituted with nitrogen. Further, the c-axis of the individual crystal portions constituting the CAAC may be aligned in a certain direction (for example, a direction perpendicular to the surface of the substrate supporting the CAAC, the surface of the CAAC, etc.). Alternatively, the normal line of the ab plane of each crystal part constituting the CAAC may be directed in a certain direction (eg, a direction perpendicular to the surface of the substrate supporting the CAAC, the surface of the CAAC, etc.).

CAAC is a conductor, a semiconductor, or an insulator depending on its composition and the like. In addition, it is transparent or opaque to visible light depending on its composition and the like.

As an example of such a CAAC, a triangular or hexagonal atomic arrangement is recognized when it is formed in a film shape and is observed in a direction perpendicular to the surface of the film or the surface of the supporting substrate, and when the cross section of the film is observed, metal atoms or metal atoms and An example is a crystal in which the layered arrangement of oxygen atoms (or nitrogen atoms) is recognized.

An example of the crystal structure contained in CAAC will be described in detail with reference to FIGS. 13A to 13E to 15A to 15C. In addition, unless otherwise noted, in Figures 13 (a) to (e) to Figure 15 (a) to (c), the upward direction is the c-axis direction, and the plane orthogonal to the c-axis direction is called the ab plane. do. In addition, when simply referring to the upper half and the lower half, it means the upper half and the lower half when the ab plane is the boundary. In addition, O surrounded by a circle in FIGS. 13A to 13E represents O in a quadruple coordination, and O surrounded by a double circle indicates an O in a third coordination.

In Fig. 13A, a structure having one 6-coordinated In and six 4th-coordinated oxygen atoms close to In (hereinafter, four-coordinated O) is shown. Here, a structure in which only adjacent oxygen atoms are shown per metal atom is called a small group. The structure of Fig. 13A takes an octahedral structure, but for simplicity, it is shown as a planar structure. In addition, in the upper half and the lower half of FIG. 13A, there are three O in the fourth coordination. The small group shown in Fig. 13A has zero charge.

Fig. 13B shows a structure having one Ga of 5 coordination, 3 oxygen atoms of 3 coordination close to Ga (hereinafter, O of 3 coordination), and two O of 4 coordination close to Ga. . All of the O in the third coordination exist on the ab side. In the upper half and the lower half of FIG. 13B, there is a four-coordinated O each. In addition, since In also takes 5 coordination, the structure shown in Fig. 13B can be taken. The small group shown in Fig. 13B has zero charge.

In Fig. 13C, a structure having one quadruple Zn and four quadruple O close to Zn is shown. In (c) of FIG. 13, there are one O in the upper half and three O in the lower half. Alternatively, there may be three four-coordinated O in the upper half of Fig. 13C, and one four-coordinated O in the lower half. The small group shown in Fig. 13C has zero charge.

Fig. 13D shows a structure having one Sn of 6 coordination and 6 O of 4 coordination close to Sn. In (d) of FIG. 13, there are three quadruple O's in the upper half and three quadruple O's in the lower half. The small group shown in Fig. 13D has a charge of +1.

In Fig. 13E, a small group containing two Zn is shown. In (e) of FIG. 13, there is one O in the upper half and one O in the lower half. The small group shown in Fig. 13E has a charge of -1.

Here, an aggregate of a plurality of small groups is referred to as a medium group, and an aggregate of a plurality of medium groups is referred to as a large group (also referred to as a unit cell).

Here, the rules for combining these small groups will be described. The three O's in the upper half of the six-coordinated In shown in Fig. 13A have three adjacent Ins each in the lower direction, and the three O's in the lower half each have three adjacent Ins in the upper direction. Have. One O in the upper half of Ga of 5-coordination shown in Fig. 13B has one proximity Ga in the downward direction, and one O in the lower half has one proximity Ga in the upward direction. One O in the upper half of the 4-coordination Zn shown in Fig. 13C has one adjacent Zn in the downward direction, and three O in the lower half each has three adjacent Zn in the upper direction. . In this way, the number of O in the upper direction of the metal atom and the number of adjacent metal atoms in the direction below the O are the same. Similarly, the number of O in the lower direction of the metal atom and the number of O The number of adjacent metal atoms in the direction is the same. Since O is quadratic, the sum of the number of adjacent metal atoms in the downward direction and the number of adjacent metal atoms in the upward direction is 4. Therefore, when the sum of the number of four-coordinated O in the upper direction of a metal atom and the number of four-coordinated O in the downward direction of another metal atom is four, two small groups having metal atoms can be bonded together. have. For example, when a 6-coordinated metal atom (In or Sn) is bonded with a 4-coordination O in the lower half, since there are 3 4-coordinated metal atoms (Ga or In) , Or it is bonded to any one of the metal atom (Zn) of the fourth coordination.

The metal atoms having these coordination numbers are bonded in the c-axis direction with O in the 4 coordination between them. In addition, in addition, a plurality of small groups are combined to form a middle group so that the total charge of the layer structure becomes zero.

Fig. 14(a) shows a model diagram of a middle group constituting the layer structure of an In-Sn-Zn-based oxide semiconductor. In Fig. 14B, a large group composed of three medium groups is shown. In addition, Fig. 14(C) shows the atomic arrangement when the layer structure of Fig. 14(b) is observed in the c-axis direction.

In (a) of FIG. 14, for simplicity, 3 coordination O is omitted, and 4 coordination O indicates only the number. For example, the upper half and lower half of Sn each have 3 4 coordination O. It is represented by 3 in a round circle. Similarly, in Fig. 14(a), in the upper half and the lower half of In, there is a four-coordinated O, respectively, and is represented by one of a round circle. Similarly, in (a) of FIG. 14, there is one quadruple O in the lower half, Zn with three quadruple O in the upper half, and one quadruple O in the upper half, and the lower half The half shows Zn with 3 quadruple O.

In Fig. 14A, in the middle group constituting the layer structure of the In-Sn-Zn-based oxide semiconductor, Sn in the upper half and the lower half of the four-coordinated O is three in order from the top, One O is combined with In in the upper half and lower half, and the In is combined with Zn, which has three quadruple O in the upper half, and 1 quadruple O in the lower half of Zn. The four-coordinated O is combined with In in the upper half and the lower half by three, and the In is combined with a small group consisting of two Zn with one quadruple O in the upper half, and the lower half of this sub-group It is a configuration in which 3 O of 4 coordination are combined with Sn in the upper half and lower half of each with one 4 coordination O in between. A plurality of these middle groups are combined to form a large group.

Here, in the case of O in the 3-coordination and O in the 4-coordination, the charge per bond can be considered as -0.667 and -0.5, respectively. For example, the charges of In (6 coordination or 5 coordination), Zn (4 coordination), and Sn (5 coordination or 6 coordination) are +3, +2, and +4, respectively. Accordingly, the small group containing Sn has a charge of +1. Therefore, in order to form a layer structure containing Sn, charge -1 to eliminate charge +1 is required. As a structure taking charge -1, as shown in Fig. 13E, a small group containing two Zn is exemplified. For example, if there is one small group containing Sn and one small group containing two Zn, the total charge of the layer structure can be set to zero in order to eliminate the charge.

Specifically, by repeating the large group shown in Fig. 14B, a crystal (In ₂ SnZn ₃ O ₈ ) of an In-Sn-Zn-based oxide semiconductor can be obtained. In addition, the layer structure of the obtained In-Sn-Zn-based oxide semiconductor can be represented by a composition formula of In ₂ SnZn ₂ O7 (ZnO) _m (m is 0 or a natural number).

In addition, in addition, In-Sn-Ga-Zn oxide, which is an oxide of a quaternary metal, In-Ga-Zn oxide (also referred to as IZO), an oxide of a ternary metal, In-Al-Zn oxide, Sn -Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In- Pr-Zn type oxide, In-Nd-Zn type oxide, In-Sm-Zn type oxide, In-Eu-Zn type oxide, In-Gd-Zn type oxide, In-Tb-Zn type oxide, In-Dy- Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, or binary metal oxide The same applies when phosphorus In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, etc. are used. to be.

For example, Fig. 15(a) shows a model diagram of a middle group constituting the layer structure of an In-Ga-Zn-based oxide semiconductor.

In (a) of FIG. 15, the middle group constituting the layer structure of the In-Ga-Zn-based oxide semiconductor has 3 O in the upper half and the In in the lower half in order from the top. One O bonds with Zn in the upper half, and three quadruple O of the lower half of Zn is interposed, and one O of four coordination bonds with Ga in the upper half and lower half, and the It is a configuration in which one four-coordinated O of the lower half of Ga is interposed, and three four-coordinated O are combined with In in the upper half and lower half. A plurality of these middle groups are combined to form a large group.

Fig. 15B shows a large group composed of three middle groups. In addition, FIG. 15(c) shows the atomic arrangement when the layer structure of FIG. 15(b) is observed from the c-axis direction.

Here, since the charges of In (6 coordination or 5 coordination), Zn (4 coordination), and Ga (5 coordination) are respectively +3, +2 and +3, the small group containing any one of In, Zn and Ga, The charge becomes zero. Therefore, if it is a combination of these small groups, the total charge of the middle groups is always zero.

In addition, the middle group constituting the layer structure of the In-Ga-Zn-based oxide semiconductor is not limited to the middle group shown in Fig. 15(a), and heavy groups having different arrangements of In, Ga, and Zn are combined. You can even take one large group.

Some or all of the content of this embodiment can be implemented in combination with all other embodiments or examples.

(Embodiment 10)

The mobility of an insulated gate transistor that is not limited to an oxide semiconductor and actually measured becomes lower than the original mobility for various reasons. Factors that lower the mobility are defects within the semiconductor or defects at the interface between the semiconductor and the insulating film, but using the Levinson model, the mobility can be theoretically derived when it is assumed that there are no defects inside the semiconductor. have.

That the semiconductor inherent mobility μ _0, μ is the mobility is measured, assuming that any potential barrier in the semiconductor (grain, etc.) is present, the mobility (μ) is represented by Equation 1 below.

E is the height of the potential barrier, k is the Boltman constant, and T is the absolute temperature. In addition, assuming that the potential barrier originates from a defect, in the Levinson model, the potential barrier E is represented by the following equation (2).

e is the small amount of electricity, N is the average defect density per unit area in the channel formation region, ε is the dielectric constant of the semiconductor, n is the number of carriers in the channel formation region per unit area, C _ox is the capacity per unit area, V _g is the gate The voltage, t, is the thickness of the channel formation region. In addition, in the case of a semiconductor film having a thickness of 30 nm or less, the thickness of the channel formation region may be the same as that of the semiconductor film.

The drain current I _d in the linear region is represented by the following equation (3).

In addition, L is a channel length, W is a channel width, and it is assumed that L = W = 10 μm. In addition, V _d is the drain voltage.

If both sides of Equation 3 are divided by V _g and the logarithm of both sides is taken, the following Equation 4 is obtained.

The right side of Equation 4 is a function of V _g . As can be seen from Equation 4, the defect density N is obtained from the slope of a straight line with the vertical axis as ln (I _d /V _g ) and the horizontal axis as 1/V _g . That is, the defect density can be evaluated from the I _d -V _g characteristics of the transistor. In an oxide semiconductor in which the ratio of indium (In), tin (Sn), and zinc (Zn) is In:Sn:Zn=1:1:1, the defect density (N) is about 1×10 ¹² /cm ² .

Based on the thus-obtained defect density and the like, μ ₀ =120 cm ² /Vs is derived. The mobility (μ) measured in the defective In-Sn-Zn oxide semiconductor is about 35cm ² /Vs. However, the mobility (μ ₀ ) of the oxide semiconductor without defects within the semiconductor and at the interface between the semiconductor and the insulating film can be expected to be 120 cm ² /Vs.

However, even if there are no defects in the semiconductor, the transport characteristics of the transistor are affected by scattering at the interface between the channel formation region and the gate insulating film. In other words, the mobility (μ ₁ ) at a location deviated by x from the gate insulating film interface is represented by the following equation (5).

D is the electric field in the direction of the gate electrode, and B and G are constants. B and G can be obtained from actual measurement results, and from the above measurement results, B = 4.75 x 10 ⁷ cm/s and G = 10 nm (depth of interfacial scattering). It can be seen that when D increases (that is, when the gate voltage increases), the second term on the right side of Equation 5 increases, so that the mobility μ ₁ decreases.

Fig. 16 shows the calculation result of the mobility (μ ₂ ) of a transistor using an ideal oxide semiconductor without defects inside the semiconductor for the channel formation region. In addition, a soft Sentaurus Device manufactured by Synopsis was used for calculation. In the calculation, the band gap, electron affinity, relative dielectric constant, and thickness of the oxide semiconductor were respectively 2.8 electron volts, 4.7 electron volts, and 15 and 15 nm. These values are obtained by measuring the thin film formed by the sputtering method.

In addition, the work functions of the gate electrode, the source electrode, and the drain electrode were set to 5.5 electron volts, 4.6 electron volts, and 4.6 electron volts, respectively. In addition, the thickness of the gate insulating film was set to 100 nm and the relative dielectric constant was set to 4.1. Both the channel length (L) and the channel width (W) are 10 μm, and the drain voltage (V _d ) is 0.1V.

As shown in the calculation result of FIG. 16, when the gate voltage (V _g ) is 1 V, the mobility (μ ₂ ) has a peak of 100 cm ² /Vs or more, but when the gate voltage (V _g ) is higher, interfacial scattering This increases and the mobility (μ ₂ ) decreases. Further, in order to reduce interfacial scattering, it is preferable to flatten the surface of the semiconductor film at the atomic level (Atomic Layer Flatness).

The characteristics in the case of fabricating a fine transistor using an oxide semiconductor having such a mobility were calculated. The transistor used in the calculation was an oxide semiconductor film in which a channel formation region was sandwiched between a pair of n-type semiconductor regions. The resistivity of a pair of n-type semiconductor regions was calculated as 2×10 ^-3 Ωcm. Further, the channel length (L) was calculated as 33 nm and the channel width (W) was 40 nm. Further, assuming that the sidewall of the gate electrode has a sidewall, the semiconductor region overlapping the sidewall was calculated as an offset region. Synopsis software, Sentaurus Device, was used for calculation.

17A to 17C are the calculation results of the dependence of the drain current (I _d , solid line) and the mobility (μ, dotted line) of the transistor on the gate voltage (V _g , the potential difference between the gate electrode and the source electrode). . The drain current I _{d is} calculated by setting the drain voltage (V _d , the potential difference between the drain electrode and the source electrode) to +1 V, and the mobility (μ) by setting the drain voltage to +0.1 V.

Fig. 17(a) is calculated by setting the thickness of the gate insulating film to 15 nm. Fig. 17B is calculated by setting the thickness of the gate insulating film to 10 nm. Fig. 17C is calculated by setting the thickness of the gate insulating film to 5 nm. As the gate insulating film becomes thinner, the drain current I _d (off current) in the off state in particular decreases significantly. On the other hand, there is no noticeable change in the peak value of the mobility (μ) or the drain current I _d (on current) in the ON state.

18A to 18C show the gate voltage (V) of the drain current (I _d ) (solid line) and mobility (μ) (dotted line) with the offset length (side wall length) Loff of 5 nm. _g ) indicates dependence. The drain current I _{d is} calculated by setting the drain voltage V _d to +1 V, and the mobility µ using the drain voltage V _d to +0.1 V. Fig. 18A is calculated by setting the thickness of the gate insulating film to 15 nm. Fig. 18B is calculated by setting the thickness of the gate insulating film to 10 nm. FIG. 18C shows the thickness of the gate insulating film calculated as 5 nm.

19A to 19C show the gate voltage dependence of the drain current (I _d ) (solid line) and mobility (μ) (dotted line) of the offset length (side wall length) (Loff) of 15 nm. Show. The drain current I _{d is} calculated by setting the drain voltage V _d to +1 V, and the mobility µ using the drain voltage V _d to +0.1 V. Fig. 19(a) is calculated by setting the thickness of the gate insulating film to 15 nm. In FIG. 19B, the thickness of the gate insulating film was calculated as 10 nm. FIG. 19C shows the thickness of the gate insulating film calculated as 5 nm. In both cases, as the gate insulating film becomes thinner, the off current remarkably decreases, while there is no noticeable change in the peak value of the mobility [mu] or the on current.

In addition, the peak of mobility (μ) is about 80 cm ² /Vs in FIGS. 17A to 17C, but about 60 cm ² /Vs in FIGS. 18A to 18C, In a) to (c), about 40 cm ² /Vs and the offset length Loff decreases as the increase. In addition, there is a similar tendency for the off current. On the other hand, the on current decreases with an increase in the offset length Loff, but is much more gentle compared to the decrease in the off current. In addition, it was found that the gate voltage (V _g ) was around 1V, and the drain current (I _d ) exceeded 10 μA required in a memory device or the like.

Some or all of the content of this embodiment can be implemented in combination with all other embodiments or examples.

[Example 1]

The storage device according to an aspect of the present invention has low power consumption, high-speed operation, and high reliability due to high storage capacity per unit area. Accordingly, by using the memory device according to an aspect of the present invention, an electronic device with low power consumption, an electronic device capable of high-speed operation, a small electronic device, and an electronic device with high reliability can be provided.

A storage device according to an aspect of the present invention includes a display device, a notebook-type personal computer, and an image reproducing device equipped with a recording medium (typically, a recording medium such as a DVD: Digital Versatile Disc can be played back and the image can be displayed. Devices with a display). In addition, as electronic devices that can use the storage device according to an aspect of the present invention, mobile phones, portable game machines, portable information terminals, electronic books, video cameras, digital still cameras, goggles-type displays (head mounted displays), and navigation systems. Systems, sound reproduction devices (car audio, digital audio player, etc.), copiers, facsimile machines, printers, printers, multifunction printers, automatic teller machines (ATMs), and vending machines. Specific examples of these electronic devices are shown in Figs. 11A to 11C.

11A is a portable game machine, a case 7031, a case 7032, a display portion 7033, a display portion 7034, a microphone 7035, a speaker 7036, operation keys 7037, and a stylus 7038. ), etc. The memory device according to an aspect of the present invention can be used in an integrated circuit for controlling driving of a portable game machine. By using the memory device according to an aspect of the present invention in an integrated circuit for controlling the driving of a portable game machine, a portable game machine with low power consumption, a portable game machine capable of high-speed operation, a small portable game machine, or a portable game machine with high reliability is provided. can do. In addition, although the portable game machine shown in Fig. 11A has two display portions 7033 and a display portion 7034, the number of display portions of the portable game machine is not limited to this.

Fig. 11B is a mobile phone, and has a case 7041, a display unit 7042, an audio input unit 7043, an audio output unit 7044, an operation key 7045, a light receiving unit 7046, and the like. By converting the light received by the light receiving unit 7046 into an electric signal, an external image can be acquired. The storage device according to an aspect of the present invention can be used in an integrated circuit for controlling driving of a mobile phone. By using the memory device according to an aspect of the present invention in an integrated circuit for controlling driving of a mobile phone, a mobile phone with low power consumption, a mobile phone capable of high-speed operation, a small mobile phone, or a highly reliable mobile phone is provided. can do.

Fig. 11C is a portable information terminal, and has a case 7051, a display portion 7052, operation keys 7053, and the like. In the portable information terminal shown in Fig. 11C, a modem may be incorporated in the case 7051. The memory device according to an aspect of the present invention can be used in an integrated circuit for controlling driving of a portable information terminal. By using the memory device according to an aspect of the present invention in an integrated circuit for controlling driving of a portable information terminal, a portable information terminal with low power consumption, a portable information terminal capable of high-speed operation, a small portable information terminal, or a highly reliable A portable information terminal can be provided.

This embodiment can be implemented in appropriate combination with the above embodiment.

[Example 2]

A transistor using an oxide semiconductor containing In, Sn, and Zn can obtain good characteristics by heating a substrate to form a film when forming an oxide semiconductor, or by performing heat treatment after forming an oxide semiconductor film. In addition, it is preferable that In, Sn, and Zn are each contained in a composition ratio of 5 atomic% or more.

By intentionally heating the substrate after forming the oxide semiconductor film containing In, Sn, and Zn, it becomes possible to improve the mobility of the transistor. Further, the threshold voltage of the n-channel transistor can be positively shifted. By positively shifting the threshold voltage of the n-channel transistor, the absolute value of the voltage for maintaining the off state of the n-channel transistor can be lowered, thereby reducing power consumption. Further, when the threshold voltage of the n-channel transistor is positively shifted and the threshold voltage is set to 0 V or more, it becomes possible to form a normally off-type transistor.

Hereinafter, characteristics of a transistor using an oxide semiconductor containing In, Sn, and Zn are shown.

(Common conditions for samples A to C)

A target of In:Sn:Zn=1:1:1 was used as the composition ratio, and the gas flow ratio was Ar/O2=6/9sccm, the film formation pressure was 0.4Pa, and the film formation power was 100W, so that the thickness was 15 nm. An oxide semiconductor film was formed. Next, the oxide semiconductor film was etched into an island shape. Then, a tungsten layer was formed on the oxide semiconductor film to a thickness of 50 nm, followed by etching to form a source electrode and a drain electrode.

Next, using a plasma CVD method, a silicon oxynitride film (SiON) was formed to a thickness of 100 nm using silane gas (SiH ₄ ) and dinitrogen monoxide (N ₂ O) to form a gate insulating layer. Next, tantalum nitride was formed to a thickness of 15 nm, tungsten was formed to a thickness of 135 nm, and these were etched to form a gate electrode. Further, by using the plasma CVD method, a silicon oxynitride film (SiON) was formed to have a thickness of 300 nm, and a polyimide film was formed to have a thickness of 1.5 μm to obtain an interlayer insulating film.

Next, a contact hole was formed in the interlayer insulating film, a first titanium film was formed to a thickness of 50 nm, an aluminum film was formed to a thickness of 100 nm, a second titanium film was formed to a thickness of 50 nm, and these were etched. A measurement pad was formed.

As described above, a semiconductor device having a transistor was formed.

(Sample A)

Sample A did not intentionally heat the substrate during the formation of the oxide semiconductor film. In addition, Sample A was after the formation of the oxide semiconductor film, and no heat treatment was performed before the etching processing of the oxide semiconductor film.

(Sample B)

In Sample B, an oxide semiconductor film was formed while the substrate was heated to 200°C. In addition, Sample B was after the formation of the oxide semiconductor film, and no heat treatment was performed before the etching processing of the oxide semiconductor film. The reason for film formation while the substrate is heated is to drive away hydrogen serving as a donor from the oxide semiconductor film.

(Sample C)

In Sample C, the oxide semiconductor film was formed while the substrate was heated to 200°C. In addition, Sample C was after the formation of the oxide semiconductor film, and before etching the oxide semiconductor film, heat treatment was performed at 650° C. for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 650° C. for 1 hour in an oxygen atmosphere. The reason for performing the heat treatment at 650°C for 1 hour in a nitrogen atmosphere is to drive away hydrogen serving as a donor from the oxide semiconductor film.

In addition, oxygen is also released in the heat treatment for removing hydrogen serving as a donor from the oxide semiconductor film, and oxygen vacancies serving as carriers in the oxide semiconductor film are also generated. Therefore, by performing a heat treatment at 650°C for 1 hour in an oxygen atmosphere, the effect of reducing oxygen vacancies was aimed at.

(Samples A to C transistor characteristics)

Fig. 20(a) shows the initial characteristics of the transistor of sample A. Fig. 20B shows the initial characteristics of the transistor of Sample B. Fig. 20C shows the initial characteristics of the transistor of Sample C.

The mobility of the transistor of Sample A was 18.8 cm ² /Vs. The mobility of the transistor of Sample B was 32.2 cm ² /Vs. The mobility of the transistor in Sample C was 34.5 cm ² /Vs.

Here, the cross section of the oxide semiconductor film formed by the same film formation method as Samples A to C was observed with a transmission microscope (TEM), and the sample formed by the same film formation method as Sample B and Sample C, which was subjected to substrate heating at the time of film formation. Crystallinity was confirmed.

Surprisingly, the sample subjected to substrate heating at the time of film formation had a crystalline portion and an amorphous portion, and was crystalline in which the orientation of the crystalline portion was aligned in the c-axis orientation. In a typical polycrystal, since the orientations of the crystalline portions are not aligned and face each direction, the sample obtained by heating the substrate at the time of film formation can be said to have a new crystal structure that has not existed before.

In addition, comparing (a) to (c) of Figs. 20, since the hydrogen element serving as a donor can be removed by heating the substrate during film formation or by performing heat treatment after film formation, the n-channel type It can be seen that the threshold voltage of the transistor can be positively shifted. That is, the threshold voltage of Sample B, which heated the substrate at the time of film formation, is positively shifted from the threshold voltage of Sample A, which did not heat the substrate at the time of film formation.

In addition, when comparing the sample B and the sample C subjected to substrate heating at the time of film formation, it can be seen that the sample C subjected to heat treatment after film formation is positively shifted from the sample B not subjected to heat treatment after film formation. In addition, since light elements such as hydrogen are more likely to be released as the temperature of the heat treatment increases, hydrogen is more likely to be released as the temperature of the heat treatment increases. Therefore, it was considered that a positive shift can be achieved by further increasing the temperature of the heat treatment at the time of film formation or after film formation.

(Gate BT stress test results of Sample B and Sample C)

The gate BT stress test was performed on Sample B (without heat treatment after film formation) and Sample C (with heat treatment after film formation).

First, the substrate temperature was set to 25°C and V _{d was set} to 10 V, and the Vg-I _d characteristics of the transistor were measured, and the characteristics of the transistor before heating and application of a positive high voltage were measured. Next, the substrate temperature was set to 150° C. and V _{d was set} to 0.1 V. Next, 20 V was applied to V _g applied to the gate insulating film, and held as it is for 1 hour. Next, V _{g was set} to 0V. Next, V _g -I _d of the transistor was measured with a substrate temperature of 25°C and V _d of 10 V, and the characteristics of the transistor after heating and application of a positive high voltage were measured.

In this way, comparing the characteristics of the transistors before and after heating and applying a positive high voltage is referred to as a positive BT test.

On the other hand, first, the substrate temperature was set to 25 DEG C and V _{d was set} to 10 V, and the V _g -I _d characteristics of the transistor were measured, and the characteristics of the transistor before heating and negative high voltage application were measured. Next, the substrate temperature was set to 150° C. and V _{d was set} to 0.1 V. Next, -20V was applied as V _g to the gate insulating film, and it was kept as it is for 1 hour. Next, V _{g was set} to 0V. Next, V _g -I _d of the transistor was measured with a substrate temperature of 25°C and V _d of 10 V, and the characteristics of the transistor after heating and negative high voltage application were measured.

As described above, comparison of the characteristics of the transistors before and after heating and applying a negative high voltage is referred to as a negative BT test.

Fig. 21(a) shows the positive BT test result of Sample B, and Fig. 21(b) shows the negative BT test result of Sample B. Fig. 22(a) shows the positive BT test result of Sample C, and Fig. 22(b) shows the negative BT test result of Sample C. The positive BT test and the negative BT test are tests to determine the deterioration state of the transistor. Referring to Figs. 21A and 22A, by performing at least the positive BT test processing, the threshold voltage is positively shifted. I knew I could do it.

In particular, in Fig. 21(a), it can be seen that the transistor is normally off by performing the positive BT test. Accordingly, it has been found that by performing the process of the positive BT test in addition to the heat treatment at the time of transistor fabrication, the positive shift of the threshold voltage can be promoted and a normally off-type transistor can be formed.

23 shows the relationship between the off-current of the transistor of Sample A and the inverse of the substrate temperature (absolute temperature) during measurement. Here, the numerical value (1000/T) obtained by multiplying the reciprocal of the substrate temperature at the time of measurement by 1000 is taken as the horizontal axis. In addition, in Fig. 23, the amount of current in the case of a channel width of 1 μm is shown.

When the substrate temperature was 125°C (1000/T is about 2.51), it was 1×10 ^-19 A or less. When the substrate temperature was 85°C (1000/T is about 3.66), it was 1×10 ^-20 A or less. That is, it was found that the off current was very low compared to the transistor using the silicon semiconductor. Further, since the lower the temperature, the lower the off current, so it is clear that the lower the off current is at room temperature.

100: memory cell 101: cell array
102: driving circuit 103: word line driving circuit
104: data line driving circuit 105: feed point
106: feeding point 107: feeding point
108: feed point 109: transistor
110: capacitor 230: transistor
260: transistor 262: operational amplifier
601: transistor 602: gate electrode
603: gate insulating film 604: oxide semiconductor film
605: conductive film 606: conductive film
607: insulating film 611: transistor
612: gate electrode 613: gate insulating film
614: oxide semiconductor film 615: conductive film
616: conductive film 617: insulating film
618: channel passivation layer 621: transistor
622: gate electrode 623: gate insulating film
624: oxide semiconductor film 625: conductive film
626: conductive film 627: insulating film
641: transistor 642: gate electrode
643: gate insulating film 644: oxide semiconductor film
645: conductive film 646: conductive film
647: insulating film 660: semiconductor substrate
661: n-channel transistor 662: p-channel transistor
663: insulating film 664: transistor
665: capacitive element 666: insulating film for element isolation
667: p well 700: substrate
701: insulating film 702: semiconductor film
703: gate insulating film 704: gate electrode
705: channel formation region 706: impurity region
707: insulating film 708: insulating film
709: insulating film 710: conductive film
711: conductive film 712: conductive film
713: insulating film 714: insulating film
715: oxide semiconductor film 716: conductive film
717: conductive film 718: conductive film
719: gate insulating film 720: gate electrode
721: conductive film 722: insulating film
725: opening 726: wiring
727: insulating film 800: memory device
801: cell array 802: driving circuit
803: input/output buffer 804: word line driving circuit
805: data line driving circuit 806: control circuit
807: row decoder 808: level shifter
809: buffer 810: column decoder
811: level shifter 812: selector
813: circuit 901: transistor
902: insulating film 903: oxide semiconductor film
904: source electrode 905: drain electrode
906: gate insulating film 907: gate electrode
908: high concentration region 909: channel formation region
911: transistor 912: insulating film
913: oxide semiconductor film 914: source electrode
915: drain electrode 916: gate insulating film
917: gate electrode 918: high concentration region
919: channel formation region 921: transistor
922: insulating film 923: oxide semiconductor film
924: source electrode 925: drain electrode
926: gate insulating film 927: gate electrode
928: high concentration area 929: low concentration area
930: side wall 931: channel formation region
941: transistor 942: insulating film
943: oxide semiconductor film 944: source electrode
945: drain electrode 946: gate insulating film
947: gate electrode 948: high concentration region
949: low concentration area 950: side wall
951: channel formation region 7031: case
7032: case 7033: display
7034: display unit 7035: microphone
7036: speaker 7037: operation keys
7038: stylus 7041: case
7042: display unit 7043: voice input unit
7044: audio output unit 7045: operation key
7046: light receiving unit 7051: case
7052: display unit 7053: operation key

Claims (6)

As a semiconductor device,
Circuit part;
An insulating film over the circuit part; And
Memory cell array on the insulating layer
Including, the memory cell array,
A plurality of first memory cells positioned in the first area;
A plurality of second memory cells positioned in the second area;
A plurality of third memory cells located in the third area;
A plurality of fourth memory cells positioned in the fourth area;
A plurality of word lines; And
Multiple data lines
Including,
The plurality of word lines are electrically connected to the circuit unit through a plurality of first contact holes,
The plurality of data lines are electrically connected to the circuit unit through a plurality of second contact holes,
The plurality of first contact holes are between the first region and the second region, and between the third region and the fourth region,
The plurality of second contact holes are between the first region and the third region, and between the second region and the fourth region,
The plurality of first contact holes are arranged along the plurality of data lines,
The plurality of second contact holes are arranged along the plurality of word lines. As a semiconductor device,
Circuit part;
An insulating film over the circuit part; And
Memory cell array on the insulating layer
Including, the memory cell array,
A plurality of first memory cells positioned in the first area;
A plurality of second memory cells positioned in the second area;
A plurality of word lines; And
Multiple data lines
Including,
The plurality of word lines are electrically connected to the circuit unit through a plurality of contact holes,
The plurality of data lines are electrically connected to the circuit unit,
The plurality of contact holes are between the first region and the second region,
The plurality of contact holes are arranged along the plurality of data lines. As a semiconductor device,
Circuit part;
An insulating film over the circuit part; And
Memory cell array on the insulating layer
Including, the memory cell array,
A plurality of first memory cells positioned in the first area;
A plurality of second memory cells positioned in the second area;
A plurality of word lines; And
Multiple data lines
Including,
The plurality of word lines are electrically connected to the circuit unit,
The plurality of data lines are electrically connected to the circuit unit through a plurality of contact holes,
The plurality of contact holes are between the first region and the second region,
The plurality of contact holes are arranged along the plurality of word lines. The method according to any one of claims 1 to 3,
One of the plurality of first memory cells includes a transistor,
The semiconductor device, wherein the transistor includes an oxide semiconductor film including a channel formation region. The method of claim 4,
The semiconductor device, wherein the oxide semiconductor film contains indium and zinc. The method of claim 4,
The semiconductor device, wherein the concentration of hydrogen in the oxide semiconductor film is 1×10 ¹⁹ /cm ³ or less.

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