JPH02148763A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To simplify the process of manufacture by making only one layer including a bit line shared by every layer formed of a work line and a memory cell. CONSTITUTION:n layers each formed of a plurality of memory cells 3 respectively connected to a plurality of word lines 5 are laminated, and one layer of a plurality of bit lines 4 is provided on the top. The gate of a NMOS transistor 1 of cells 3 of each layer is connected with the line 5 of each layer, the source is connected with one end of an electrostatic capacity 2 of each layer, and the drain is connected with the line 4 of the uppermost part. The cells of each layer are commonly, i.e., perpendicularly connected to the line 4. Another one end of the capacity 2 is connected to counterpolar terminal commonly to all the cells 3. Thus, an increase in wirings due to the multilayer of a memory cell array can be suppressed to minimum, and problems of flattening due to the multilayer, low temperature of a process, etc., can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device configured by stacking memory cell arrays in multiple nodes.

[Conventional technology]

Conventionally, this type of semiconductor memory device has a memory cell array as shown in FIG. FIG. 3 shows an example of a memory cell array of a dynamic semiconductor memory device. Here, the dynamic memory cell 3 consists of 8 MO8 transistors 1 and capacitors 2 each.
The word IvJ! is connected to the gate of 8MO8 transistor 1. 5 is connected, the drain is connected to the bit line 4, the source is connected to one terminal of the capacitor 12t2, and the other terminal of the static capacitor 81k2 is connected to the opposite terminal common to the memory cells ( (not shown).

Word lines 5 and bit lines 4 are arranged in a grid pattern, and memory cells 3 are arranged at points where the word lines 5 and bit lines 4 intersect. Read selection of memory cell 3 is as follows: selection of word line 5 → transfer of memory cell data to bit line 4 (data of all memory cells connected to the selected word line is transferred to bit line 4) → bit Line data amplification (performed by a sense amplifier)→bit line 4 selection is performed in this order.

In a semiconductor memory device using a memory cell array 3 as shown in FIG. 3, a configuration for increasing the storage capacity i' is as follows.
The first method is to simply expand the memory cell array two-dimensionally, the second method is to increase the storage capacity per unit area by reducing all elements, wiring widths, and wiring spacing. There is a third method of increasing the storage capacity per unit area by stacking memory cell arrays in multiple layers.

The first method of simply expanding the memory cell array in a planar manner is limited by the size of the package to be accommodated and the size of the semiconductor substrate used, so this method is not normally used alone. Conventionally, the second method of shrinking has been used, but there are physical and elemental limits to simply shrinking, and once the limits of shrinking are reached, the memory cell array can be multi-layered three-dimensionally. A third method of overlapping is used.

[Problem to be solved by the invention]

A semiconductor memory device constructed by stacking the conventional memory cell arrays described above in multiple layers is effective for increasing storage capacity, but multilayering is extremely difficult in terms of manufacturing process.

For example, if the number of wiring layers increases, it becomes difficult to planarize each layer, or if aluminum wiring, which is sensitive to heat, is used in each layer, it becomes necessary to lower the temperature of the process.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device which solves the above-mentioned problems, has a simple manufacturing process, is easy to manufacture, and does not have to worry about lowering the temperature of the process.

[Means to solve the problem]

The structure of the semiconductor memory device of the present invention includes a plurality of bit lines,
A memory cell array including a plurality of word lines and a memory cell arranged at a position where the word line and the bit line intersect as a first layer, and a memory cell having a plurality of word lines and a plurality of memory cells. - At least one layer of the array is arranged as a unit layer below the first layer, and the bit lines of the unit layer are connected to corresponding bit lines of the first layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, in this embodiment, a dynamic memory cell composed of one NMO transistor 1 and one capacitive element 2 is used as the memory cell 3. A plurality of memory cells 3 each connected to a plurality of word lines 5 are stacked in n layers, and one layer of a plurality of bit lines 4 is provided on top of the n layers, and the gate of the NMO8 transistor 1 of the memory cell 3 in each layer is stacked. is connected to the word line 5 of each layer, the source is connected to one end of the capacitance 2 of each layer, and the drain is connected to the uppermost bit line 4.

This bit line 4 connects the memory cells of each layer in common, that is, in the vertical direction. Further, the other end of the capacitor 2 is connected to a common opposite terminal of all memory cells 3.

This embodiment basically uses a layer consisting of a plurality of word lines 5 and memory cells 3 in a semiconductor memory device having a memory cell array consisting of a plurality of words M5, bit lines 4, and memory cells 3. It is characterized by the provision of multiple layers, and a single layer consisting of bit lines 4, word lines 5, and memory cells 3 connected to memory cells 3 in each layer.

The selection method for the memory cells 3 is the same as in the conventional example, but it is also necessary to perform word selection in the vertical direction.

In other words, when selecting arbitrary memory cells in the n-th layer one after another, select the word in the n-th layer, transfer the data to the bit line 4 in the top layer, and after amplifying the data on this bit line 4,
Bit [4 is selected, and so on.

FIG. 2 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention. In FIG. 2, in this embodiment, the memory cell 3 is a static memory cell. This case can also be realized with substantially the same reliability as in the first embodiment. The operation is the same as in the two-dimensional case, only that selection in the vertical direction is required. A static write memory cell 3 is provided at a position where a bit line pair 4 and a word line 5 intersect.

The bit line pairs 4 are vertically connected and connected to memory cells in each layer. Word lines 5 are prepared for each layer.

〔Effect of the invention〕

As explained above, the present invention provides a semiconductor memory device in which memory cell arrays are stacked in multiple layers, in which only layers consisting of word lines and memory cells are stacked in multiple layers, and a single layer in which bit lines are added. By connecting the bit lines of the memory cells of each layer and the bit lines of the - layer in the vertical direction, it is possible to minimize the increase in wiring due to multilayer memory cell arrays. This has a great effect in solving problems such as flattening and lowering the process temperature, which are important issues in multilayering. This is because when stacking conventional memory cell arrays that combine word lines, bit lines, and memory cells, it is necessary to provide bit lines in each layer, whereas in the present invention, bit lines are provided in each layer.
By sharing only one additional layer in each layer composed of word lines and memory cells, it is possible to reduce the number of bit lines.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIG.
The figure is a circuit diagram of a conventional memory cell array. 1...8MO8 transistor, 2...
Capacitance, 3...Memory cell, 4...
Bit line, 5 old... word line. Agent Patent Attorney Shinkari Uchihara! \、

Claims (1)

[Claims] A first layer is a memory cell array having a plurality of bit lines, a plurality of word lines, and a memory cell arranged at a position where the word line and the bit line intersect. a memory cell array having at least one unit layer disposed below the first layer;
A semiconductor memory device, wherein the bit line of the unit layer is connected to a corresponding bit line of the first layer.