WO2008065927A1 - Organic thin film transistor, organic composite electronic element, method for manufacturing such transistor and element, and display device and memory - Google Patents

Organic thin film transistor, organic composite electronic element, method for manufacturing such transistor and element, and display device and memory Download PDF

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Publication number
WO2008065927A1
WO2008065927A1 PCT/JP2007/072424 JP2007072424W WO2008065927A1 WO 2008065927 A1 WO2008065927 A1 WO 2008065927A1 JP 2007072424 W JP2007072424 W JP 2007072424W WO 2008065927 A1 WO2008065927 A1 WO 2008065927A1
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WIPO (PCT)
Prior art keywords
film
transistor
organic
low dielectric
forming
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PCT/JP2007/072424
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French (fr)
Japanese (ja)
Inventor
Mamoru Baba
Rongbin Ye
Takeyoshi Katoh
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Zeon Corporation
Iwate University
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Priority claimed from JP2006319184A external-priority patent/JP2010034090A/en
Priority claimed from JP2006319186A external-priority patent/JP2010034092A/en
Priority claimed from JP2006319185A external-priority patent/JP2010034091A/en
Application filed by Zeon Corporation, Iwate University filed Critical Zeon Corporation
Publication of WO2008065927A1 publication Critical patent/WO2008065927A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40111Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B51/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B51/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40Organic transistors
    • H10K10/46Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462Insulated gate field-effect transistors [IGFETs]
    • H10K10/468Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/474Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure

Definitions

  • Organic thin film transistor organic composite electronic device, manufacturing method thereof, display device, and memory
  • the present invention relates to an organic thin film transistor, a method for producing the organic thin film transistor, and a display device such as an organic EL display device including the organic thin film transistor.
  • the present invention also relates to an organic composite electronic device including an organic thin film transistor and a high dielectric capacitor, a method for manufacturing the organic composite electronic device, and an organic semiconductor memory using the organic composite electronic device.
  • the present invention relates to an organic composite electronic device comprising two or more organic thin film transistors having different performances, a method for producing the organic composite electronic device, and a strong dielectric memory using the organic composite electronic device.
  • An organic thin film transistor has, for example, a structure in which a substrate, a gate electrode, a gate insulating film, a source electrode, a drain electrode, an organic semiconductor film, and a protective film are stacked.
  • Organic thin-film transistors can be obtained by a low-cost manufacturing process under normal temperature and normal pressure, such as printing, and have good strength and compatibility with flexible substrates.
  • organic thin film transistors can be applied to image drive elements of flat panel displays such as liquid crystal display devices and organic electoluminescence (EU display devices, electrophoretic display devices, sheet displays, electronic It is expected to be applied to integrated circuit technology for electronic devices such as paper, electronic price tags and electronic tags, and biosensors.
  • EU display devices organic electoluminescence
  • electrophoretic display devices electrophoretic display devices
  • sheet displays electronic It is expected to be applied to integrated circuit technology for electronic devices such as paper, electronic price tags and electronic tags, and biosensors.
  • a high dielectric constant for example, in the organic thin film transistor disclosed in Japanese Patent Publication No. 5-508745 and US Pat. No. 5,347,144, in order to increase the drain current, Since it is better to have a larger electric capacity per unit area, a high dielectric constant, a dielectric constant of at least 5 and a high insulating polymer (such as cyanoethyl pullulan) are used for the gate insulating film.
  • This cyanoethyl pullulan has a dielectric constant of 18.5.
  • polyacrylonitrile which is a polymer having a cyano group
  • the relative dielectric constant of polyatrylonitrile is 4.5.
  • polyimide, polystyrene, polymethylmetatalylate, polybuluchloride, polybulualcohol, polyparaxylene, polyvinylidene fluoride, polybutanol, Polymers such as pullulan and norylene and their derivatives have been proposed.
  • Japanese Patent Publication No. 8-191162 it is further proposed to use a composite material mixed with a material for increasing the dielectric constant in order to obtain a more effective electric field effect.
  • a first object of the present invention is to provide an organic thin film transistor capable of suppressing leakage current in a gate insulating film, obtaining a high insulating film capacity, and operating at a low gate voltage, a method for producing the same, and the organic thin film transistor. It is to provide a display device to be used.
  • a second object of the present invention is to simplify the manufacturing process of an organic composite electronic device including an organic thin film transistor and a high dielectric capacitor.
  • a third object of the present invention is to simplify a manufacturing process of an organic composite electronic device including two or more organic thin film transistors having different performances.
  • the present inventors have studied various organic gate insulating film materials conventionally used for organic thin film transistors, and as a result, have found that there is a sensory function present in the molecular structure. As a result of further investigation, it was found that there was no functional group with an unshared electron pair and a ⁇ -electron bond in the molecular structure.
  • a low dielectric film is formed using an organic polymer compound that does not have a layer, and this low dielectric film and a ferroelectric film are laminated to form a gate insulating film.
  • an organic thin film transistor comprising a gate electrode, a gate insulating film, an organic semiconductor film, a source electrode, and a drain electrode on a substrate.
  • the gate insulating film includes a ferroelectric film, and a low dielectric film having a low dielectric constant compared to the ferroelectric film interposed between the ferroelectric film and the organic semiconductor film.
  • the low-dielectric film includes an organic thin film transistor including an organic polymer compound that does not have a functional group having an unshared electron pair and does not have 71 electronic bonds in the molecular structure.
  • a first step of forming a gate electrode on the substrate a second step of forming a ferroelectric film on the substrate including the gate electrode, and a ferroelectric film on the ferroelectric film
  • a third step of forming a low dielectric film having a low dielectric constant compared to the fourth step a fourth step of forming an organic semiconductor film on the low dielectric film, and a source electrode and a drain on the organic semiconductor film.
  • a method for producing an organic thin film transistor which comprises a step of obtaining a solution, and a step of casting the solution and then removing the solvent.
  • a display device comprising the organic thin film transistor is also provided.
  • the organic thin film transistor of the present invention is capable of suppressing leakage current in the gate insulating film, realizing stable and excellent performance, and operating at a low gate voltage.
  • the method for producing an organic thin film transistor of the present invention can produce an organic thin film transistor that has stable characteristics, has a high insulating film capacity, and can operate at a low gate voltage.
  • the organic thin film transistor of the present invention can be used as an image driving element for a flat panel display such as a liquid crystal display device, an organic EL (electrical luminance) display device, and an electrophoretic display device. It can also be applied to integrated circuit technology for electronic devices such as sheet displays, electronic paper, electronic price tags and electronic tags, and biosensors, gas sensors, and memory elements. In particular, since the organic thin film transistor of the present invention can be operated at a low voltage, it is suitable for an image driving element of an organic EL display device, for example.
  • a method for producing an organic composite electronic device is a method for producing an organic composite electronic device comprising a transistor and a capacitor on a substrate.
  • a second electrode group for the transistor is formed in a predetermined positional relationship with the first electrode group, and a second electrode group for the capacitor is formed corresponding to the first electrode group for the capacitor at least across the ferroelectric film.
  • the electrode group refers to one or more electrodes.
  • the predetermined positional relationship refers to a positional relationship in which each electrode is arranged so as to constitute a transistor.
  • the transistor ferroelectric film and the capacitor ferroelectric film are formed in the same formation process, and the transistor electrode group and the capacitor electrode group are formed in the same formation process. Therefore, it is possible to manufacture organic composite electronic devices having transistors and capacitors with less man-hours compared to the conventional technology, which are formed by different forming processes! Manufacturing cost can be reduced.
  • the insulating film (gate insulating film) of the transistor is formed by laminating a ferroelectric film and a low dielectric film, the dielectric constant of the low dielectric film should be appropriately selected.
  • the present invention it is possible to facilitate the manufacture of an organic composite electronic device including an organic thin film transistor and a high dielectric capacitor.
  • the organic composite electronic device manufactured according to the present invention can be suitably used for manufacturing, for example, a signal circuit for a wireless transmission tag.
  • an organic composite electronic device manufacturing method includes an organic composite electronic device including a first transistor and a second transistor on a substrate.
  • a second electrode group forming step of forming the second electrode group for the second transistor in a predetermined positional relationship with the first electrode group for the second transistor refers to one or more electrodes.
  • the predetermined positional relationship means a positional relationship in which each electrode is arranged so as to constitute a transistor.
  • the ferroelectric film for the first transistor and the ferroelectric film for the second transistor are formed in the same formation process, and the first transistor electrode group and the second transistor electrode group are formed. Therefore, it is possible to manufacture organic composite electronic devices with two types of transistors with a small amount and a small number compared to the conventional technology formed by different forming processes. Manufacturing cost can be reduced.
  • the first transistor is formed with a two-layer gate insulating film having a ferroelectric film and a low dielectric film, the dielectric constant of the low dielectric film can be selected appropriately.
  • An organic thin film transistor having a good characteristic with low hysteresis capable of setting a dielectric constant of an insulating film composed of a dielectric film and a low dielectric film to a desired value, being operable at a low gate voltage.
  • a gate insulating film made of a ferroelectric film is formed, an organic thin film transistor suitable for use in, for example, a ferroelectric memory can be obtained.
  • FIG. La is a diagram showing a configuration example of a top gate staggered organic thin film transistor of the first embodiment.
  • FIG. Lb is a diagram showing a configuration example of a top gate coplanar type organic thin film transistor of the first embodiment.
  • FIG. 2a is a diagram showing a configuration example of a bottom-gate staggered organic thin film transistor of the first embodiment.
  • FIG. 2b Configuration example of bottom gate 'coplanar type organic thin film transistor of the first embodiment
  • FIG. 4 is a diagram illustrating a configuration example of one pixel of the organic EL display device according to the first embodiment.
  • FIG. 6a is a diagram showing a manufacturing process (part 1) of an organic composite electronic device including a bottom-gate staggered organic thin film transistor and a capacitor according to a second embodiment.
  • FIG. 6b A diagram showing a manufacturing process (part 2) of the organic composite electronic device including the bottom gate staggered organic thin film transistor and the capacitor according to the second embodiment.
  • 6c] is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the bottom gate staggered organic thin film transistor and the capacitor according to the second embodiment.
  • 6d is a diagram showing a manufacturing process (No. 4) of the organic composite electronic device including the bottom gate staggered organic thin film transistor and the capacitor according to the second embodiment.
  • 6e is a view showing a manufacturing process (No. 5) of the organic composite electronic device including the bottom gate staggered organic thin film transistor and the capacitor according to the second embodiment.
  • 6f is a diagram showing a manufacturing process (No. 6) of the organic composite electronic device including the bottom gate staggered organic thin film transistor and the capacitor of the second embodiment.
  • FIG. 7a] is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including a bottom gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
  • FIG. 7b] is a diagram showing a manufacturing process (No. 2) of the organic composite electronic device including the bottom gate 'coplanar type organic thin film transistor and the capacitor of the second embodiment.
  • FIG. 7c] is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the bottom gate coplanar type organic thin film transistor and the capacitor according to the second embodiment.
  • FIG. 7d] is a diagram showing a manufacturing process (No. 4) of the organic composite electronic device including the bottom gate and coplanar type organic thin film transistor and capacitor of the second embodiment.
  • FIG. 7e] is a diagram showing a manufacturing process (No. 5) of an organic composite electronic device including a bottom-gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
  • FIG. 11 is a diagram showing a manufacturing process (No. 6) of an organic composite electronic device including a shita.
  • FIG. 8a] is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including a top gate stagger type organic thin film transistor and a capacitor according to a second embodiment.
  • FIG. 8b] is a diagram showing a manufacturing process (No. 2) of the organic composite electronic device including the top gate stagger type organic thin film transistor and the capacitor of the second embodiment.
  • FIG. 8c] is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the top gate staggered organic thin film transistor and the capacitor according to the second embodiment.
  • FIG. 8d] is a diagram showing a manufacturing process (No. 4) of the organic composite electronic device including the top gate staggered organic thin film transistor and the capacitor according to the second embodiment.
  • FIG. 8e] is a diagram showing a manufacturing process (No. 5) of the organic composite electronic device including the top gate stagger-type organic thin film transistor and capacitor of the second embodiment.
  • FIG. 8f] is a diagram showing a manufacturing process (No. 6) of the organic composite electronic device including the top gate stagger type organic thin film transistor and capacitor of the second embodiment.
  • FIG. 9a] is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including a top-gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
  • FIG. 9b] is a diagram showing a manufacturing process (No. 2) of an organic composite electronic device including a top gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
  • FIG. 9c] is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the top gate coplanar type organic thin film transistor and the capacitor according to the second embodiment.
  • FIG. 9d] is a diagram showing a manufacturing process (No. 4) of an organic composite electronic device including a top gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
  • FIG. 9e] is a diagram showing a manufacturing process (No. 5) of an organic composite electronic device including a top gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
  • FIG. 9f] is a diagram showing a manufacturing process (No. 6) of an organic composite electronic device including the top gate coplanar type organic thin film transistor and capacitor of the second embodiment.
  • FIG. 10 A diagram showing a configuration example of the high dielectric memory cell of the second embodiment.
  • FIG. 1 la] is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including the bottom gate stagger type organic thin film transistor of the third embodiment.
  • FIG. 1 lb is a diagram showing a manufacturing process (No. 2) of an organic composite electronic device including a bottom-gate staggered organic thin film transistor according to a third embodiment.
  • FIG. 11c is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the bottom-gate staggered organic thin film transistor of the third embodiment.
  • FIG. 1 Id is a diagram showing a manufacturing process (No. 4) of an organic composite electronic device including a bottom-gate staggered organic thin film transistor according to a third embodiment.
  • FIG. 1 is a diagram showing a manufacturing process (No. 5) of an organic composite electronic device including a bottom-gate staggered organic thin film transistor according to a third embodiment.
  • FIG. 1 If is a diagram showing a manufacturing process (No. 6) of an organic composite electronic device including a bottom-gate staggered organic thin film transistor according to a third embodiment.
  • FIG. 12a is a view showing a manufacturing process (No. 1) of an organic composite electronic device including a bottom-gate coplanar type organic thin film transistor according to a third embodiment.
  • FIG. 12 b is a diagram showing a manufacturing process (No. 2) of the organic composite electronic device including the bottom gate coplanar type organic thin film transistor of the third embodiment.
  • FIG. 12c is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the bottom-gate coplanar type organic thin film transistor of the third embodiment.
  • FIG. 12d is a diagram showing a manufacturing step (No. 4) of the organic composite electronic device including the bottom gate ′ coplanar type organic thin film transistor of the third embodiment.
  • FIG. 12e is a diagram showing a manufacturing process (No. 5) of the organic composite electronic device including the bottom gate ′ coplanar type organic thin film transistor of the third embodiment.
  • FIG. 12f is a diagram showing a manufacturing step (No. 6) of the organic composite electronic device including the bottom gate ′ coplanar type organic thin film transistor of the third embodiment.
  • FIG. 13a is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including a top-gate staggered organic thin film transistor according to a third embodiment.
  • FIG. 13b is a diagram showing a manufacturing process (No. 2) of the organic composite electronic device including the top gate stagger type organic thin film transistor of the third embodiment.
  • FIG. 13c is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the top-gate staggered organic thin film transistor of the third embodiment.
  • FIG. 13d is a diagram showing a manufacturing process (No. 4) of the organic composite electronic device including the top-gate staggered organic thin film transistor of the third embodiment.
  • FIG. 13e is a diagram showing a manufacturing process (No. 5) of an organic composite electronic device including a top-gate staggered organic thin film transistor according to a third embodiment.
  • FIG. 13f is a diagram showing a manufacturing process (No. 6) of an organic composite electronic device including the top-gate staggered organic thin film transistor of the third embodiment.
  • FIG. 14a is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including a top gate coplanar type organic thin film transistor of a third embodiment.
  • FIG. 14b is a diagram showing a manufacturing process (No. 2) of the organic composite electronic device including the top gate coplanar type organic thin film transistor of the third embodiment.
  • FIG. 14c is a view showing a manufacturing process (No. 3) of the organic composite electronic device including the top gate coplanar type organic thin film transistor of the third embodiment.
  • FIG. 14d is a diagram showing a manufacturing step (No. 4) of the organic composite electronic device including the top gate coplanar type organic thin film transistor of the third embodiment.
  • FIG. 14e is a diagram showing a manufacturing process (No. 5) of the organic composite electronic device including the top gate coplanar type organic thin film transistor of the third embodiment.
  • FIG. 14f is a diagram showing a manufacturing process (No. 6) of the organic composite electronic device including the top gate coplanar type organic thin film transistor of the third embodiment.
  • FIG. 15 is a diagram showing a configuration example of a ferroelectric memory cell according to a third embodiment.
  • FIG. 16 is a VD-ID diagram of the transistor or the first transistor in the example.
  • FIG. 17 is a VG-ID diagram of the transistor or the first transistor in the example.
  • FIG. 18 is a VG-ID diagram of the second transistor in the example.
  • the organic thin film transistor of this embodiment has an organic semiconductor film, a gate electrode, and a soot on a substrate.
  • the gate insulating film has a two-layer structure in which a low dielectric constant low dielectric film and a ferroelectric film having a higher dielectric constant than the low dielectric film are stacked.
  • An organic thin film transistor has a source electrode and a drain electrode in contact with an organic semiconductor film, and has a top gate type having a gate electrode via a gate insulating film thereon, a gate electrode, and a gate insulating film thereon It is roughly classified into a bottom gate type having a source electrode and a drain electrode connected by an organic semiconductor film through a via.
  • the organic thin film transistor to which the present invention can be applied may be a top gate type or a bottom gate type. However, damage to the organic semiconductor film due to the formation of the source electrode and the drain electrode is prevented. From the viewpoint of avoidance, the bottom gate type is preferable.
  • FIG. La is a diagram showing a configuration of a top gate stagger type organic thin film transistor.
  • the organic thin film transistor shown in FIG. La has an undercoat layer 12 on a substrate 11.
  • the undercoat layer 12 contains a polymer or a compound selected from inorganic oxides and inorganic nitrides.
  • An organic semiconductor film 16, a drain electrode 14, and a source electrode 15 are provided in contact with the undercoat layer 12.
  • a gate electrode 18 is provided on the organic semiconductor film 16 via a gate insulating film 17.
  • the gate insulating film 17 is formed by laminating a low dielectric film 17a and a ferroelectric film 17b.
  • the low dielectric film 17a is disposed between the organic semiconductor film 16 and the ferroelectric film 17b.
  • a protective film (sealing film) 23 is provided as the outermost layer.
  • Figure lb shows the configuration of the top gate coplanar type with the drain electrode and the stacking order of the source electrode and the organic semiconductor film changed.
  • FIG. 2a is a diagram showing a configuration of an organic thin film transistor of a bottom gate stagger type (Bottom Gate Stagger type).
  • the organic thin film transistor shown in FIG. 2 a has an undercoat layer 12 on a substrate 11.
  • the undercoat layer 12 contains a polymer or a compound selected from inorganic oxides and inorganic nitrides.
  • An organic semiconductor film 16 is provided in contact with the undercoat layer 12 via a gate electrode 18 and a gate insulating film 17.
  • the gate insulating film 17 is formed by laminating a low dielectric film 17a and a ferroelectric film 17b.
  • the low dielectric film 17a is interposed between the organic semiconductor film 16 and the ferroelectric film 17b.
  • Further organic semiconductor film A drain electrode 14 and a source electrode 15 are provided in contact with 16.
  • Figure 2b shows the configuration of the bottom gate coplanar type with the drain electrode and the stacking order of the source electrode and the organic semiconductor film changed.
  • Organic semiconductor materials include ⁇ -conjugated materials.
  • ⁇ -conjugated materials include polypyrrole, poly ( ⁇ substituted pyrrole), poly (3-substituted pyrrole), poly (3,4-disubstituted pyrrole), and the like; polythiophene, poly (3-substituted thiophene) Polythiophenes such as poly (3,4-disubstituted thiophene) and polybenzothiophene; Polyisothianaphthenes such as polyisothianaphthene; Polyethylene vinylenes such as polyphenylene vinylene; Poly ( ⁇ vinylene) such as poly (.rho. phenylene vinylene) s; Poria diphosphate, poly (Nyu- substituted Ayurin), poly (3 - substituent Ayurin), poly (2, 3 - substituted Ayurin) Polya diphosphate,
  • Poly rubazoles such as Nole and poly ( ⁇ -substituted carbazole); Polyselenophenes such as polyselenophene; Polyfurans such as polyfuran and polybenzofuran; Poly ( ⁇ -phenol) such as poly ( ⁇ -phenol) Polyindoles such as polypyridazine; polypyridazines such as polypyridazine; naphthacene, pentacene, hexacene, heptacene, dibenzopentacene, tetrabenzopentacene, pyrene, dibenzopyrene, taricene, perylene, coronene, terylene, Derivatives (triphenodioxazines) in which a part of carbon of polyacene is substituted with an atom such as N, S, or O, or a functional group such as carbonyl group.
  • Triphenodioxazines in which a part of carbon
  • these polymers have the same repeating unit, for example, thiophene hexamer.
  • ⁇ -seccithiophene ⁇ , ⁇ -dihexinole ⁇ -seccithiophene, ⁇ , ⁇ -dihexoxyl ⁇ -kinchethiophene, ⁇ , ⁇ -bis (3-butoxypropyl) ⁇ -sexuality
  • examples include oligomers such as ophene and styrylbenzene derivatives.
  • metal phthalocyanines such as copper phthalocyanine and fluorine-substituted copper phthalocyanine described in Japanese Patent Application Laid-Open No. 11-251601; naphthalene 1, 4, 5, 8-tetracarboxylic acid diimide, N, N, Bis (4 trifluoromethylbenzyl) naphthalene 1, 4, 5, 8— Tetracarboxylic acid diimide, N, N, 1 bis (1H, 1H-perfluorooctyl) naphthalene 1, 4, 5, 8— Tetracarboxylic acid diimide, N, N, monobis (1H, 1H-perfluorobutyl) naphthalene 1, 4, 5, 8-tetracarboxylic acid diimide and N, N'-dioctylnaphthalene 1, 4, 5, 8 tetracarboxylic acid Naphthalene tetracarboxylic acid diimides such as diimide, na
  • thiophene, chelenylene vinylene, phenylene vinylene, ⁇ -phenylene, and at least one of these substituents are repeating units, and the number of repeating units ⁇ is 4 to; an oligomer having 10 to 10 and a polymer having ⁇ of 20 or more; a condensed polycyclic aromatic compound such as pentacene; fullerenes; a condensed ring tetracarboxylic diimide; and a group consisting of metal phthalocyanines At least one selected from is preferred.
  • organic semiconductor materials include tetrathiafunolevalene (TTF) -tetracyanoquinodimethane (TCNQ) complex, bisethylenetetrathiafulvalene (BEDTTTF) -perchloric acid complex, BEDTTTF iodine complex, TCNQ iodine complex
  • TTF tetrathiafunolevalene
  • BEDTTTF bisethylenetetrathiafulvalene
  • TCNQ iodine complex TCNQ iodine complex
  • Organic molecular complex such as Further examples include ⁇ -conjugated polymers such as polysilane and polygermane, and organic / inorganic hybrid materials described in Japanese Unexamined Patent Publication No. 2000-260999.
  • a material having a functional group such as acrylic acid, acetamido, dimethylamino group, cyano group, carboxyl group, nitro group; benzoquinone derivative, tetracyanethylene, tetracyanoquinodimethane and derivatives thereof Materials that accept electrons, such as amino groups, triphenyl groups, alkyl groups, hydroxyl groups, Materials having functional groups such as alkoxy groups and phenyl groups; substituted amines such as phenylenediamine, substituted amines, anthracene, benzoanthracene, substituted benzoanthracenes, pyrene, substituted pyrene, force rubazole and derivatives thereof, tetrathiafulvalene and its A material which becomes a donor which is an electron donor such as a derivative may be contained.
  • a functional group such as acrylic acid, acetamido, dimethylamino group, cyano group, carboxyl group, nitro group
  • Organic semiconductor film formation (formation) methods include vacuum deposition, molecular beam epitaxy, ion cluster beam, low energy ion beam, ion plating, CVD, sputtering, plasma Examples include a polymerization method, an electrolytic polymerization method, a chemical polymerization method, a spray coating method, a spin coating method, a blade coating method, a dip coating method, a casting method, a Rhino recording method, a bar coating method, a die coating method, and an LB method.
  • the thickness of the organic semiconductor film varies depending on the organic semiconductor material to be used, but is usually 1 ⁇ m or less, preferably from a monolayer thickness to 400 nm.
  • Each electrode (gate electrode, source electrode and drain electrode) constituting the organic thin film transistor is formed of a conductive material.
  • conductive materials include platinum, gold, silver, nickel, chromium, copper, iron, tin, antimony lead, tantalum, indium, palladium, tellurium, rhenium, iridium, aluminum, ruthenium, germanium, and molybdenum.
  • Tungsten tin oxide / antimony, indium tin oxide (ITO), fluorine-doped zinc oxide, zinc, carbon, graphite, glassy carbon, silver paste and carbon paste, lithium, beryllium, magnesium, potassium, calcium, scandium, Titanium, manganese, zirconium oxide, gallium, niobium, sodium, sodium-potassium alloy, magnesium / copper mixture, magnesium / silver mixture, magnesium / aluminum mixture, magnesium / indium mixture, aluminum / aluminum oxide Compound, and lithium / aluminum mixed compounds and the like.
  • ITO indium tin oxide
  • conductive polymers whose conductivity has been improved by doping or the like, for example, conductive polyaniline, conductive polypyrrole, or conductive polythiophene (polyethylene dioxythiophene and polystyrene sulfonic acid complex, etc.) can be mentioned.
  • the material for forming the source electrode and the drain electrode is preferably a p-type semiconductor having a low electrical resistance at the contact surface with the organic semiconductor film among the materials listed above. Platinum, gold, silver, ITO, conductive polymer and carbon are preferred.
  • the gate electrode, the source electrode, and the drain electrode are formed using a fluid electrode material such as a solution, paste, ink, or dispersion liquid containing the above-described conductive material. It is preferable to use a conductive polymer or a fluid electrode material containing fine metal particles containing platinum, gold, silver and copper!
  • the fluid electrode material containing fine metal particles for example, a known conductive paste may be used.
  • the average particle size is 1 to 50 nm, preferably 1 to;
  • a material in which fine particles are dispersed in water or a dispersion medium that is an arbitrary organic solvent using a dispersion stabilizer as required is used.
  • the average particle size can be measured by a photon correlation method.
  • a metal phase in a liquid phase such as a physical production method such as a gas evaporation method, a sputtering method or a metal vapor synthesis method, a colloid method or a coprecipitation method is used.
  • a chemical production method in which metal fine particles are produced by reducing ON. After forming an electrode using these metal fine particle dispersions and drying the solvent, the metal fine particles are formed by heating in the range of 100 to 300 ° C, preferably 150 to 200 ° C as necessary. An electrode pattern having a desired shape is formed by heat fusion.
  • a conductive thin film is formed by sputtering or vapor deposition using the conductive material as a raw material, and then a pattern is formed with a photoresist, and then an unnecessary thin film is removed by etching to form an electrode pattern.
  • Photolithographic method to form an electrode metal mask method on which a metal mask is placed on a substrate, and sputtering or vapor deposition is performed as it is to form an electrode pattern; a photoresist film is formed on a metal foil such as aluminum or copper by thermal transfer or ink jet
  • a method of forming an electrode pattern by removing an unnecessary thin film by etching after forming a pattern There are known methods such as a method of forming an electrode pattern by removing an unnecessary thin film by etching after forming a pattern.
  • a solution or dispersion of a conductive polymer, a dispersion containing metal fine particles, or the like may be directly patterned by an ink jet method, or may be formed from a coating film by lithograph or laser abrasion. You may make it.
  • a method of patterning conductive inks or conductive pastes containing conductive polymers and metal fine particles by printing methods such as relief printing, intaglio printing, lithographic printing, and screen printing.
  • the thickness of the electrode is not particularly limited, but is usually 20 to 500 nm, preferably 50 to 200.
  • the gate insulating film is a film having a two-layer structure in which a low dielectric film having a relatively low dielectric constant and a ferroelectric film (high dielectric film) having a relatively high dielectric constant are stacked.
  • the power to explain the gate insulating film having a two-layer structure may be a film having a multilayer structure of two or more layers within a range not impairing the object of the present invention.
  • the low dielectric film is formed in contact with the organic semiconductor film, and the ferroelectric film is formed in contact with the gate electrode.
  • the relative dielectric constant of the low dielectric film is normally set to a value of 4 or less, and is preferably set to a value of 3.5 or less. Force S is preferable, and is more preferably set to a value of 3 or less. .
  • the lower limit of the dielectric constant is usually around 2.
  • the film thickness of the low dielectric film is preferably set to 5 nm to 500 nm, more preferably 10 nm to 300 nm.
  • the relative dielectric constant of the ferroelectric film is normally set to a value of 5 or more, and is preferably set to a value of 7 or more, and is preferably set to a value of 10 or more.
  • the upper limit of the relative dielectric constant is usually about 50.
  • the film thickness of the ferroelectric film is preferably set to 5 nm to 500 nm, more preferably 10 nm to 300 nm.
  • the effective dielectric constant of the entire gate insulating film can be adjusted by appropriately setting the relative dielectric constant and film thickness of the low dielectric film and the relative dielectric constant and film thickness of the ferroelectric film.
  • the total thickness of the gate insulating film formed by laminating the low dielectric film and the ferroelectric film may be any thickness as long as the insulating property is maintained. 10 to 500 nm, more preferably 10 to 300 nm. It is desirable to make it as thin as possible as the size of organic thin-film transistor elements becomes smaller.
  • the low dielectric film constituting the gate insulating film is a film containing an organic polymer compound that does not have a functional group having an unshared electron pair and does not have a negative electron bond in the molecular structure.
  • the “functional group” is not involved in the formation of the skeleton structure of the main chain of the organic polymer compound.
  • the unshared electron pair is an electron that is paired with two of the outermost electrons of the atom without involving a bond with another atom. It is also called a lone pair or a non-bonded pair.
  • the functional group having an unshared electron pair is a group bonded to the main chain and branched from the main chain, and does not include those based on the main chain itself.
  • an imino group in the case where the main chain itself exists in the main chain itself such as polyamine has an unshared electron pair. Not included in the functional group.
  • a nitrile group having a nitrile group bonded to the main chain such as polyacrylonitrile or a fluorine group having a fluorine group bonded to the main chain such as polytetrafluoroethylene has an unshared electron pair. Included in functional group.
  • a ⁇ -electron bond is a bond formed by electrons belonging to a ⁇ orbit.
  • a ⁇ orbital is a type of orbit that accommodates electrons in a molecule, and orbitals that are distributed in a direction perpendicular to the axis connecting the nuclei of one bond (bonding axis) are above and below the molecular plane. It is an electron orbit created by overlapping in the horizontal direction.
  • bonds having a ⁇ -electron bond include carbon-carbon double bonds and triple bonds, nitrogen-carbon triple bonds, carbon-oxygen double bonds, and benzene and naphthalene double bonds. It is done.
  • the organic polymer compound contained in the low dielectric film is a compound that does not have a functional group having an unshared electron pair and does not have a negative electron bond in the molecular structure as described above. Any of these compounds can achieve the desired effects of the present invention.
  • the organic high molecular compound used in this embodiment has a small relative dielectric constant and is usually 3 or less. In this embodiment, the relative dielectric constant can be measured by a capacitance method using an LCR meter (manufactured by Agilent Technologies, part number 4284 ⁇ ).
  • organic polymer compounds examples include polyolefins such as polyethylene, polypropylene, and polybutene; alicyclic polyolefin polymers; polyamines; polyethers; Of these, alicyclic polyolefin polymers are preferred from the viewpoint that the frequency dependence of the dielectric constant is small.
  • the alicyclic olefin polymer is a polymer having a cycloalkane structure in the main chain and / or side chain. From the viewpoint of mechanical strength and heat resistance, a polymer containing a cycloalkane structure in the main chain is preferred. Cycloalkane structures can be monocyclic or polycyclic (condensed). Multi-rings, bridge rings, etc.). The number of carbon atoms constituting one unit of the cycloalkane structure is not particularly limited, but is usually 4 to 30, preferably 5 to 20, more preferably 5 to 15; Various characteristics such as mechanical strength, heat resistance, and moldability are highly known and suitable. In addition, the alicyclic olefin polymer used in the present embodiment is usually a thermoplastic resin.
  • the repeating unit having a cycloalkane structure is usually 30 to 100% by weight in all the repeating units in the main chain of the alicyclic olefin polymer, preferably 50 to 50%. 100 weight. / 0 , more preferably from 70 to 100% by weight. If the ratio of the repeating unit having a cycloalkane structure is within these ranges, the heat resistance is excellent.
  • the alicyclic olefin polymer is usually obtained by addition polymerization or ring-opening polymerization of olefin having a ring structure, and hydrogenating the unsaturated bond portion and the aromatic ring portion as necessary. .
  • Olefins having a ring structure used to obtain an alicyclic olefin polymer include norbornene, dicyclopentagen, tetracyclododecene, ethyltetracyclododecene, and ethylidenetetracyclodone. Decene, tetracyclo [7 ⁇ 4.0.110, 13.
  • Polymerization of olefin having a ring structure can be carried out according to a known method.
  • the polymerization temperature, pressure and the like are not particularly limited, but the polymerization is usually carried out at a polymerization temperature of 50 ° C to 100 ° C and a polymerization pressure of 0 to 5 MPa.
  • the hydrogenation reaction is carried out by blowing hydrogen in the presence of a known hydrogenation catalyst.
  • alicyclic olefin polymer examples include a hydride of a ring-opening polymer of a norbornene monomer, an addition polymer of a norbornene monomer and a hydride thereof, and a norbornene monomer.
  • hydrides of ring-opening polymers of norbornene monomers are preferred, addition polymers of norbornene monomers, addition weights of norbornene monomers and bur compounds (such as ethylene and a 1-year-old refin).
  • aromatic ring hydrides of polymers and aromatic olefin polymers particularly hydrides of ring-opening polymers of norbornene monomers.
  • the above alicyclic olefin polymers can be used singly or in combination of two or more.
  • the norbornene monomer is a monomer having a norbornene structure as shown in Chemical Formula 1.
  • the norbornene monomer is ring-opening polymerized, a polymer having a repeating unit as shown in Chemical Formula 2 is obtained, and when this is hydrogenated, a polymer having a repeating unit as shown in Chemical Formula 3 is obtained.
  • Rl and R2 in Chemical Formula 3 represent a substituent having no unshared electron pair and having no ⁇ -electron bond, and R1 and R2 may be bonded to form a ring.
  • R1 and R2 in Chemical Formula 1 and Chemical Formula 2 are subjected to various production processes, and the finally obtained alicyclic olefin polymer does not have a functional group having an unshared electron pair and has a ⁇ -electron bond. Is not particularly limited, but preferably represents a substituent having no unshared electron pair and no ⁇ -electron bond, and R1 and R2 may be bonded to form a ring. Good.
  • the alicyclic olefin polymer used in the present embodiment is not particularly limited by the molecular weight.
  • the molecular weight of an alicyclic olefin polymer is a polystyrene-equivalent weight average molecular weight (Mw) measured by gel permeation chromatography (GPC) using cyclohexane as a solvent, and is usually 1,000— 1, 000,000, preferably ⁇ is in the range of 5,000-500,000, more preferably in the range of 10,000-250,000.
  • the molecular weight distribution of the alicyclic olefin polymer is the ratio (Mw / Mn) of the weight average molecular weight (Mw) and the number average molecular weight (Mn) measured by GPC using cyclohexane as a solvent. Usually, it is 5 or less, preferably 4 or less, more preferably 3 or less.
  • the glass transition temperature of the alicyclic olefin polymer is preferably 70 ° C or higher, more preferably 120 ° C or higher, and most preferably 140 ° C or higher. The glass transition temperature can be measured with a differential scanning calorimeter.
  • the low dielectric film has no functional group having an unshared electron pair and has 71 electronic bonds in the molecular structure as long as expression of the desired effect of the present invention is not inhibited.
  • organic polymer compounds other known organic polymer compounds are included!
  • the content of the organic polymer compound in the gate insulating film that does not have a functional group having an unshared electron pair and has 71 electronic bonds in the molecular structure is preferably 70 to 100% by weight
  • colorants such as pigments and dyes, optical brighteners, dispersants, heat stabilizers, light stabilizers, UV absorbers, antistatic agents, antioxidants, lubricants, solvents, and other compounding agents are used as appropriate. You may mix
  • Low dielectric film formation (formation) methods include vacuum deposition, molecular beam epitaxy, ion cluster beam, low energy ion beam, ion plating, CVD, sputtering, Examples include plasma polymerization method, electrolytic polymerization method, chemical polymerization method, spray coating method, spin coating method, blade coating method, dip coating method, casting method, Rhino recording method, bar coating method, die coating method and LB method. .
  • the wet method is preferred.
  • the organic polymer compound constituting the low dielectric film and the compounding agent are dissolved in a solvent as desired to obtain a solution, and after casting the solution, the solvent is removed to form a film. Is the method.
  • the solvent to be used may be appropriately selected from known solvents according to the organic polymer compound to be used.
  • the wet method include spin coating, blade coating, dip coating, roll coating, bar coating, die coating, screen printing, and ink jet printing. It is also possible to apply a printing method called soft lithography such as microcontact printing and micromolding. Of these wet methods, the spin coating method is particularly preferable.
  • the material of the ferroelectric film constituting the gate insulating film is not particularly limited. Usually, the insulating organic polymer alone, or the insulating organic polymer and the inorganic metal oxide or high dielectric insulator nanoparticles are used. Can be used. The dielectric constant can be adjusted by selecting an insulating organic polymer and adjusting the mass ratio between the insulating organic polymer and the nanoparticles. Using such a material, a ferroelectric film can be formed according to the same formation method as that of the low dielectric film described above. Also in the formation of the ferroelectric film, among the above-described forming methods, the spin coating method is particularly preferable, which is preferable to the wet method.
  • Examples of the insulating organic polymer include polyester, polycarbonate, polyvinyl alcohol, polyvinyl butyral, polyacetal, polyarylate, polyamide, polyamidoimide, polyetherimide, polyphenylene ether, polyphenylene sulfide, Polyethersulfone, polyetherketone, polyphthalanolamide, polyethernitrile, polyethersulfone, polybenzimidazole, polycarpositimide, polysiloxane, polymethylmethacrylate, polymethacrylamide, nitrile rubber, acrylic rubber , Polyethylene tetrafluoride, epoxy resin, phenol resin, melamine resin, urea resin, polybutene, polypentene, ethylene-propylene copolymer, ethylene-butene copolymer Polymer, polybutadiene, polyisoprene, ethylene propylene copolymer, butyl rubber, polymethylpentene, polystyrene, styren
  • the inorganic metal oxide nanoparticles are not particularly limited, and examples thereof include Ta 2 O 3, Y 2 O 3,
  • Nanoparticles such as TiO 2, CeO and ZrO can be mentioned. High dielectric insulator nanoparticles and
  • Ba Sr TiO (where d is 0 and d satisfies 1); d 1 d 3
  • Nanoparticles such as BZT), BaTiO 3, SrTiO 2 and Bi Ti 2 O 3
  • Ba Sr TiO is called Barium Strontium Titanate d 1 d 3
  • the weight ratio of BaTiO and SrTiO is 1: 9 to 9: 1
  • nanoparticles may be used alone or in combination of two or more. It can be used together.
  • the nanoparticles those having a dielectric constant of 5 or more are preferable. From the viewpoint of achieving this, normally, nanoparticles of a high dielectric insulator are preferably used.
  • the average particle size of the nanoparticles is usually 50 nm or less, preferably !!-50 nm, more preferably !!-30 nm.
  • the dielectric constant is measured according to JIS K 6911, and the average particle size is measured by the dynamic light scattering method.
  • the material of the ferroelectric film at least one selected from the group consisting of a titanium compound, a zirconium compound, a hafnium compound, and an aluminum compound, instead of the nanoparticle, instead of the insulating organic polymer as described above.
  • a mixture of these organometallic compounds may also be used. Also in this case, it is preferable to use an organometallic compound having a relative dielectric constant of 5 or more.
  • the organic thin film transistor of this embodiment may have a protective film (for example, the protective film 23 in FIGS. La, lb, 2a, and 2b) as the outermost layer.
  • the protective film is formed by, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film formed by a CVD method or a sputtering method; a polyparaxylene film formed by a thermal CVD method; or a wet method as described above
  • Preferred are a polyimide film, an alicyclic olefin polymer film, an ultraviolet curable epoxy resin film, an acrylic resin film, and the like.
  • the thickness of the protective film is usually preferably from lOOnm to ⁇ .
  • the substrate 11 is used to support the thin film organic thin film transistor.
  • the substrate is not particularly limited, and any material may be used.
  • polycarbonate, polyimide, polyethylene terephthalate (PET), and flexible plastic substrates such as alicyclic olefin polymers are used as substrates, such as glass, quartz, soda glass, and inorganic alkali. Glass substrates such as glass and silicon wafers can also be used.
  • the substrate and / or the protective film is made of the above-described alicyclic polyolefin polymer. Since the alicyclic olefin polymer has low moisture permeability and gas permeability! /, If the substrate and / or the protective film is made of the above alicyclic olefin polymer, the organic semiconductor film is not deteriorated. High effect to prevent Yes.
  • an undercoat layer 12 containing a compound selected from a polymer or an inorganic oxide and an inorganic nitride is provided.
  • Examples of the inorganic oxide contained in the undercoat layer include silicon oxide, aluminum oxide, and tantalum oxide.
  • Examples of the inorganic nitride include silicon nitride and aluminum nitride. Of these, preferred are silicon oxide and nitride nitride.
  • Polymers used for the undercoat layer containing the polymer include polyester resin, polycarbonate resin, cellulose resin, acrylic resin, polyurethane resin, polyethylene resin, polypropylene resin, polystyrene resin, phenoxy resin, norbornene resin, epoxy resin.
  • the undercoat layer is not particularly limited by the formation method.
  • the method for forming the undercoat layer include vacuum deposition, molecular beam epitaxy, ion cluster beam, low energy ion beam, ion plating, CVD, sputtering, and atmospheric pressure plasma.
  • the display device of this embodiment includes the organic thin film transistor.
  • This table In order to describe the display device more specifically, an organic EL display device will be described as an example.
  • This organic EL display device has at least one organic EL element with each pixel force formed in a matrix arrangement on a substrate, and at least two organic thin film transistors for driving the organic EL element. is there. At least one of the organic thin film transistors is the aforementioned organic thin film transistor.
  • the organic EL element is not particularly limited.
  • a structure in which a hole transport layer and a light emitting material layer are formed between a hole injection electrode serving as an anode and an electron injection electrode serving as a cathode SH--
  • a structure), a structure in which a light emitting material layer and an electron transport layer are formed between a hole injection electrode and an electron injection electrode (SH-B structure), or a hole injection electrode and an electron injection electrode a structure in which a hole transport layer, a light emitting material layer, and an electron transport layer are formed (DH structure) is included.
  • the organic EL element has a light emitting material layer and a hole (or electron) transport layer formed by the holes injected from the hole injection electrode (anode) and the electrons injected from the electron injection electrode (cathode). It operates on the principle that light is emitted by recombination within the interface and the light emitting material layer.
  • FIG. 3 shows a configuration example of a typical organic EL element.
  • the organic EL element shown in FIG. 3 includes a transparent substrate 1, a lower electrode layer (anode) 54, a light emitting material layer 62, and an upper electrode layer (cathode) 55.
  • a protective film 23 is provided as the outermost layer.
  • the transparent substrate 11 ′ has a visible light transmittance of 400 to 700 nm of 50% or more, is smooth, and does not change its characteristics when forming each layer of electrodes and organic EL elements! /, I prefer to be a thing!
  • the transparent substrate 11 ' can be formed of a material selected from the group consisting of plastic, glass, quartz, silicon, and ceramic.
  • a flexible and lightweight organic EL display can be obtained.
  • the plastic is preferably selected from the group consisting of polycarbonate resin, polyethersulfone resin, polyethylene terephthalate resin, polyimide resin, polymethyl methacrylate resin, and alicyclic olefin polymer.
  • the average thickness of the substrate is usually 30 111 to 3111111, preferably 50 to 300 mm 111.
  • Examples of the material constituting the lower electrode layer 54 include materials for emitting light from the lower electrode layer. Specifically, a conductive metal oxide, a translucent metal, or a laminate thereof is used. Can be mentioned. Specifically, indium oxide, zinc oxide, tin oxide, and composites thereof Conductive glass (NESA, etc.) made of indium oxide (tin) (ITO), indium oxide, zinc, etc., gold, platinum, silver, copper, etc. are used. Among them, ITO, indium oxide (zinc oxide, tin oxide) are used. preferable. As the lower electrode layer, an organic transparent conductive film such as polyaniline or a derivative thereof or polythiophene may be used.
  • the average thickness of the lower electrode layer can be selected as appropriate in consideration of light transmittance and electrical conductivity. Usually, lOnm to lO ⁇ m, preferably 100 to 500 nm. It is convenient that the lower electrode layer is transparent or translucent because the emission efficiency of light emission is good. Examples of the method for producing the lower electrode layer include a vacuum deposition method, a sputtering method, and a laminating method in which a metal thin film is thermocompression bonded.
  • the material constituting the light emitting material layer 62 a known material can be used as a light emitting material in the organic EL element without particular limitation.
  • Specific examples of such light-emitting materials include fluorescent brighteners such as benzothiazole, benzimidazole, and benzoxazole, metal chelated oxinoid compounds, styrylbenzene compounds, distyrylpyrazine derivatives, and aromatic dimethylidine. Compound etc. are mentioned.
  • Two or more kinds of light emitting materials may be mixed and used in the light emitting material layer. Two or more light emitting material layers may be laminated. Examples of a method for manufacturing the light emitting material layer include a vacuum deposition method and a casting method.
  • the average thickness of the light-emitting material layer varies depending on the material used, and may be selected so that the drive voltage and the light emission efficiency are moderate values, but is usually 11 111 to 1 111, preferably 2 nm. ⁇ 500nm.
  • the material constituting the upper electrode layer 55 is preferably a material having a small work function! /, Which reflects light emitted from the light emitting material layer toward the upper electrode layer and is directed toward the lower electrode layer. Therefore, a mirror body is more preferable.
  • the alloy include magnesium silver alloy, magnesium indium alloy, magnesium aluminum alloy, indium silver alloy, lithium aluminum alloy, lithium magnesium alloy, lithium indium alloy, and calcium aluminum alloy.
  • the upper electrode layer may have a laminated structure of two or more layers. Examples of the method for producing the upper electrode layer include a vacuum deposition method, a sputtering method, an ion plating method, and a plating method.
  • the average thickness of the upper electrode layer can be appropriately selected in consideration of electric conductivity and durability, but is usually 10 nm to 10111, preferably 100 to 500 nm.
  • the organic EL element includes a transparent substrate 11 ', a lower electrode layer 54, a light emitting material layer 62, an upper electrode layer.
  • another layer may be provided.
  • the other layer include a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • the hole injection layer is a layer provided adjacent to the anode, and is a layer having a function of improving the hole injection efficiency from the anode.
  • the average thickness of the hole injection layer is usually 1 nm to 100 nm, preferably 2 nm to 50 nm.
  • the hole transport layer refers to a layer having a function of transporting holes.
  • the thickness of the hole transport layer differs depending on the material used, and it may be selected so that the drive voltage and luminous efficiency are appropriate. If it is too thick, the drive voltage of the element increases, which is not preferable. Therefore, the average thickness of the hole transport layer is usually 11 111 to 1111, preferably 2 nm to 500 nm. Examples of materials used for the hole injection layer and the hole transport layer include those known as hole transport compounds in organic EL devices.
  • the electron transport layer is a layer having a function of transporting electrons.
  • the thickness of the electron transport layer differs depending on the material used and may be selected so that the drive voltage and light emission efficiency are appropriate. However, the thickness should be at least sufficient to prevent pinholes. If it is too thick, the driving voltage of the organic EL element increases, which is not preferable. Therefore, the average thickness of the electron transport layer is usually 11 111 to 1111, preferably 2 nm to 500 nm.
  • the electron injection layer is a layer provided adjacent to the cathode and has a function of improving the electron injection efficiency from the cathode and has an effect of lowering the driving voltage of the element. The average thickness of the electron injection layer is usually In m ⁇ ;! OOnm, preferably 2 nm ⁇ 50 nm.
  • Examples of the material include those known as electron transfer compounds in organic EL devices. Examples of other methods for producing the layers include spin coating, casting, and vacuum deposition.
  • FIG. 4 is a circuit configuration example for one pixel of the organic EL display device of the present embodiment.
  • a configuration for one pixel of an organic EL display device usually, at least two organic thin film transistors for driving the EL element are required for at least one organic EL element, that is, a driving transistor and a writing transistor.
  • a driving transistor and a writing transistor In the configuration example in Fig. 4, only the drive transistor is shown, and the write transistor is omitted. At least one of the drive transistor and the write transistor is constituted by the organic thin film transistor of this embodiment.
  • the anode 54 of the organic EL element 6 and the drain electrode 14 of the organic thin film transistor 5 are connected. Then, for example, the organic thin film transistor 2 (write transistor) is turned on by the voltage applied in sequence to the scan electrode 1 connected to the horizontal drive circuit, as compared with an active matrix circuit as shown in FIG. Thus, the charge amount corresponding to the display signal from the data electrode 3 connected to the vertical drive circuit is accumulated in the capacitor 4.
  • the drive transistor 5 operates according to the amount of charge accumulated in the capacitor 4, current is supplied to the organic EL element 6, and the organic EL element is turned on. This lighting state is maintained until the voltage is applied to the scan electrode 1.
  • FIGS. 6a to 6f are diagrams showing a manufacturing process of an organic composite electronic device including a bottom gate stagger type transistor and a capacitor.
  • a first electrode group forming process is performed in which one of the transistor gate electrode Ga and the capacitor counter electrode CE1 is formed on the substrate 11 in the same process (FIG. 6a).
  • an undercoat layer (not shown) may be formed on the substrate 11, and these electrodes Ga and CE1 may be formed on the undercoat layer.
  • an insulating film forming step is performed in which an insulating film 17 is formed on the substrate 11 including these electrodes Ga and CEl (on the underlayer when the undercoat layer is formed) (FIG. 6b).
  • the insulating film forming step includes a ferroelectric film forming step for forming the ferroelectric film 17b, and a low dielectric film having a low dielectric constant on the ferroelectric film 17b as compared with the ferroelectric film 17b.
  • a low dielectric film forming step of forming 17a is included.
  • an organic semiconductor film forming step of forming the organic semiconductor film 16 on the low dielectric film 17a is performed (FIG. 6c).
  • a film removal step is performed to remove portions of the low dielectric film 17a and the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 (including the vicinity thereof! /).
  • a mask formation process (FIG. 6d) for forming or placing a mask MS on the organic semiconductor film 16, an etching process for removing a portion corresponding to the capacitor counter electrode CE1 by etching or the like, And a mask removing step for removing the mask MS.
  • removal portions are formed in portions of the low dielectric film 17a and the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 (FIG. 6e).
  • the transistor source electrode So is configured so that the transistor is configured in a predetermined positional relationship with the transistor gate electrode Ga across the ferroelectric film 17b, the low dielectric film 17a, and the organic semiconductor film 16.
  • a protective film is formed by forming a protective film.
  • an organic composite electronic device including an organic thin film transistor Tr having the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and a high dielectric capacitor Ca having the ferroelectric film 17b as the insulating film is manufactured. Is done.
  • the low dielectric film 17a and the organic semiconductor film 16 are formed.
  • the force S that removes the capacitor forming part S the low dielectric film 17a is formed except the capacitor forming part in the low dielectric film forming process, and then the capacitor is formed in the organic semiconductor film forming process.
  • the organic semiconductor film 16 may be formed except for the portion to be formed.
  • the film removal step only the organic semiconductor film 16 is removed without removing the low dielectric film 17a. You may make it leave.
  • the organic thin film transistor Tr having the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and the high dielectric capacitor Ca having the ferroelectric film 17b and the low dielectric film 17a as the insulating film 17 are formed.
  • An organic composite electronic device is provided.
  • the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 may be removed by removing only a portion of the low dielectric film 17a in the thickness direction.
  • FIG. 7a to FIG. 7f are diagrams illustrating a manufacturing process of an organic composite electronic device including a bottom gate coplanar type transistor and a capacitor.
  • a first electrode group forming process is performed in which one of the transistor gate electrode Ga and the capacitor counter electrode CE1 is formed on the substrate 11 in the same process (FIG. 7a).
  • An undercoat layer (not shown) may be formed on the substrate 11, and these electrodes Ga and CE1 may be formed on the undercoat layer.
  • an insulating film forming step is performed in which an insulating film 17 is formed on the substrate 11 including these electrodes Ga and CE1 (on the undercoat layer when the undercoat layer is formed) (FIG. 7b).
  • the insulating film forming process includes a ferroelectric film forming process for forming the ferroelectric film 17b, and a low dielectric film 17a having a low dielectric constant on the ferroelectric film 17b as compared with the dielectric film 17b. Forming a low dielectric film.
  • a low dielectric film removal step is performed to remove a portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 (including the vicinity thereof! /).
  • This low dielectric film removal process includes a mask formation process (FIG. 7b) in which a mask MS1 is formed or placed on the low dielectric film 17a, and an etching process that removes a portion corresponding to the capacitor counter electrode CE1 by etching or the like. And a mask removing step for removing the mask MS1. As a result, a removal portion is formed in the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 (FIG. 7).
  • the transistor source electrode So and the drain electrode Dr are formed so as to form a transistor in a predetermined positional relationship with the transistor gate electrode Ga across the ferroelectric film 17b and the low dielectric film 17a.
  • a second electrode group forming step of forming a capacitor counter electrode CE2 corresponding to the capacitor counter electrode CE1 so as to constitute a capacitor with the ferroelectric film 17b interposed therebetween, and the organic semiconductor film 16 is formed thereon The organic semiconductor film formation process to be formed is performed (Fig. 7 d) 0
  • an organic semiconductor film removal step is performed to remove a portion of the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 (which may include the vicinity thereof).
  • This film removing step includes a mask forming step (FIG. 7e) for forming or placing a mask MS2 on the organic semiconductor film 16, an etching step for removing a portion corresponding to the capacitor counter electrode CE1 by etching or the like, And a mask removing process for removing the mask MS2.
  • a removal portion is formed in the portion of the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 (FIG. 7f).
  • a protective film formation process is performed and a protective film is formed.
  • an organic composite electronic device including an organic thin film transistor Tr having the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and a high dielectric capacitor Ca having the ferroelectric film 17b as the insulating film is obtained. Manufactured.
  • the portion of the low dielectric film 17a in which the capacitor is formed is removed in the low dielectric film removal process.
  • the low dielectric film 17a may be formed except for the part where the capacitor is formed in the low dielectric film forming step.
  • the portion of the organic semiconductor film 16 in which the capacitor is formed is removed in the organic semiconductor film removing process, but the capacitor is removed in the organic semiconductor film forming process.
  • the organic semiconductor film 16 may be formed except for the portion to be formed.
  • the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 may be removed by removing only a part of the thickness in the thickness direction! /.
  • FIGS. 8a to 8f are diagrams showing a manufacturing process of an organic composite electronic device including a top gate stagger type transistor and a capacitor.
  • a first electrode group forming step is performed in which one of the transistor source electrode So, drain Dr, and capacitor counter electrode CE 1 is formed in the same step on the substrate 11, and the organic semiconductor film 16 is formed thereon.
  • An organic semiconductor film forming step is performed (FIG. 8a).
  • An undercoat layer (not shown) may be formed on the substrate 11, and these electrodes So, Dr, and CE1 may be formed on the undercoat layer.
  • An organic semiconductor film removing step is performed to remove the surrounding portion of the substrate.
  • This organic semiconductor film removing step includes a mask forming step (FIG. 8a) for forming or placing a mask MS1 on the organic semiconductor film 16, and an etching step for removing a portion corresponding to the capacitor counter electrode CE1 by etching or the like. And a mask removing process for removing the mask MS1. As a result, a removal portion is formed in the portion corresponding to the counter electrode CE1 for the capacitor of the organic semiconductor film 16 and its surrounding portion (FIG. 8b).
  • a low dielectric film forming step is performed to form a low dielectric film 17a having a lower dielectric constant than that of a ferroelectric film 17b described later (FIG. 8c.
  • a low dielectric film removal step is performed to remove the portion corresponding to the capacitor counter electrode CE1 (may include the vicinity thereof! /), Which is performed on the low dielectric film 17a.
  • a removal portion is formed in the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 (FIG. 8d).
  • a ferroelectric film forming step for forming the ferroelectric film 17b is performed (FIG. 8e). Thereafter, a transistor gate electrode is formed so that the transistor is configured in a predetermined positional relationship with the transistor source electrode So and the drain electrode Dr across the organic semiconductor film 16, the low dielectric film 17a, and the ferroelectric film 17b.
  • a second electrode group forming step is performed in which the capacitor counter electrode CE2 is formed in the same process corresponding to the capacitor counter electrode CE1 so as to constitute a capacitor with Ga and the ferroelectric film 17b interposed therebetween (FIG. 8f). ). After that, although not shown, a protective film is formed by performing a protective film forming step.
  • an organic composite electronic device including an organic thin film transistor Tr having the low dielectric film 17a and the ferroelectric film 17b as the gate insulating film 17 and a high dielectric capacitor Ca having the ferroelectric film 17b as the insulating film is manufactured.
  • the portion of the organic semiconductor film 16 in which the capacitor is formed is removed in the organic semiconductor film removing step.
  • the organic semiconductor film 16 may be formed except for the part where the capacitor is formed in the forming process.
  • the capacitor of the low dielectric film 17a is formed in the low dielectric film removal step.
  • the low dielectric film 17a may be formed by removing the portion where the capacitor is formed in the low dielectric film forming step.
  • the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 may be removed by removing only a portion of the thickness direction! / ,.
  • FIG. 9a to FIG. 9f are diagrams showing a manufacturing process of an organic composite electronic device including a transistor and a capacitor of a top gate coplanar type.
  • an organic semiconductor film forming step for forming the organic semiconductor film 16 on the substrate 11 is performed (FIG. 9a).
  • An undercoat layer (not shown) may be formed on the substrate 11 and the organic semiconductor film 16 may be formed on the undercoat layer.
  • an organic semiconductor film removing step is performed to remove the portion of the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 and the surrounding portion thereof.
  • This organic semiconductor film removal step includes a mask formation step (FIG.
  • a low dielectric film forming step for forming a low dielectric film 17a having a lower dielectric constant than that of a ferroelectric film 17b described later is performed (FIG. 9c).
  • a low dielectric film removal step is performed to remove a portion of the low dielectric film 17a corresponding to the counter electrode CE1 for the capacitor (including the vicinity thereof! /).
  • This low dielectric film removal process includes a mask formation process (FIG. 9c) for forming or placing a mask MS2 on the low dielectric film 17a, and an etching process for removing a portion corresponding to the capacitor counter electrode CE1 by etching or the like.
  • a removal portion is formed in the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 (FIG. 9d).
  • a ferroelectric film forming step for forming the ferroelectric film 17b is performed (FIG. 1).
  • the transistor source electrode So and drain are sandwiched between the low dielectric film 17a and the ferroelectric film 17b.
  • the transistor gate electrode Ga is configured so as to configure the transistor in a predetermined positional relationship with the transistor electrode Dr, and the capacitor corresponding to the capacitor counter electrode CE1 so as to configure the capacitor sandwiching the ferroelectric film 17b.
  • a second electrode group forming process is performed in which the counter electrode CE2 is formed in the same process (FIG. 9f).
  • a protective film is formed by performing a protective film forming step.
  • an organic composite electronic device including an organic thin film transistor Tr having a low dielectric film 17a and a ferroelectric film 17b as a gate insulating film 17 and a high dielectric capacitor Ca having a ferroelectric film 17b as an insulating film is manufactured. Is done.
  • the portion of the organic semiconductor film 16 in which the capacitor is formed is removed in the organic semiconductor film removing step.
  • the organic semiconductor film 16 may be formed excluding the portion where the capacitor is formed and the surrounding portion in the forming step.
  • the low dielectric film 17a removes the capacitor forming portion of the low dielectric film 17a.
  • the low dielectric film 17a may be formed except for the part where the capacitor is formed in the film forming process.
  • the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 may be removed by removing only a portion of the thickness in the thickness direction.
  • the material for forming the organic semiconductor film constituting the thin film transistor of the organic composite electronic device of the second embodiment, the method of forming (forming) the same, and the like are the same as those of the first embodiment described above.
  • the material for forming the gate electrode, the source electrode and the drain electrode constituting the thin film transistor of the organic composite electronic device of the second embodiment, and the pair of counter electrodes constituting the high dielectric capacitor, and the film formation (formation) method thereof are as follows: This is the same as the first embodiment described above.
  • a single-layer film having a ferroelectric film force is used as an insulating film for a capacitor.
  • the low dielectric film and the ferroelectric film are the same as the transistor. You can also use a two-layered film with body layers stacked! /.
  • the relative dielectric constant of the low dielectric film and the ferroelectric film, the forming material, the film formation (formation) method, and the like are the same as those in the first embodiment described above.
  • a uniform film is formed by using the spin coating method described above, and then a photoresist is formed thereon.
  • a method can be used in which a mask pattern is formed or a mask such as a metal mask is provided and unnecessary portions are removed by etching.
  • etching method either dry etching or wet etching may be used, but dry etching is preferable. Examples of dry etching methods include gas etching, ion etching, plasma etching, ICP (Inductively Coupled Plasma Inductive Coupling), radical ion etching (RIE), and the like.
  • a method of forming a film by removing the removal portion may be used.
  • a solution or a dispersion liquid of a low dielectric material may be formed only on a necessary portion by a direct ink jet method or the like, or after unnecessary portions are masked and formed using a printing method or the like, the mask is formed. You may make it remove.
  • the protective film and substrate forming material of the organic composite electronic device of the second embodiment, and the film forming (forming) method or manufacturing method thereof are the same as those of the first embodiment described above.
  • an undercoat layer containing a compound selected from a polymer or an inorganic oxide and an inorganic nitride may be provided on the substrate.
  • the material for forming the undercoat layer, the film formation (formation) method, and the like are the same as in the first embodiment described above.
  • the inorganic oxide contained in the undercoat layer includes titanium oxide, tin oxide, vanadium oxide, as well as the silicon oxide, aluminum oxide, and tantalum oxide exemplified in the first embodiment.
  • the organic composite electronic device manufactured as described above has a signal writing characteristic and a charge storing characteristic. Therefore, for example, it is suitable for manufacturing a memory, particularly a signal circuit for a wireless transmission tag. It can be used suitably.
  • a capacitor type organic semiconductor memory can be configured by arranging the organic composite electronic elements manufactured as described above in a matrix on a substrate.
  • FIG. 10 is a diagram showing a circuit of an organic semiconductor memory cell of 1T1C (1 transistor ⁇ 1 capacitor) type. The sense amplifier is not shown. Writing is performed by activating the WL (lead line) of the corresponding cell, turning on the FET (Tr), and applying a voltage between BL (bit line) and PL (plate line). .
  • BL Vcc PL is GND (OV)
  • the upper part of the capacitor Ca is + (plus) and the lower part is (minus) polarization, and "1" is written.
  • BL is GND PL and Vcc, the upper part of the capacitor is at the bottom.
  • the organic composite electronic device according to the present embodiment can be applied to a 2T2C (2-transistor / 2-capacitor) type high-dielectric memory cell in addition to such a 1T1C-type high-dielectric memory cell. .
  • FIGS. 11a to l lf are diagrams illustrating a manufacturing process of an organic composite electronic device including a bottom gate stagger type transistor.
  • a first electrode group forming step is performed in which the first transistor gate electrode Gal and the second transistor gate electrode Ga2 are formed on the substrate 11 in the same step (FIG. 11a).
  • An undercoat layer (not shown) may be formed on the substrate 11, and these electrodes GalGa2 may be formed on the undercoat layer.
  • the undercoat An insulating film forming step for forming an insulating film 17 on the layer is performed (FIG. 1 lb).
  • a ferroelectric film forming step for forming the ferroelectric film 17b, and a low dielectric film formation for forming the low dielectric film 17a having a low dielectric constant on the ferroelectric film 17b are performed.
  • a process is included.
  • a low dielectric film removal step is performed to remove a part of the low dielectric film 17a in order to form a later-described source / drain electrode in a predetermined positional relationship with the second transistor gate electrode Ga2.
  • This low dielectric film removal process includes a mask formation process (FIG. 11c) for forming or placing a mask MS on the low dielectric film 17a, and an etching process for removing a part of the low dielectric film 17a by etching or the like. A step and a mask removing step of removing the mask MS.
  • a transistor is configured in a predetermined positional relationship with the gate electrode Gal for the first transistor across the ferroelectric film 17b, the low dielectric film 17a, and the organic semiconductor film 16.
  • Source electrode Sol, drain electrode Drl, and second transistor source electrode so that the transistor is configured in a predetermined positional relationship with second transistor gate electrode Ga2 across ferroelectric film 17b and organic semiconductor film 16
  • a second electrode group forming process is performed in which So2 and drain electrode Dr2 are formed in the same process (FIG. 1, If).
  • a protective film is formed by performing a protective film forming step.
  • an organic composite electronic device including an organic thin film transistor Trl using the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and an organic thin film transistor Tr2 using the ferroelectric film 17b as the gate insulating film is manufactured.
  • the portion of the low dielectric film 17a where the second transistor is formed (part of the low dielectric film 17a)
  • the low dielectric film 17a may be formed except for the portion where the second transistor is formed in the low dielectric film formation step.
  • a part of the low dielectric film 17a may be removed not only in the thickness direction.
  • FIGS. 12a to 12f are diagrams illustrating a manufacturing process of an organic composite electronic device including a bottom gate coplanar type transistor.
  • a first electrode group forming process is performed in which the first transistor gate electrode Gal and the second transistor gate electrode Ga2 are formed on the substrate 11 in the same process (FIG. 12a).
  • An undercoat layer (not shown) may be formed on the substrate 11, and these electrodes Gal and Ga2 may be formed on the undercoat layer.
  • an insulating film forming step is performed in which an insulating film 17 is formed on the substrate 11 including these electrodes Gal and Ga2 (on the undercoat layer when the undercoat layer is formed) (FIG. 12b).
  • the insulating film forming process includes a ferroelectric film forming process for forming the ferroelectric film 17b and a low dielectric film forming process for forming the low dielectric film 17a having a low dielectric constant on the ferroelectric film 17b. Is included
  • a low dielectric film removal step is performed to remove a part of the low dielectric film 17a in order to form a later-described source / drain electrode in a predetermined positional relationship with the second transistor gate electrode Ga2.
  • This low dielectric film removal process includes a mask formation process (FIG. 12c) for forming or placing a mask MS on the low dielectric film 17a, and an etching process for removing a part of the low dielectric film 17a by etching or the like.
  • a step and a mask removing step of removing the mask MS As a result, a removed portion of the low dielectric film 17a for forming a later-described source / drain electrode in a predetermined positional relationship with the second transistor gate electrode Ga2 is formed (FIG. 12d).
  • the first transistor source electrode Sol and the drain electrode are formed so as to form a transistor in a predetermined positional relationship with the first transistor gate electrode Gal across the ferroelectric film 17b and the low dielectric film 17a.
  • the second transistor source electrode So2 and the drain electrode Dr2 are formed in the same process so that the transistor is configured in a predetermined positional relationship with the second transistor gate electrode Ga2 across the Drl and the ferroelectric film 17b.
  • performing two electrodes forming step (Fig. 12e) 0
  • each electrode Sol, Drl, So2 performs the organic semiconductor film forming step of forming an organic semiconductor film 16 on the low dielectric film 17a containing Dr2 ( Figure 12f ).
  • a protective film is formed by performing a protective film forming step.
  • an organic composite electronic device including the organic thin film transistor Trl having the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and the organic thin film transistor Tr2 having the ferroelectric film 17b as the gate insulating film is manufactured.
  • the low dielectric film 17a after forming the low dielectric film 17a in the low dielectric film formation step, the portion of the low dielectric film 17a where the second transistor is formed (part of the low dielectric film 17a)
  • the low dielectric film 17a may be formed except for the portion where the second transistor is formed in the low dielectric film formation step.
  • the low dielectric film removal step a part of the low dielectric film 17a may be removed not only in the thickness direction.
  • FIG. 13a to FIG. 13f are diagrams illustrating a manufacturing process of an organic composite electronic device including a top gate stagger type transistor.
  • a first electrode group forming process is performed in which the first transistor source electrode Sol, the drain electrode Drl, the second transistor source electrode So2, and the drain electrode Dr2 are formed on the substrate 11 in the same process (FIG. 13a).
  • An undercoat layer (not shown) may be formed on the substrate 11, and these electrodes Sol, Dr1, So2, and Dr2 may be formed on the undercoat layer.
  • the low dielectric film removal is performed to remove a part of the low dielectric film 17a in order to form the gate electrode described later in a predetermined positional relationship with the source electrode So2 and the drain electrode Dr2 for the second transistor. Perform the process.
  • This low dielectric film removal step includes a mask formation step (FIG. 13c) for forming or placing a mask MS on the low dielectric film 17a, and an etching for removing a part of the low dielectric film 17a by etching or the like. And a mask removing step for removing the mask MS.
  • a removal portion of the low dielectric film 17a for forming a gate electrode described later in a predetermined positional relationship with the source electrode So2 and the drain electrode Dr2 for the second transistor is formed (FIG. 13d).
  • a ferroelectric film forming step of forming a ferroelectric film 17b on the low dielectric film 17a including the removed portion is performed (FIG. 13e).
  • a transistor is configured in a predetermined positional relationship with the source electrode Sol and the drain electrode Drl for the first transistor across the organic semiconductor film 16, the low dielectric film 17a, and the ferroelectric film 17b.
  • First transistor gate electrode Gal, ferroelectric film 17b and organic semiconductor Second electrode group forming step in which the second transistor gate electrode Ga2 is formed in the same process so as to form a transistor with a predetermined positional relationship with the second transistor source electrode So2 and drain electrode Dr2 across the film 16.
  • a protective film is formed by performing a protective film forming step.
  • an organic composite electronic device including an organic thin film transistor Trl using the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and an organic thin film transistor Tr2 using the ferroelectric film 17b as the gate insulating film is manufactured.
  • the portion of the low dielectric film 17a where the second transistor is formed (part of the low dielectric film 17a)
  • the low dielectric film 17a may be formed except for the portion where the second transistor is formed in the low dielectric film formation step.
  • a part of the low dielectric film 17a may be removed not only in the thickness direction.
  • FIG. 14a to FIG. 14f are diagrams illustrating a manufacturing process of an organic composite electronic device including a transistor of a top gate coplanar type.
  • the organic semiconductor film forming process for forming the organic semiconductor film 16 is performed on the substrate 11, and then the source electrode Sol for the first transistor, the drain electrode Drl, the source electrode So2 for the second transistor, the drain electrode Dr2
  • a first electrode group forming step is performed in which the steps are formed in the same step (FIG. 14a).
  • An undercoat layer (not shown) may be formed on the substrate 11 and the organic semiconductor film 16 may be formed on the undercoat layer.
  • a low dielectric film forming step for forming a low dielectric film 17a on the organic semiconductor film 16 containing these electrodes Sol, Drl, So2, and Dr2 is performed (FIG. 14b).
  • the low dielectric film removal is performed to remove a part of the low dielectric film 17a in order to form the gate electrode described later in a predetermined positional relationship with the source electrode So2 and the drain electrode Dr2 for the second transistor. Perform the process.
  • This low dielectric film removal process includes a mask formation process (FIG. 14c) for forming or placing a mask MS on the low dielectric film 17a, and an etching process for removing a part of the low dielectric film 17a by etching or the like. And a mask removing step for removing the mask MS.
  • the second transistor source electrode So2 and drain electrode Dr2 Due to the arrangement, a removed portion of the low dielectric film 17a for forming a gate electrode described later is formed (FIG. 14d). Thereafter, a ferroelectric film forming step of forming a ferroelectric film 17b on the low dielectric film 17a including the removed portion is performed (FIG. 14e).
  • the first transistor gate electrode is configured so that the transistor is configured in a predetermined positional relationship with the first transistor source electrode Sol and the drain electrode Drl with the low dielectric film 17a and the ferroelectric film 17b interposed therebetween.
  • the second transistor gate electrode Ga2 is formed in the same process so that the transistor is configured in a predetermined positional relationship with the source electrode So2 and drain electrode Dr2 of the second transistor across Gal and the ferroelectric film 17b.
  • the second electrode group forming step is performed (FIG. 14f). Then, although illustration is abbreviate
  • an organic composite electronic device including an organic thin film transistor Trl having the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and an organic thin film transistor Tr2 having the ferroelectric film 17b as the gate insulating film is obtained. Manufactured.
  • the low dielectric film 17a after forming the low dielectric film 17a in the low dielectric film formation step, a portion of the low dielectric film 17a for forming the second transistor (a part of the low dielectric film 17a) is formed. Although removed, the low dielectric film 17a may be formed in the low dielectric film forming step except for the portion constituting the second transistor. In the low dielectric film removal step, a part of the low dielectric film 17a may be removed not only in the thickness direction.
  • the material for forming the organic semiconductor film constituting the organic thin film transistor of the organic composite electronic device of the third embodiment, the film formation (formation) method, and the like are the same as those in the first or second embodiment described above.
  • the material for forming the gate electrode, the source electrode and the drain electrode, and the method for forming (forming) the first and second organic thin film transistors constituting the first and second organic thin film transistors of the organic composite electronic device of the third embodiment are the same as those described in the first or second embodiment. It is the same as the form.
  • a gate insulating film for the first transistor As a gate insulating film for the first transistor, A two-layered film in which a low dielectric constant film having a low dielectric constant and a ferroelectric film are stacked is used, and a single layer film having a ferroelectric film force is used as a gate insulating film for the second transistor.
  • the relative dielectric constant, the forming material, the film forming (forming) method, and the like of the low dielectric film and the ferroelectric film are the same as those in the first or second embodiment described above.
  • a method for forming the low dielectric film when forming the removal portion described above the same method as described in the second embodiment may be used.
  • the material for forming the protective film and substrate of the organic composite electronic device of the third embodiment, the film forming (forming) method, the manufacturing method, and the like are the same as those in the first or second embodiment described above.
  • an undercoat layer containing a compound selected from a polymer or an inorganic oxide and an inorganic nitride may be provided on the substrate.
  • the material for forming the undercoat layer, the film formation (formation) method, and the like are the same as those in the first or second embodiment described above.
  • the second transistor of the organic composite electronic device manufactured as described above can be used as a 1T (1 transistor) type ferroelectric memory device, and the organic composite electronic device is arranged in a matrix on the substrate.
  • a ferroelectric memory FeRAM: Ferroelectric Random Access Memory
  • FIG. 15 is a diagram showing a circuit of an IT type ferroelectric memory element.
  • BL is a bit line
  • WL is a word line
  • Tr2 is a second organic thin film transistor.
  • the sense amplifier is not shown.
  • Examples of the present invention will be specifically described below.
  • the present invention was applied to manufacture an organic electronic device including a bottom-gate staggered organic thin film transistor (TFT) as shown in FIG. 2a.
  • bottom gate staggered organic thin film as shown in Figure 6f
  • An organic composite electronic device with a transistor (Tr) and a high dielectric capacitor (Ca) was manufactured.
  • an organic composite electronic device having two bottom gate / stagger type organic thin film transistors (Trl, Tr2) as shown in FIG. 1 If was manufactured.
  • a polyethylene terephthalate film substrate 25 mm x 10 mm x O. 5 mm in size
  • the gate electrode (and capacitor electrode) was formed by vapor-depositing aluminum on the substrate.
  • the aluminum was deposited so that the degree of vacuum was less than 1 ⁇ 10-2 Pa, the substrate temperature was RT (room temperature), and the film thickness was about 200 nm.
  • the ferroelectric film which is the first layer of the insulating film having a two-layer structure, is prepared by dissolving cyanoethylated cellulose (manufactured by Shin-Etsu Chemical Co., Ltd .: Cyanoresin CR—S (trade name)) in cyclopentanone Solutions with a concentration of 3-7% by weight were produced. This solution was formed by applying the spin coat method at a rotational speed of 3000 rpm for 30 seconds and drying at 100 ° C. for 2 minutes. This ferroelectric film had a thickness of about 300 nm and a relative dielectric constant of 17.
  • the low dielectric film which is the second layer of the insulating film is a 5% cyclohexane solution of alicyclic olefin polymer (manufactured by Nippon Zeon Co., Ltd .: ZEONEX (registered trademark) 480R) at a rotational speed of 5000 rpm. It was formed by applying for 30 seconds using a spin coating method and drying at 60 ° C. for 2 minutes. The thickness of this low dielectric film was about 300 nm and the relative dielectric constant was 2.2.
  • the organic semiconductor film was formed by vapor-depositing pentacene on the insulating film. Pentacene deposition is performed so that the degree of vacuum is less than 2 X 10-3 Pa, the substrate temperature is RT (room temperature), the deposition temperature is 185 ° C, the deposition rate is 0.06 nm / s, and the film thickness is about 50 nm. It was.
  • Fig. 16 is a VD ID fountain diagram when VD is changed between + 10V and 30V with VG kept constant
  • Fig. 17 shows VG with + 10V when VD is kept constant (30V). Change between 30V It is a VG-ID diagram when it is made to be.
  • the organic transistor (Tr, Trl) in which the two-layer insulating film of the ferroelectric film and the low dielectric film of this example is used as a gate insulating film can be operated at a low V and a driving voltage. It can be seen that it has good characteristics with very little hysteresis.
  • the second transistor (Tr2) of the organic composite electronic device having two transistors manufactured as described above that is, an organic thin film transistor (organic TFT) having a single-layer ferroelectric film as a gate insulating film.
  • organic TFT organic thin film transistor
  • the electrical characteristics were evaluated by measuring the current-voltage curve, and the results are shown in Fig.18. It can be seen that the second transistor (Tr2) can be operated with a low driving voltage and has a large hysteresis, so that it is suitable for use in a ferroelectric memory.

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Abstract

An organic thin film transistor is provided with a gate electrode (18), a gate insulating film (17), an organic semiconductor film (16), a drain electrode (14) and a source electrode (15) on a substrate (11). The gate insulating film (17) has a double layer structure of a low dielectric constant film (17a) and a ferroelectric film (17b). The low dielectric constant film (17a) is arranged between the ferroelectric film (17b) and the organic semiconductor film (16), and the low dielectric constant film (17a) includes an organic polymeric compound which does not have a functional group that has an unshared electron pair nor π electron coupling within the molecular structure.

Description

明 細 書  Specification
有機薄膜トランジスタ、有機複合電子素子、これらの製造方法、表示装置 、及びメモリ  Organic thin film transistor, organic composite electronic device, manufacturing method thereof, display device, and memory
技術分野  Technical field
[0001] 本発明は、有機薄膜トランジスタ、該有機薄膜トランジスタの製造方法、及び該有 機薄膜トランジスタを備える有機 EL表示装置などの表示装置に関する。  The present invention relates to an organic thin film transistor, a method for producing the organic thin film transistor, and a display device such as an organic EL display device including the organic thin film transistor.
[0002] また、本発明は、有機薄膜トランジスタと高誘電体キャパシタとを備える有機複合電 子素子、該有機複合電子素子の製造方法、及び該有機複合電子素子を用いる有機 半導体メモリに関する。 The present invention also relates to an organic composite electronic device including an organic thin film transistor and a high dielectric capacitor, a method for manufacturing the organic composite electronic device, and an organic semiconductor memory using the organic composite electronic device.
[0003] さらに、本発明は、性能の異なる 2以上の有機薄膜トランジスタを備える有機複合電 子素子、該有機複合電子素子の製造方法、及び該有機複合電子素子を用いる強誘 電体メモリに関する。 背景技術  Furthermore, the present invention relates to an organic composite electronic device comprising two or more organic thin film transistors having different performances, a method for producing the organic composite electronic device, and a strong dielectric memory using the organic composite electronic device. Background art
[0004] 有機薄膜トランジスタは、例えば、基板、ゲート電極、ゲート絶縁膜、ソース電極、ド レイン電極、有機半導体膜及び保護膜を積層した構造を有している。有機薄膜トラン ジスタは、印刷法などの常温 ·常圧下での低コスト製造プロセスによって得ることがで き、し力、も柔軟な基板への適合性が良い。その特性を活力、して、有機薄膜トランジス タは、液晶表示装置、有機エレクト口ルミネッセンス(EU表示装置、電気泳動表示装 置等のフラットパネルディスプレイの画像駆動素子への適用や、シートディスプレイ、 電子ペーパー、電子値札'電子荷札などの電子タグ、バイオセンサー等の電子機器 の集積回路技術への適用が期待されている。  [0004] An organic thin film transistor has, for example, a structure in which a substrate, a gate electrode, a gate insulating film, a source electrode, a drain electrode, an organic semiconductor film, and a protective film are stacked. Organic thin-film transistors can be obtained by a low-cost manufacturing process under normal temperature and normal pressure, such as printing, and have good strength and compatibility with flexible substrates. By virtue of its characteristics, organic thin film transistors can be applied to image drive elements of flat panel displays such as liquid crystal display devices and organic electoluminescence (EU display devices, electrophoretic display devices, sheet displays, electronic It is expected to be applied to integrated circuit technology for electronic devices such as paper, electronic price tags and electronic tags, and biosensors.
[0005] このように期待される有機薄膜トランジスタの特性を向上させるために、チャネル層 の有機半導体の移動度を高くすることが考えられてレ、る。その有機半導体の移動度 がゲート絶縁膜の材質によって変化することが知られており、有機ゲート絶縁膜用の 材料開発が盛んに行われるようになつてきた。  [0005] In order to improve the characteristics of the organic thin film transistor expected as described above, it is considered to increase the mobility of the organic semiconductor in the channel layer. It is known that the mobility of the organic semiconductor varies depending on the material of the gate insulating film, and material development for the organic gate insulating film has been actively conducted.
[0006] 例えば、 日本国特表平 5— 508745号公報及び米国特許 5347144号公報に開示 されている有機薄膜トランジスタでは、ドレイン電流を大きくとるには、ゲート絶縁膜の 単位面積当りの電気容量が大きい方がよいので、高誘電率、少なくとも 5の比誘電率 を持つ、絶縁性の高レ、ポリマー(シァノエチルプルランなど)をゲート絶縁膜に用いて いる。このシァノエチルプルランは比誘電率が 18. 5である。 [0006] For example, in the organic thin film transistor disclosed in Japanese Patent Publication No. 5-508745 and US Pat. No. 5,347,144, in order to increase the drain current, Since it is better to have a larger electric capacity per unit area, a high dielectric constant, a dielectric constant of at least 5 and a high insulating polymer (such as cyanoethyl pullulan) are used for the gate insulating film. This cyanoethyl pullulan has a dielectric constant of 18.5.
[0007] また、 日本国特開 2004— 179542号公報において、有機ゲート絶縁材料として、 シァノ基を有するポリマーであるポリアクリロニトリルが提案されている。ポリアタリロニト リルの比誘電率は 4· 5である。さらに、 日本国特開 2004— 179542号公報ではゲー ト絶縁膜として、ポリイミド、ポリスチレン、ポリメチルメタタリレート、ポリビュルクロライド 、ポリビュルアルコール、ポリパラキシレン、ポリフッ化ビニリデン、ポリビュルフエノー ノレ、プルラン、ノ リレンなどのポリマー及びその誘導体が提案されている。 日本国特 開平 8— 191162号公報には、さらに、より効果的な電界効果を得るために誘電率を 大きくするための材料を混入した複合材料を用いることが提案されている。  [0007] In Japanese Patent Application Laid-Open No. 2004-179542, polyacrylonitrile, which is a polymer having a cyano group, is proposed as an organic gate insulating material. The relative dielectric constant of polyatrylonitrile is 4.5. Furthermore, in Japanese Patent Application Laid-Open No. 2004-179542, as a gate insulating film, polyimide, polystyrene, polymethylmetatalylate, polybuluchloride, polybulualcohol, polyparaxylene, polyvinylidene fluoride, polybutanol, Polymers such as pullulan and norylene and their derivatives have been proposed. In Japanese Patent Publication No. 8-191162, it is further proposed to use a composite material mixed with a material for increasing the dielectric constant in order to obtain a more effective electric field effect.
[0008] しかしながら、これらの有機材料は、膜厚を大きく確保しておかな!/、と、絶縁膜にト ンネル現象によるゲートリーク電流が流れてしまい、絶縁性が保たれなくなってしまい 、優れた特性を安定的に実現することができない場合があるとともに、高い絶縁膜容 量を実現することができず、低ゲート電圧で動作可能にすることが難しい場合があつ た。  [0008] However, these organic materials have an excellent film thickness! /, And a gate leakage current due to a tunnel phenomenon flows through the insulating film, and the insulating property cannot be maintained. In some cases, it was not possible to achieve stable characteristics, and it was difficult to achieve high insulation film capacity and to enable operation with a low gate voltage.
[0009] また、有機薄膜トランジスタや有機強誘電体キャパシタ等の電子素子は、従来の無 機材料を用いる電子素子と比較して、印刷法などの常温 ·常圧下での低コスト製造プ ロセスによって得ることができ、基板などの材料の制約が少ないなどの理由から、近 時、有機 ELディスプレイ等のフラットパネルディスプレイや強誘電体メモリ(FeRAM : Ferroelectric Random Access Memory)などへの応用がなされている。このような電子 素子を複数用いて基板上に回路を形成する場合、同一の電子素子については同一 の製造プロセスにより製造することができる。し力、しながら、例えば、ゲート絶縁膜の 絶縁膜容量の異なる複数種類の有機薄膜トランジスタを基板上に形成する場合や有 機薄膜トランジスタと有機キャパシタとを基板上に形成する場合等、異なる種類の電 子素子を形成する場合には、用いる誘電体の誘電率や求められる素子の特性等が 異なるため、それぞれ異なる製造プロセス(成膜プロセス)を用いて製造されて!/、るの が現状である。従って、製造のための工数が多ぐ有機複合電子素子の低コスト化の 障害となる場合があった。 [0009] In addition, electronic devices such as organic thin film transistors and organic ferroelectric capacitors are obtained by a low-cost manufacturing process under normal temperature and normal pressure, such as a printing method, as compared to electronic devices using conventional inorganic materials. In recent years, it has been applied to flat panel displays such as organic EL displays and ferroelectric memory (FeRAM: Ferroelectric Random Access Memory) because of the few restrictions on materials such as substrates. When a circuit is formed on a substrate using a plurality of such electronic elements, the same electronic element can be manufactured by the same manufacturing process. However, for example, when different types of organic thin film transistors having different insulating film capacities of the gate insulating film are formed on the substrate, or when organic thin film transistors and organic capacitors are formed on the substrate, different types of electric transistors are used. When forming a child element, the dielectric constant of the dielectric to be used and the required element characteristics are different, so it is currently manufactured using a different manufacturing process (film formation process)! . Therefore, it is possible to reduce the cost of organic composite electronic devices that require many man-hours for manufacturing. There were cases where it was an obstacle.
[0010] 異なる種類の電子素子を基板上に形成するための従来技術としては、例えば、有 機薄膜トランジスタと強誘電体キャパシタを備える強誘電体メモリの製造方法(日本 国特開 2006— 245185号公報)が提案されている。すなわち、この公報には、基板 上に有機薄膜トランジスタを形成した後、電極上にさらに強誘電体膜及びキャパシタ 用の電極を形成する方法が開示されている。この方法では、ある程度、素子の製造 の容易化は図れるものの、トランジスタを形成した後に、強誘電体膜及びキャパシタ 用の電極を別途成膜するものであるから、依然として工数が多いという問題がある。 発明の開示 As a conventional technique for forming different types of electronic elements on a substrate, for example, a method for manufacturing a ferroelectric memory including an organic thin film transistor and a ferroelectric capacitor (Japanese Patent Laid-Open No. 2006-245185) ) Has been proposed. That is, this publication discloses a method in which after forming an organic thin film transistor on a substrate, a ferroelectric film and an electrode for a capacitor are further formed on the electrode. Although this method can facilitate the manufacture of the device to some extent, there is a problem that the number of steps is still large because the ferroelectric film and the electrode for the capacitor are separately formed after the transistor is formed. Disclosure of the invention
[0011] 本発明の第 1の目的は、ゲート絶縁膜におけるリーク電流が抑止され、高い絶縁膜 容量が得られ、低ゲート電圧で動作可能な有機薄膜トランジスタ、その製造方法、及 び該有機薄膜トランジスタを用いる表示装置を提供することである。  [0011] A first object of the present invention is to provide an organic thin film transistor capable of suppressing leakage current in a gate insulating film, obtaining a high insulating film capacity, and operating at a low gate voltage, a method for producing the same, and the organic thin film transistor. It is to provide a display device to be used.
[0012] 本発明の第 2の目的は、有機薄膜トランジスタと、高誘電体キャパシタとを備える有 機複合電子素子の製造工程の簡略化を図ることである。  A second object of the present invention is to simplify the manufacturing process of an organic composite electronic device including an organic thin film transistor and a high dielectric capacitor.
[0013] 本発明の第 3の目的は、互いに異なる性能を有する 2以上の有機薄膜トランジスタ を備える有機複合電子素子の製造工程を簡略化することである。  [0013] A third object of the present invention is to simplify a manufacturing process of an organic composite electronic device including two or more organic thin film transistors having different performances.
[0014] 上述した第 1の目的を達成するため、本発明者らは、従来、有機薄膜トランジスタに 用いられて!/、た有機ゲート絶縁膜材料を種々検討した結果、分子構造中に存在する 官能基の電子対及びベンゼン環等の π電子がリーク電流に影響していることに気づ き、さらに検討した結果、非共有電子対を有する官能基を持たず且つ分子構造内に π電子結合を持たない有機高分子化合物を用いて低誘電体膜を形成し、この低誘 電体膜と強誘電体膜とを積層してゲート絶縁膜を構成することにより、該ゲート絶縁 膜は良質でピンホールができにくい膜となり、ゲート絶縁膜におけるリーク電流が抑 止され、高い絶縁膜容量が得られ、低ゲート電圧で動作可能な有機薄膜トランジスタ が得られることを見出した。本発明者らはこの知見に基づいて本発明を完成するに 至ったものである。  [0014] In order to achieve the first object described above, the present inventors have studied various organic gate insulating film materials conventionally used for organic thin film transistors, and as a result, have found that there is a sensory function present in the molecular structure. As a result of further investigation, it was found that there was no functional group with an unshared electron pair and a π-electron bond in the molecular structure. A low dielectric film is formed using an organic polymer compound that does not have a layer, and this low dielectric film and a ferroelectric film are laminated to form a gate insulating film. It was found that an organic thin film transistor capable of operating at a low gate voltage can be obtained because the film becomes difficult to form holes, the leakage current in the gate insulating film is suppressed, a high insulating film capacity is obtained. Based on this knowledge, the inventors have completed the present invention.
[0015] すなわち、本発明の第 1の観点によれば、基板上に、ゲート電極、ゲート絶縁膜、 有機半導体膜、ソース電極、及びドレイン電極を備える有機薄膜トランジスタであって 、前記ゲート絶縁膜は、強誘電体膜、及び該強誘電体膜と前記有機半導体膜との間 に介装される、強誘電体膜と比較して低誘電率を有する低誘電体膜を有し、前記低 誘電体膜は、非共有電子対を有する官能基を持たず且つ分子構造内に 71電子結 合を持たない有機高分子化合物を含む有機薄膜トランジスタが提供される。 That is, according to a first aspect of the present invention, there is provided an organic thin film transistor comprising a gate electrode, a gate insulating film, an organic semiconductor film, a source electrode, and a drain electrode on a substrate. The gate insulating film includes a ferroelectric film, and a low dielectric film having a low dielectric constant compared to the ferroelectric film interposed between the ferroelectric film and the organic semiconductor film. The low-dielectric film includes an organic thin film transistor including an organic polymer compound that does not have a functional group having an unshared electron pair and does not have 71 electronic bonds in the molecular structure.
[0016] また、基板上にゲート電極を形成する第 1工程と、前記ゲート電極を含む前記基板 上に強誘電体膜を形成する第 2工程と、前記強誘電体膜上に強誘電体膜と比較して 低誘電率を有する低誘電体膜を形成する第 3工程と、前記低誘電体膜上に有機半 導体膜を形成する第 4工程と、前記有機半導体膜上にソース電極及びドレイン電極 を形成する第 5工程とを備え、前記第 3工程は、非共有電子対を有する官能基を持 たず且つ分子構造内に 71電子結合を持たなレ、有機高分子化合物を溶媒に溶かし 溶液を得る工程、及び該溶液を流延させた後、溶媒を除去する工程を有する有機薄 膜トランジスタの製造方法が提供される。また、前記有機薄膜トランジスタを備えてな る表示装置が提供される。  [0016] Further, a first step of forming a gate electrode on the substrate, a second step of forming a ferroelectric film on the substrate including the gate electrode, and a ferroelectric film on the ferroelectric film A third step of forming a low dielectric film having a low dielectric constant compared to the fourth step, a fourth step of forming an organic semiconductor film on the low dielectric film, and a source electrode and a drain on the organic semiconductor film. A fifth step of forming an electrode, wherein the third step dissolves an organic polymer compound in a solvent that does not have a functional group having an unshared electron pair and has 71 electronic bonds in the molecular structure. There is provided a method for producing an organic thin film transistor, which comprises a step of obtaining a solution, and a step of casting the solution and then removing the solvent. A display device comprising the organic thin film transistor is also provided.
[0017] 本発明の有機薄膜トランジスタは、ゲート絶縁膜におけるリーク電流が抑止され、安 定的に優れた性能を実現できるとともに、低いゲート電圧で動作させることができる。 また、本発明の有機薄膜トランジスタの製造方法は、特性が安定しており、高い絶縁 膜容量が得られ、低いゲート電圧で動作可能な有機薄膜トランジスタを製造すること ができる。本発明の有機薄膜トランジスタは、液晶表示装置、有機 EL (エレクト口ルミ ネッセンス)表示装置、電気泳動表示装置等のフラットパネルディスプレイの画像駆 動素子として用いること力 Sできる。また、シートディスプレイ、電子ペーパー、電子値札 •電子荷札などの電子タグ、バイオセンサー、ガスセンサー、メモリ素子等の電子機器 の集積回路技術に適用できる。特に本発明の有機薄膜トランジスタは低電圧で動作 できるということから、例えば有機 EL表示装置の画像駆動素子に好適である。  [0017] The organic thin film transistor of the present invention is capable of suppressing leakage current in the gate insulating film, realizing stable and excellent performance, and operating at a low gate voltage. In addition, the method for producing an organic thin film transistor of the present invention can produce an organic thin film transistor that has stable characteristics, has a high insulating film capacity, and can operate at a low gate voltage. The organic thin film transistor of the present invention can be used as an image driving element for a flat panel display such as a liquid crystal display device, an organic EL (electrical luminance) display device, and an electrophoretic display device. It can also be applied to integrated circuit technology for electronic devices such as sheet displays, electronic paper, electronic price tags and electronic tags, and biosensors, gas sensors, and memory elements. In particular, since the organic thin film transistor of the present invention can be operated at a low voltage, it is suitable for an image driving element of an organic EL display device, for example.
[0018] 上述した第 2の目的を達成するため、本発明の第 2の観点に係る有機複合電子素 子の製造方法は、基板上にトランジスタ及びキャパシタを備える有機複合電子素子 の製造方法であって、トランジスタ用第 1電極群及びキャパシタ用第 1電極群を形成 する第 1電極群形成工程と、強誘電体膜を形成する強誘電体膜形成工程と、強誘電 体膜と比較して低誘電率を有する低誘電体膜を形成する低誘電体膜形成工程と、 前記キャパシタを形成する部分を除き、前記トランジスタを形成する部分を含んで、 有機半導体膜を形成する有機半導体膜形成工程と、前記強誘電体膜及び前記低 誘電体膜を少なくとも挟んで前記トランジスタ用第 1電極群と所定の位置関係でトラン ジスタ用第 2電極群を、及び前記強誘電体膜を少なくとも挟んで前記キャパシタ用第 1電極群に対応してキャパシタ用第 2電極群を形成する第 2電極群形成工程とを備え て構成される。ここで、電極群とは、 1又は 2以上の電極をいう。また、所定の位置関 係とは、各電極がトランジスタを構成するように配置される位置関係をいう。 [0018] In order to achieve the second object described above, a method for producing an organic composite electronic device according to a second aspect of the present invention is a method for producing an organic composite electronic device comprising a transistor and a capacitor on a substrate. The first electrode group forming process for forming the first electrode group for the transistor and the first electrode group for the capacitor, the ferroelectric film forming process for forming the ferroelectric film, and low compared with the ferroelectric film. A low dielectric film forming step of forming a low dielectric film having a dielectric constant; An organic semiconductor film forming step for forming an organic semiconductor film, including a portion for forming the transistor, excluding a portion for forming the capacitor, and for the transistor with at least the ferroelectric film and the low dielectric film interposed therebetween A second electrode group for the transistor is formed in a predetermined positional relationship with the first electrode group, and a second electrode group for the capacitor is formed corresponding to the first electrode group for the capacitor at least across the ferroelectric film. And a two-electrode group forming step. Here, the electrode group refers to one or more electrodes. The predetermined positional relationship refers to a positional relationship in which each electrode is arranged so as to constitute a transistor.
[0019] 本発明では、トランジスタ用の強誘電体膜とキャパシタ用の強誘電体膜を同一の形 成工程で形成するとともに、トランジスタ用電極群とキャパシタ用電極群を同一の形 成工程で形成して!/、るので、それぞれ異なる形成工程で形成して!/、た従来技術と比 較して、トランジスタ及びキャパシタを有する有機複合電子素子を少な!/、工数で製造 すること力 Sでき、製造コストを削減することができる。しかも、トランジスタの絶縁膜 (ゲ ート絶縁膜)を、強誘電体膜と低誘電体膜とを積層することにより形成するようにした ので、該低誘電体膜の誘電率を適宜選定することにより、強誘電体膜と低誘電体膜 とからなる絶縁膜の誘電率を所望の値に設定することができるとともに、低ゲート電圧 で動作可能で、ヒステリシスの小さい良好な特性を有するトランジスタを形成すること ができる。 In the present invention, the transistor ferroelectric film and the capacitor ferroelectric film are formed in the same formation process, and the transistor electrode group and the capacitor electrode group are formed in the same formation process. Therefore, it is possible to manufacture organic composite electronic devices having transistors and capacitors with less man-hours compared to the conventional technology, which are formed by different forming processes! Manufacturing cost can be reduced. In addition, since the insulating film (gate insulating film) of the transistor is formed by laminating a ferroelectric film and a low dielectric film, the dielectric constant of the low dielectric film should be appropriately selected. This makes it possible to set the dielectric constant of an insulating film made of a ferroelectric film and a low dielectric film to a desired value, and to operate with a low gate voltage and to form a transistor with good characteristics with low hysteresis. can do.
[0020] このように、本発明によると、有機薄膜トランジスタと、高誘電体キャパシタとを備える 有機複合電子素子の製造を容易化できる。特に、本発明により製造された有機複合 電子素子は、例えば、無線伝送タグ用信号回路などの製造に好適に用いることがで きる。  As described above, according to the present invention, it is possible to facilitate the manufacture of an organic composite electronic device including an organic thin film transistor and a high dielectric capacitor. In particular, the organic composite electronic device manufactured according to the present invention can be suitably used for manufacturing, for example, a signal circuit for a wireless transmission tag.
[0021] 上述した第 3の目的を達成するため、本発明の第 3の観点に係る有機複合電子素 子の製造方法は、基板上に第 1トランジスタ及び第 2トランジスタを備える有機複合電 子素子の製造方法であって、第 1トランジスタ用第 1電極群及び第 2トランジスタ用第 1電極群を形成する第 1電極群形成工程と、強誘電体膜を形成する強誘電体膜形成 工程と、前記第 2トランジスタを形成する部分を除き、前記第 1トランジスタを形成する 部分を含んで、強誘電体膜と比較して低誘電率を有する低誘電体膜を形成する低 誘電体膜形成工程と、有機半導体膜を形成する有機半導体膜形成工程と、前記強 誘電体膜及び前記低誘電体膜を少なくとも挟んで前記第 1トランジスタ用第 1電極群 と所定の位置関係で第 1トランジスタ用第 2電極群を、及び前記強誘電体膜を少なく とも挟んで前記第 2トランジスタ用第 1電極群と所定の位置関係で第 2トランジスタ用 第 2電極群を形成する第 2電極群形成工程とを備えて構成される。ここで、電極群と は、 1又は 2以上の電極をいう。また、所定の位置関係とは、各電極がトランジスタを 構成するように配置される位置関係をいう。 In order to achieve the third object described above, an organic composite electronic device manufacturing method according to a third aspect of the present invention includes an organic composite electronic device including a first transistor and a second transistor on a substrate. A first electrode group forming step for forming a first electrode group for a first transistor and a first electrode group for a second transistor, and a ferroelectric film forming step for forming a ferroelectric film, A low dielectric film forming step of forming a low dielectric film having a low dielectric constant compared to a ferroelectric film, including a part forming the first transistor, except for a part forming the second transistor; An organic semiconductor film forming step of forming an organic semiconductor film, and the strong The second electrode group for the first transistor in a predetermined positional relationship with the first electrode group for the first transistor and at least the ferroelectric film between the first electrode group for the first transistor and at least the dielectric film and the low dielectric film, respectively. And a second electrode group forming step of forming the second electrode group for the second transistor in a predetermined positional relationship with the first electrode group for the second transistor. Here, the electrode group refers to one or more electrodes. Further, the predetermined positional relationship means a positional relationship in which each electrode is arranged so as to constitute a transistor.
[0022] 本発明では、第 1トランジスタ用の強誘電体膜と第 2トランジスタ用の強誘電体膜を 同一の形成工程で形成するとともに、第 1トランジスタ用電極群と第 2トランジスタ用電 極群を同一の形成工程で形成して!/、るので、それぞれ異なる形成工程で形成してレヽ た従来技術と比較して、 2種類のトランジスタを有する有機複合電子素子を少なレ、ェ 数で製造することができ、製造コストを削減することができる。しかも、第 1トランジスタ においては、強誘電体膜と低誘電体膜とを有する二層のゲート絶縁膜を形成するよ うにしたので、該低誘電体膜の誘電率を適宜選定することにより、強誘電体膜と低誘 電体膜とからなる絶縁膜の誘電率を所望の値に設定することができるとともに、低ゲ ート電圧で動作可能で、ヒステリシスの小さい良好な特性を有する有機薄膜トランジ スタを得ること力 Sできる。また、第 2トランジスタにおいては、強誘電体膜からなるゲート 絶縁膜を形成するようにしたので、例えば、強誘電体メモリに用いて好適な有機薄膜 トランジスタを得ることが可能となる。  In the present invention, the ferroelectric film for the first transistor and the ferroelectric film for the second transistor are formed in the same formation process, and the first transistor electrode group and the second transistor electrode group are formed. Therefore, it is possible to manufacture organic composite electronic devices with two types of transistors with a small amount and a small number compared to the conventional technology formed by different forming processes. Manufacturing cost can be reduced. In addition, since the first transistor is formed with a two-layer gate insulating film having a ferroelectric film and a low dielectric film, the dielectric constant of the low dielectric film can be selected appropriately. An organic thin film transistor having a good characteristic with low hysteresis, capable of setting a dielectric constant of an insulating film composed of a dielectric film and a low dielectric film to a desired value, being operable at a low gate voltage. The ability to get a star S. In the second transistor, since a gate insulating film made of a ferroelectric film is formed, an organic thin film transistor suitable for use in, for example, a ferroelectric memory can be obtained.
[0023] このように、本発明によると、互いに異なる性能を有する 2以上の有機薄膜トランジ スタを備える有機複合電子素子の製造を容易化できる。  As described above, according to the present invention, it is possible to facilitate the manufacture of an organic composite electronic device including two or more organic thin film transistors having different performances.
図面の簡単な説明  Brief Description of Drawings
[0024] [図 la]第 1実施形態のトップゲート'スタガー型の有機薄膜トランジスタの構成例を示 す図である。  [0024] FIG. La is a diagram showing a configuration example of a top gate staggered organic thin film transistor of the first embodiment.
[図 lb]第 1実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタの構成例を 示す図である。  FIG. Lb is a diagram showing a configuration example of a top gate coplanar type organic thin film transistor of the first embodiment.
[図 2a]第 1実施形態のボトムゲート'スタガー型の有機薄膜トランジスタの構成例を示 す図である。  FIG. 2a is a diagram showing a configuration example of a bottom-gate staggered organic thin film transistor of the first embodiment.
[図 2b]第 1実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタの構成例を 示す図である。 [Fig. 2b] Configuration example of bottom gate 'coplanar type organic thin film transistor of the first embodiment FIG.
園 3]第 1実施形態の有機 EL素子の構成例を示す図である。 3] A diagram showing a configuration example of the organic EL element of the first embodiment.
[図 4]第 1実施形態の有機 EL表示装置の一画素分の構成例を示す図である。  FIG. 4 is a diagram illustrating a configuration example of one pixel of the organic EL display device according to the first embodiment.
園 5]第 1実施形態のアクティブマトリックス方式の有機 EL表示装置の回路の一例を 示す図である。 5] An example of a circuit of the active matrix organic EL display device of the first embodiment.
園 6a]第 2実施形態のボトムゲート'スタガー型の有機薄膜トランジスタ及びキャパシ タを備える有機複合電子素子の製造工程 (その 1)を示す図である。 6a] is a diagram showing a manufacturing process (part 1) of an organic composite electronic device including a bottom-gate staggered organic thin film transistor and a capacitor according to a second embodiment.
園 6b]第 2実施形態のボトムゲート'スタガー型の有機薄膜トランジスタ及びキャパシ タを備える有機複合電子素子の製造工程 (その 2)を示す図である。 6b] A diagram showing a manufacturing process (part 2) of the organic composite electronic device including the bottom gate staggered organic thin film transistor and the capacitor according to the second embodiment.
園 6c]第 2実施形態のボトムゲート'スタガー型の有機薄膜トランジスタ及びキャパシ タを備える有機複合電子素子の製造工程 (その 3)を示す図である。 6c] is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the bottom gate staggered organic thin film transistor and the capacitor according to the second embodiment.
園 6d]第 2実施形態のボトムゲート'スタガー型の有機薄膜トランジスタ及びキャパシ タを備える有機複合電子素子の製造工程 (その 4)を示す図である。 6d] is a diagram showing a manufacturing process (No. 4) of the organic composite electronic device including the bottom gate staggered organic thin film transistor and the capacitor according to the second embodiment.
園 6e]第 2実施形態のボトムゲート'スタガー型の有機薄膜トランジスタ及びキャパシ タを備える有機複合電子素子の製造工程 (その 5)を示す図である。 6e] is a view showing a manufacturing process (No. 5) of the organic composite electronic device including the bottom gate staggered organic thin film transistor and the capacitor according to the second embodiment.
園 6f]第 2実施形態のボトムゲート'スタガー型の有機薄膜トランジスタ及びキャパシタ を備える有機複合電子素子の製造工程 (その 6)を示す図である。 6f] is a diagram showing a manufacturing process (No. 6) of the organic composite electronic device including the bottom gate staggered organic thin film transistor and the capacitor of the second embodiment.
園 7a]第 2実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 1)を示す図である。 FIG. 7a] is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including a bottom gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
園 7b]第 2実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 2)を示す図である。 FIG. 7b] is a diagram showing a manufacturing process (No. 2) of the organic composite electronic device including the bottom gate 'coplanar type organic thin film transistor and the capacitor of the second embodiment.
園 7c]第 2実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 3)を示す図である。 FIG. 7c] is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the bottom gate coplanar type organic thin film transistor and the capacitor according to the second embodiment.
園 7d]第 2実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 4)を示す図である。 FIG. 7d] is a diagram showing a manufacturing process (No. 4) of the organic composite electronic device including the bottom gate and coplanar type organic thin film transistor and capacitor of the second embodiment.
園 7e]第 2実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 5)を示す図である。 FIG. 7e] is a diagram showing a manufacturing process (No. 5) of an organic composite electronic device including a bottom-gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
園 7f]第 2実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 6)を示す図である。 7f] The bottom-gate coplanar type organic thin film transistor and capacitor of the second embodiment FIG. 11 is a diagram showing a manufacturing process (No. 6) of an organic composite electronic device including a shita.
園 8a]第 2実施形態のトップゲート'スタガー型の有機薄膜トランジスタ及びキャパシ タを備える有機複合電子素子の製造工程 (その 1 )を示す図である。 FIG. 8a] is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including a top gate stagger type organic thin film transistor and a capacitor according to a second embodiment.
園 8b]第 2実施形態のトップゲート'スタガー型の有機薄膜トランジスタ及びキャパシ タを備える有機複合電子素子の製造工程 (その 2)を示す図である。 FIG. 8b] is a diagram showing a manufacturing process (No. 2) of the organic composite electronic device including the top gate stagger type organic thin film transistor and the capacitor of the second embodiment.
園 8c]第 2実施形態のトップゲート'スタガー型の有機薄膜トランジスタ及びキャパシ タを備える有機複合電子素子の製造工程 (その 3)を示す図である。 FIG. 8c] is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the top gate staggered organic thin film transistor and the capacitor according to the second embodiment.
園 8d]第 2実施形態のトップゲート'スタガー型の有機薄膜トランジスタ及びキャパシ タを備える有機複合電子素子の製造工程 (その 4)を示す図である。 FIG. 8d] is a diagram showing a manufacturing process (No. 4) of the organic composite electronic device including the top gate staggered organic thin film transistor and the capacitor according to the second embodiment.
園 8e]第 2実施形態のトップゲート'スタガー型の有機薄膜トランジスタ及びキャパシ タを備える有機複合電子素子の製造工程 (その 5)を示す図である。 FIG. 8e] is a diagram showing a manufacturing process (No. 5) of the organic composite electronic device including the top gate stagger-type organic thin film transistor and capacitor of the second embodiment.
園 8f]第 2実施形態のトップゲート'スタガー型の有機薄膜トランジスタ及びキャパシタ を備える有機複合電子素子の製造工程 (その 6)を示す図である。 FIG. 8f] is a diagram showing a manufacturing process (No. 6) of the organic composite electronic device including the top gate stagger type organic thin film transistor and capacitor of the second embodiment.
園 9a]第 2実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 1 )を示す図である。 FIG. 9a] is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including a top-gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
園 9b]第 2実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 2)を示す図である。 FIG. 9b] is a diagram showing a manufacturing process (No. 2) of an organic composite electronic device including a top gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
園 9c]第 2実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 3)を示す図である。 FIG. 9c] is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the top gate coplanar type organic thin film transistor and the capacitor according to the second embodiment.
園 9d]第 2実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 4)を示す図である。 FIG. 9d] is a diagram showing a manufacturing process (No. 4) of an organic composite electronic device including a top gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
園 9e]第 2実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 5)を示す図である。 FIG. 9e] is a diagram showing a manufacturing process (No. 5) of an organic composite electronic device including a top gate coplanar type organic thin film transistor and a capacitor according to a second embodiment.
園 9f]第 2実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタ及びキャパ シタを備える有機複合電子素子の製造工程 (その 6)を示す図である。 FIG. 9f] is a diagram showing a manufacturing process (No. 6) of an organic composite electronic device including the top gate coplanar type organic thin film transistor and capacitor of the second embodiment.
園 10]第 2実施形態の高誘電体メモリセルの構成例を示す図である。 FIG. 10] A diagram showing a configuration example of the high dielectric memory cell of the second embodiment.
園 1 la]第 3実施形態のボトムゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 1 )を示す図である。 [図 1 lb]第 3実施形態のボトムゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 2)を示す図である。 FIG. 1 la] is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including the bottom gate stagger type organic thin film transistor of the third embodiment. FIG. 1 lb is a diagram showing a manufacturing process (No. 2) of an organic composite electronic device including a bottom-gate staggered organic thin film transistor according to a third embodiment.
[図 11c]第 3実施形態のボトムゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 3)を示す図である。  FIG. 11c is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the bottom-gate staggered organic thin film transistor of the third embodiment.
[図 1 Id]第 3実施形態のボトムゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 4)を示す図である。  FIG. 1 Id is a diagram showing a manufacturing process (No. 4) of an organic composite electronic device including a bottom-gate staggered organic thin film transistor according to a third embodiment.
[図 l ie]第 3実施形態のボトムゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 5)を示す図である。  FIG. 1 is a diagram showing a manufacturing process (No. 5) of an organic composite electronic device including a bottom-gate staggered organic thin film transistor according to a third embodiment.
[図 1 If]第 3実施形態のボトムゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 6)を示す図である。  FIG. 1 If is a diagram showing a manufacturing process (No. 6) of an organic composite electronic device including a bottom-gate staggered organic thin film transistor according to a third embodiment.
[図 12a]第 3実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 1)を示す図である。  FIG. 12a is a view showing a manufacturing process (No. 1) of an organic composite electronic device including a bottom-gate coplanar type organic thin film transistor according to a third embodiment.
[図 12b]第 3実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 2)を示す図である。  FIG. 12 b is a diagram showing a manufacturing process (No. 2) of the organic composite electronic device including the bottom gate coplanar type organic thin film transistor of the third embodiment.
[図 12c]第 3実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 3)を示す図である。  FIG. 12c is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the bottom-gate coplanar type organic thin film transistor of the third embodiment.
[図 12d]第 3実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 4)を示す図である。  FIG. 12d is a diagram showing a manufacturing step (No. 4) of the organic composite electronic device including the bottom gate ′ coplanar type organic thin film transistor of the third embodiment.
[図 12e]第 3実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 5)を示す図である。  FIG. 12e is a diagram showing a manufacturing process (No. 5) of the organic composite electronic device including the bottom gate ′ coplanar type organic thin film transistor of the third embodiment.
[図 12f]第 3実施形態のボトムゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 6)を示す図である。  FIG. 12f is a diagram showing a manufacturing step (No. 6) of the organic composite electronic device including the bottom gate ′ coplanar type organic thin film transistor of the third embodiment.
[図 13a]第 3実施形態のトップゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 1)を示す図である。  FIG. 13a is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including a top-gate staggered organic thin film transistor according to a third embodiment.
[図 13b]第 3実施形態のトップゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 2)を示す図である。  FIG. 13b is a diagram showing a manufacturing process (No. 2) of the organic composite electronic device including the top gate stagger type organic thin film transistor of the third embodiment.
[図 13c]第 3実施形態のトップゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 3)を示す図である。 [図 13d]第 3実施形態のトップゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 4)を示す図である。 FIG. 13c is a diagram showing a manufacturing process (No. 3) of the organic composite electronic device including the top-gate staggered organic thin film transistor of the third embodiment. FIG. 13d is a diagram showing a manufacturing process (No. 4) of the organic composite electronic device including the top-gate staggered organic thin film transistor of the third embodiment.
[図 13e]第 3実施形態のトップゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 5)を示す図である。  FIG. 13e is a diagram showing a manufacturing process (No. 5) of an organic composite electronic device including a top-gate staggered organic thin film transistor according to a third embodiment.
[図 13f]第 3実施形態のトップゲート'スタガー型の有機薄膜トランジスタを備える有機 複合電子素子の製造工程 (その 6)を示す図である。  FIG. 13f is a diagram showing a manufacturing process (No. 6) of an organic composite electronic device including the top-gate staggered organic thin film transistor of the third embodiment.
[図 14a]第 3実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 1)を示す図である。  FIG. 14a is a diagram showing a manufacturing process (No. 1) of an organic composite electronic device including a top gate coplanar type organic thin film transistor of a third embodiment.
[図 14b]第 3実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 2)を示す図である。  FIG. 14b is a diagram showing a manufacturing process (No. 2) of the organic composite electronic device including the top gate coplanar type organic thin film transistor of the third embodiment.
[図 14c]第 3実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 3)を示す図である。  FIG. 14c is a view showing a manufacturing process (No. 3) of the organic composite electronic device including the top gate coplanar type organic thin film transistor of the third embodiment.
[図 14d]第 3実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 4)を示す図である。  FIG. 14d is a diagram showing a manufacturing step (No. 4) of the organic composite electronic device including the top gate coplanar type organic thin film transistor of the third embodiment.
[図 14e]第 3実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 5)を示す図である。  FIG. 14e is a diagram showing a manufacturing process (No. 5) of the organic composite electronic device including the top gate coplanar type organic thin film transistor of the third embodiment.
[図 14f]第 3実施形態のトップゲート'コプレナ一型の有機薄膜トランジスタを備える有 機複合電子素子の製造工程 (その 6)を示す図である。  FIG. 14f is a diagram showing a manufacturing process (No. 6) of the organic composite electronic device including the top gate coplanar type organic thin film transistor of the third embodiment.
[図 15]第 3実施形態の強誘電体メモリセルの構成例を示す図である。  FIG. 15 is a diagram showing a configuration example of a ferroelectric memory cell according to a third embodiment.
[図 16]実施例におけるトランジスタ又は第 1トランジスタの VD— ID線図である。  FIG. 16 is a VD-ID diagram of the transistor or the first transistor in the example.
[図 17]実施例におけるトランジスタ又は第 1トランジスタの VG— ID線図である。  FIG. 17 is a VG-ID diagram of the transistor or the first transistor in the example.
[図 18]実施例における第 2トランジスタの VG— ID線図である。  FIG. 18 is a VG-ID diagram of the second transistor in the example.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0025] (1)第 1実施形態 [0025] (1) First embodiment
以下、第 1実施形態として、上述した本発明の第 1の観点に対応する有機薄膜トラ ンジスタ、その製造方法、及び表示装置について説明する。  Hereinafter, an organic thin film transistor, a manufacturing method thereof, and a display device corresponding to the first aspect of the present invention described above will be described as a first embodiment.
[0026] (1 1)有機薄膜トランジスタの全体構成 [0026] (1 1) Overall configuration of organic thin film transistor
本実施形態の有機薄膜トランジスタは、基板上に、有機半導体膜、ゲート電極、ソ ース電極、ドレイン電極、及びゲート絶縁膜を備えて構成される。ゲート絶縁膜は、低 誘電率の低誘電体膜と該低誘電体膜よりも高誘電率の強誘電体膜とを積層して二 層構造としたものである。有機薄膜トランジスタは、有機半導体膜に接したソース電極 とドレイン電極を有し、その上にゲート絶縁膜を介してゲート電極を有するトップグー ト型と、ゲート電極を有し、その上にゲート絶縁膜を介して有機半導体膜で連結され たソース電極とドレイン電極を有するボトムゲート型とに大別される。 The organic thin film transistor of this embodiment has an organic semiconductor film, a gate electrode, and a soot on a substrate. A source electrode, a drain electrode, and a gate insulating film. The gate insulating film has a two-layer structure in which a low dielectric constant low dielectric film and a ferroelectric film having a higher dielectric constant than the low dielectric film are stacked. An organic thin film transistor has a source electrode and a drain electrode in contact with an organic semiconductor film, and has a top gate type having a gate electrode via a gate insulating film thereon, a gate electrode, and a gate insulating film thereon It is roughly classified into a bottom gate type having a source electrode and a drain electrode connected by an organic semiconductor film through a via.
[0027] 本発明が適用可能な有機薄膜トランジスタは、トップゲート型のものであっても、ボト ムゲート型のものであっても良いが、ソース電極及びドレイン電極の形成による有機 半導体膜へのダメージを回避するという観点からは、ボトムゲート型のものが好ましいThe organic thin film transistor to which the present invention can be applied may be a top gate type or a bottom gate type. However, damage to the organic semiconductor film due to the formation of the source electrode and the drain electrode is prevented. From the viewpoint of avoidance, the bottom gate type is preferable.
Yes
[0028] 図 laはトップゲート'スタガー型 (Top Gate Stagger type)の有機薄膜トランジスタの 構成を示す図である。図 laに示す有機薄膜トランジスタは、基板 11上に下引き層 12 を有している。下引き層 12は、ポリマー、又は無機酸化物及び無機窒化物から選ば れる化合物を含有している。下引き層 12に接して有機半導体膜 16、ドレイン電極 14 及びソース電極 15が設けられている。有機半導体膜 16の上には、ゲート絶縁膜 17 を介してゲート電極 18が設けられている。ゲート絶縁膜 17は、低誘電体膜 17aと強 誘電体膜 17bとを積層して構成されている。低誘電体膜 17aは、有機半導体膜 16と 強誘電体膜 17bとの間に介装 ·配置されて!/、る。また最外層として保護膜 (封止膜) 2 3が設けられている。図 lbはドレイン電極及びソース電極と有機半導体膜の積層順 序を入れ替えたトップゲート'コプレナ一型 (Top Gate Coplanar type)の構成を示して いる。  [0028] FIG. La is a diagram showing a configuration of a top gate stagger type organic thin film transistor. The organic thin film transistor shown in FIG. La has an undercoat layer 12 on a substrate 11. The undercoat layer 12 contains a polymer or a compound selected from inorganic oxides and inorganic nitrides. An organic semiconductor film 16, a drain electrode 14, and a source electrode 15 are provided in contact with the undercoat layer 12. A gate electrode 18 is provided on the organic semiconductor film 16 via a gate insulating film 17. The gate insulating film 17 is formed by laminating a low dielectric film 17a and a ferroelectric film 17b. The low dielectric film 17a is disposed between the organic semiconductor film 16 and the ferroelectric film 17b. A protective film (sealing film) 23 is provided as the outermost layer. Figure lb shows the configuration of the top gate coplanar type with the drain electrode and the stacking order of the source electrode and the organic semiconductor film changed.
[0029] 図 2aは、ボトムゲート'スタガー型 (Bottom Gate Stagger type)の有機薄膜トランジス タの構成を示す図である。図 2aに示す有機薄膜トランジスタは、基板 11上に下引き 層 12を有している。下引き層 12は、ポリマー、又は無機酸化物及び無機窒化物から 選ばれる化合物を含有している。下引き層 12に接して、ゲート電極 18、及びゲート 絶縁膜 17を介して有機半導体膜 16が設けられている。ゲート絶縁膜 17は、低誘電 体膜 17aと強誘電体膜 17bとを積層して構成されている。低誘電体膜 17aは、有機 半導体膜 16と強誘電体膜 17bとの間に介装 ·配置されている。さらに有機半導体膜 16に接して、ドレイン電極 14及びソース電極 15が設けられている。図 2bはドレイン 電極及びソース電極と有機半導体膜の積層順序を入れ替えたボトムゲート'コプレナ 一型 (Bottom Gate Coplanar type)の構成を示している。 [0029] FIG. 2a is a diagram showing a configuration of an organic thin film transistor of a bottom gate stagger type (Bottom Gate Stagger type). The organic thin film transistor shown in FIG. 2 a has an undercoat layer 12 on a substrate 11. The undercoat layer 12 contains a polymer or a compound selected from inorganic oxides and inorganic nitrides. An organic semiconductor film 16 is provided in contact with the undercoat layer 12 via a gate electrode 18 and a gate insulating film 17. The gate insulating film 17 is formed by laminating a low dielectric film 17a and a ferroelectric film 17b. The low dielectric film 17a is interposed between the organic semiconductor film 16 and the ferroelectric film 17b. Further organic semiconductor film A drain electrode 14 and a source electrode 15 are provided in contact with 16. Figure 2b shows the configuration of the bottom gate coplanar type with the drain electrode and the stacking order of the source electrode and the organic semiconductor film changed.
[0030] (1 2)有機半導体膜及びその形成工程 (1 2) Organic semiconductor film and formation process thereof
有機半導体膜の形成には有機半導体材料が用いられる。有機半導体材料として は、 π共役系材料が挙げられる。 π共役系材料としては、例えばポリピロール、ポリ( Ν 置換ピロール)、ポリ(3—置換ピロール)、ポリ(3, 4—二置換ピロール)などのポ リピロール類;ポリチォフェン、ポリ(3—置換チォフェン)、ポリ(3, 4—二置換チオフ ェン)、ポリベンゾチォフェンなどのポリチォフェン類;ポリイソチアナフテンなどのポリ イソチアナフテン類;ポリチェ二レンビニレンなどのポリチェ二レンビニレン類;ポリ(ρ フエ二レンビニレン)などのポリ(ρ—フエ二レンビニレン)類;ポリア二リン、ポリ(Ν— 置換ァュリン)、ポリ(3—置換ァュリン)、ポリ(2, 3—置換ァュリン)などのポリア二リン An organic semiconductor material is used for forming the organic semiconductor film. Organic semiconductor materials include π-conjugated materials. Examples of π-conjugated materials include polypyrrole, poly (ピ substituted pyrrole), poly (3-substituted pyrrole), poly (3,4-disubstituted pyrrole), and the like; polythiophene, poly (3-substituted thiophene) Polythiophenes such as poly (3,4-disubstituted thiophene) and polybenzothiophene; Polyisothianaphthenes such as polyisothianaphthene; Polyethylene vinylenes such as polyphenylene vinylene; Poly (ρ vinylene) such as poly (.rho. phenylene vinylene) s; Poria diphosphate, poly (Nyu- substituted Ayurin), poly (3 - substituent Ayurin), poly (2, 3 - substituted Ayurin) Polya diphosphate such as
ノレ、ポリ(Ν 置換カルバゾール)などのポリ力ルバゾール類;ポリセレノフェンなどの ポリセレノフェン類;ポリフラン、ポリべンゾフランなどのポリフラン類;ポリ(ρ—フエユレ ン)などのポリ(ρ—フエ二レン)類;ポリインドールなどのポリインドール類;ポリピリダジ ンなどのポリピリダジン類;ナフタセン、ペンタセン、へキサセン、ヘプタセン、ジベン ゾペンタセン、テトラべンゾペンタセン、ピレン、ジベンゾピレン、タリセン、ペリレン、コ ロネン、テリレン、ォバレン、クオテリレン、サ一力ムアントラセンなどのポリアセン類;及 びポリアセン類の炭素の一部を N、 S、 Oなどの原子、カルボニル基などの官能基に 置換した誘導体(トリフエノジォキサジン、トリフエノジチアジン、へキサセン 6, 15 - キノンなど)、ポリビュルカルバゾール、ポリフエ二レンスルフイド、ポリビニレンスルフィ ドなどのポリマーや日本国特開平 11— 195790号公報に記載された多環縮合体な どを挙げること力 Sできる。 Poly rubazoles such as Nole and poly (Ν-substituted carbazole); Polyselenophenes such as polyselenophene; Polyfurans such as polyfuran and polybenzofuran; Poly (ρ-phenol) such as poly (ρ-phenol) Polyindoles such as polypyridazine; polypyridazines such as polypyridazine; naphthacene, pentacene, hexacene, heptacene, dibenzopentacene, tetrabenzopentacene, pyrene, dibenzopyrene, taricene, perylene, coronene, terylene, Derivatives (triphenodioxazines) in which a part of carbon of polyacene is substituted with an atom such as N, S, or O, or a functional group such as carbonyl group. , Triphenodithiazine, hexacene 6, 15-quinone, etc. , Poly Bulle carbazole, Porifue two Rensurufuido can be force S include etc. polycyclic a condensate described in the polymer and Japanese Patent Laid-Open 11-195790 discloses such polyvinylene sulfide.
[0031] また、これらのポリマーと同じ繰返し単位を有する、例えばチォフェン 6量体である [0031] Further, these polymers have the same repeating unit, for example, thiophene hexamer.
α—セクシチォフェン、 α , ω—ジへキシノレ α—セクシチォフェン、 α , ω—ジへ キシルー α—キンケチォフェン、 α , ω—ビス(3—ブトキシプロピル) α—セクシチ ォフェン、スチリルベンゼン誘導体などのオリゴマーが挙げられる。 α-seccithiophene, α, ω-dihexinole α-seccithiophene, α, ω-dihexoxyl α-kinchethiophene, α, ω-bis (3-butoxypropyl) α-sexuality Examples include oligomers such as ophene and styrylbenzene derivatives.
[0032] さらに、銅フタロシアニンや日本国特開平 11— 251601号公報に記載のフッ素置 換銅フタロシアニンなどの金属フタロシアニン類;ナフタレン 1 , 4, 5, 8—テトラカルボ ン酸ジイミド、 N, N, 一ビス(4 トリフルォロメチルベンジル)ナフタレン 1 , 4, 5, 8— テトラカルボン酸ジイミド、 N, N, 一ビス(1H, 1H—ペルフルォロォクチル)ナフタレ ン 1 , 4, 5, 8—テトラカルボン酸ジイミド、 N, N, 一ビス(1H, 1H—ペルフルォロブ チル)ナフタレン 1 , 4, 5, 8—テトラカルボン酸ジイミド及び N, N'—ジォクチルナフ タレン 1 , 4, 5, 8 テトラカルボン酸ジイミド、ナフタレン 2, 3, 6, 7 テトラカルボン 酸ジイミドなどのナフタレンテトラカルボン酸ジイミド類;及びアントラセン 2, 3, 6, 7— テトラカルボン酸ジイミドなどのアントラセンテトラカルボン酸ジイミド類などの縮合環 テトラカルボン酸ジイミド類; C60、 C70、 C76、 C78、 C84等のフラーレン類、 SWN Tなどのカーボンナノチューブ、メロシアニン色素類、へミシァニン色素類などの色素 などが挙げられる。 [0032] Further, metal phthalocyanines such as copper phthalocyanine and fluorine-substituted copper phthalocyanine described in Japanese Patent Application Laid-Open No. 11-251601; naphthalene 1, 4, 5, 8-tetracarboxylic acid diimide, N, N, Bis (4 trifluoromethylbenzyl) naphthalene 1, 4, 5, 8— Tetracarboxylic acid diimide, N, N, 1 bis (1H, 1H-perfluorooctyl) naphthalene 1, 4, 5, 8— Tetracarboxylic acid diimide, N, N, monobis (1H, 1H-perfluorobutyl) naphthalene 1, 4, 5, 8-tetracarboxylic acid diimide and N, N'-dioctylnaphthalene 1, 4, 5, 8 tetracarboxylic acid Naphthalene tetracarboxylic acid diimides such as diimide, naphthalene 2, 3, 6, 7 tetracarboxylic acid diimide; and anthracene tetracarboxylic acid such as anthracene 2, 3, 6, 7- tetracarboxylic acid diimide Fused ring tetracarboxylic acid diimides such as imides; C60, C70, C76, C78, fullerenes such as C84, carbon nanotube such as SWN T, merocyanine dyes, etc. dyes such Mishianin dyes and the like to.
[0033] これらの π共役系材料のうちでも、チォフェン、チェ二レンビニレン、フエ二レンビニ レン、 ρ—フエ二レン、及びこれらの置換体の少なくとも 1種を繰返し単位とし、かつ該 繰返し単位の数 ηが 4〜; 10であるオリゴマー並びに該繰返し単位の数 ηが 20以上で あるポリマー;ペンタセンなどの縮合多環芳香族化合物;フラーレン類;縮合環テトラ カルボン酸ジイミド類;並びに金属フタロシアニンよりなる群から選ばれた少なくとも 1 種が好ましい。  [0033] Among these π-conjugated materials, thiophene, chelenylene vinylene, phenylene vinylene, ρ-phenylene, and at least one of these substituents are repeating units, and the number of repeating units η is 4 to; an oligomer having 10 to 10 and a polymer having η of 20 or more; a condensed polycyclic aromatic compound such as pentacene; fullerenes; a condensed ring tetracarboxylic diimide; and a group consisting of metal phthalocyanines At least one selected from is preferred.
[0034] また、その他の有機半導体材料としては、テトラチアフノレバレン (TTF)—テトラシァ ノキノジメタン(TCNQ)錯体、ビスエチレンテトラチアフルバレン(BEDTTTF)—過 塩素酸錯体、 BEDTTTF ヨウ素錯体、 TCNQ ヨウ素錯体、などの有機分子錯体 力 S挙げられる。さらにポリシラン、ポリゲルマンなどの σ共役系ポリマーや日本国特開 2000— 260999号公報に記載の有機.無機混成材料が挙げられる。  [0034] Other organic semiconductor materials include tetrathiafunolevalene (TTF) -tetracyanoquinodimethane (TCNQ) complex, bisethylenetetrathiafulvalene (BEDTTTF) -perchloric acid complex, BEDTTTF iodine complex, TCNQ iodine complex Organic molecular complex such as Further examples include σ-conjugated polymers such as polysilane and polygermane, and organic / inorganic hybrid materials described in Japanese Unexamined Patent Publication No. 2000-260999.
[0035] 有機半導体膜には、例えば、アクリル酸、ァセトアミド、ジメチルァミノ基、シァノ基、 カルボキシル基、ニトロ基などの官能基を有する材料;ベンゾキノン誘導体、テトラシ ァノエチレン及びテトラシァノキノジメタンやそれらの誘導体などのように電子を受容 するァクセプターとなる材料;例えばアミノ基、トリフエニル基、アルキル基、水酸基、 アルコキシ基、フエニル基などの官能基を有する材料;フエ二レンジァミンなどの置換 アミン類、アントラセン、ベンゾアントラセン、置換べンゾアントラセン類、ピレン、置換 ピレン、力ルバゾール及びその誘導体、テトラチアフルバレンとその誘導体などのよう に電子の供与体であるドナーとなるような材料を含有させてもよい。 [0035] For the organic semiconductor film, for example, a material having a functional group such as acrylic acid, acetamido, dimethylamino group, cyano group, carboxyl group, nitro group; benzoquinone derivative, tetracyanethylene, tetracyanoquinodimethane and derivatives thereof Materials that accept electrons, such as amino groups, triphenyl groups, alkyl groups, hydroxyl groups, Materials having functional groups such as alkoxy groups and phenyl groups; substituted amines such as phenylenediamine, substituted amines, anthracene, benzoanthracene, substituted benzoanthracenes, pyrene, substituted pyrene, force rubazole and derivatives thereof, tetrathiafulvalene and its A material which becomes a donor which is an electron donor such as a derivative may be contained.
[0036] 有機半導体膜の成膜 (形成)法としては、真空蒸着法、分子線ェピタキシャル成長 法、イオンクラスタービーム法、低エネルギーイオンビーム法、イオンプレーティング 法、 CVD法、スパッタリング法、プラズマ重合法、電解重合法、化学重合法、スプレ 一コート法、スピンコート法、ブレードコート法、ディップコート法、キャスト法、ローノレコ ート法、バーコート法、ダイコート法及び LB法等が挙げられる。  [0036] Organic semiconductor film formation (formation) methods include vacuum deposition, molecular beam epitaxy, ion cluster beam, low energy ion beam, ion plating, CVD, sputtering, plasma Examples include a polymerization method, an electrolytic polymerization method, a chemical polymerization method, a spray coating method, a spin coating method, a blade coating method, a dip coating method, a casting method, a Rhino recording method, a bar coating method, a die coating method, and an LB method.
[0037] 有機半導体膜の膜厚は、用いられる有機半導体材料により異なるが、通常 1 μ m以 下、好ましくは一単分子層の厚み以上 400nm以下である。  [0037] The thickness of the organic semiconductor film varies depending on the organic semiconductor material to be used, but is usually 1 µm or less, preferably from a monolayer thickness to 400 nm.
[0038] (1 3)電極及びその形成工程  [0038] (1 3) Electrode and formation process thereof
有機薄膜トランジスタを構成する各電極 (ゲート電極、ソース電極及びドレイン電極 )は、導電性材料で形成される。導電性材料としては、例えば、白金、金、銀、ニッケ ル、クロム、銅、鉄、錫、アンチモン鉛、タンタル、インジウム、パラジウム、テルル、レ 二ゥム、イリジウム、アルミニウム、ルテニウム、ゲルマニウム、モリブデン、タングステン 、酸化スズ ·アンチモン、酸化インジウム'スズ (ITO)、フッ素ドープ酸化亜鉛、亜鉛、 炭素、グラフアイト、グラッシ一カーボン、銀ペースト及びカーボンペースト、リチウム、 ベリリウム、マグネシウム、カリウム、カルシウム、スカンジウム、チタン、マンガン、ジル コユウム、ガリウム、ニオブ、ナトリウム、ナトリウム—カリウム合金、マグネシウム/銅混 合物、マグネシウム/銀混合物、マグネシウム/アルミニウム混合物、マグネシウム/ インジウム混合物、アルミニウム/酸化アルミニウム混合物、リチウム/アルミニウム混 合物等が挙げられる。またドーピング等で導電率を向上させた公知の導電性ポリマ 一、例えば導電性ポリア二リン、導電性ポリピロール、導電性ポリチォフェン (ポリェチ レンジォキシチォフェンとポリスチレンスルホン酸の錯体など)が挙げられる。  Each electrode (gate electrode, source electrode and drain electrode) constituting the organic thin film transistor is formed of a conductive material. Examples of conductive materials include platinum, gold, silver, nickel, chromium, copper, iron, tin, antimony lead, tantalum, indium, palladium, tellurium, rhenium, iridium, aluminum, ruthenium, germanium, and molybdenum. , Tungsten, tin oxide / antimony, indium tin oxide (ITO), fluorine-doped zinc oxide, zinc, carbon, graphite, glassy carbon, silver paste and carbon paste, lithium, beryllium, magnesium, potassium, calcium, scandium, Titanium, manganese, zirconium oxide, gallium, niobium, sodium, sodium-potassium alloy, magnesium / copper mixture, magnesium / silver mixture, magnesium / aluminum mixture, magnesium / indium mixture, aluminum / aluminum oxide Compound, and lithium / aluminum mixed compounds and the like. Further, known conductive polymers whose conductivity has been improved by doping or the like, for example, conductive polyaniline, conductive polypyrrole, or conductive polythiophene (polyethylene dioxythiophene and polystyrene sulfonic acid complex, etc.) can be mentioned.
[0039] 特に、ソース電極及びドレイン電極を形成する材料は、上に挙げた中で有機半導 体膜との接触面において電気抵抗が少ないものが好ましぐ p型半導体の場合は、 特に、白金、金、銀、 ITO、導電性ポリマー及び炭素が好ましい。 [0040] これらのゲート電極、ソース電極及びドレイン電極としては、上記の導電性材料を含 む、溶液、ペースト、インク、分散液などの流動性電極材料を用いて形成したもの、特 に、導電性ポリマー、又は白金、金、銀、銅を含有する金属微粒子を含む流動性電 極材料を用いて形成したものが好まし!/、。 [0039] In particular, the material for forming the source electrode and the drain electrode is preferably a p-type semiconductor having a low electrical resistance at the contact surface with the organic semiconductor film among the materials listed above. Platinum, gold, silver, ITO, conductive polymer and carbon are preferred. [0040] The gate electrode, the source electrode, and the drain electrode are formed using a fluid electrode material such as a solution, paste, ink, or dispersion liquid containing the above-described conductive material. It is preferable to use a conductive polymer or a fluid electrode material containing fine metal particles containing platinum, gold, silver and copper!
[0041] 金属微粒子を含有する流動性電極材料としては、例えば公知の導電性ペーストな どを用いても良いが、好ましくは、平均粒子径が l〜50nm、好ましくは 1〜; !Onmの 金属微粒子を、必要に応じて分散安定剤を用いて、水や任意の有機溶剤である分 散媒中に分散した材料を用いる。平均粒子径は光子相関法により測定することがで きる。  [0041] As the fluid electrode material containing fine metal particles, for example, a known conductive paste may be used. Preferably, the average particle size is 1 to 50 nm, preferably 1 to; A material in which fine particles are dispersed in water or a dispersion medium that is an arbitrary organic solvent using a dispersion stabilizer as required is used. The average particle size can be measured by a photon correlation method.
[0042] 金属微粒子の材料としては、前記した白金、金、銀、銅の他、ニッケル、クロム、鉄、 錫、アンチモン鉛、タンタル、インジウム、パラジウム、テルル、レニウム、イリジウム、ァ ルミユウム、ルテニウム、ゲルマニウム、モリブデン、タングステン、亜鉛等であってもよ い。  [0042] In addition to platinum, gold, silver and copper, nickel, chromium, iron, tin, antimony lead, tantalum, indium, palladium, tellurium, rhenium, iridium, aluminum, ruthenium, Germanium, molybdenum, tungsten, zinc, etc. may be used.
[0043] このような金属微粒子の分散物の製造方法として、ガス中蒸発法、スパッタリング法 、金属蒸気合成法などの物理的生成法や、コロイド法、共沈法などの、液相で金属ィ オンを還元して金属微粒子を生成する化学的生成法が挙げられる。これらの金属微 粒子分散物を用いて電極を成形し、溶媒を乾燥させた後、必要に応じて 100〜300 °C、好ましくは 150〜200°Cの範囲で加熱することにより、金属微粒子を熱融着させ 、 目的の形状を有する電極パターンを形成するものである。  [0043] As a method for producing such a dispersion of metal fine particles, a metal phase in a liquid phase such as a physical production method such as a gas evaporation method, a sputtering method or a metal vapor synthesis method, a colloid method or a coprecipitation method is used. There is a chemical production method in which metal fine particles are produced by reducing ON. After forming an electrode using these metal fine particle dispersions and drying the solvent, the metal fine particles are formed by heating in the range of 100 to 300 ° C, preferably 150 to 200 ° C as necessary. An electrode pattern having a desired shape is formed by heat fusion.
[0044] 電極の形成方法としては、前記導電性材料を原料としてスパッタリングや蒸着など により導電性薄膜を形成し、次いでフォトレジストでパターンを形成した後にエツチン グにより不要な薄膜を除去して電極パターンを形成するフォトリソグラフ法;基板上に メタルマスクを置いて、そのままスパッタリングや蒸着を行い、電極パターンを形成す るメタルマスク法;アルミニウムや銅などの金属箔上に熱転写やインクジェット等により フォトレジストのパターンを形成した後にエッチングにより不要な薄膜を除去して電極 ノ ターンを形成する方法などの公知の方法が挙げられる。また導電性ポリマーの溶 液あるいは分散液、金属微粒子を含有する分散液等を直接インクジェット法によりパ ターニングしてもよいし、塗工膜からリソグラフやレーザーアブレーシヨンなどにより形 成してもよい。さらに導電性ポリマーや金属微粒子を含有する導電性インク、導電性 ペーストなどを凸版、凹版、平版、スクリーン印刷などの印刷法でパターユングする方 法も用いること力できる。電極の厚さは特に限定されないが、通常 20〜500nm、好 ましくは 50〜200應である。 [0044] As a method for forming an electrode, a conductive thin film is formed by sputtering or vapor deposition using the conductive material as a raw material, and then a pattern is formed with a photoresist, and then an unnecessary thin film is removed by etching to form an electrode pattern. Photolithographic method to form an electrode; metal mask method on which a metal mask is placed on a substrate, and sputtering or vapor deposition is performed as it is to form an electrode pattern; a photoresist film is formed on a metal foil such as aluminum or copper by thermal transfer or ink jet There are known methods such as a method of forming an electrode pattern by removing an unnecessary thin film by etching after forming a pattern. In addition, a solution or dispersion of a conductive polymer, a dispersion containing metal fine particles, or the like may be directly patterned by an ink jet method, or may be formed from a coating film by lithograph or laser abrasion. You may make it. Furthermore, it is also possible to use a method of patterning conductive inks or conductive pastes containing conductive polymers and metal fine particles by printing methods such as relief printing, intaglio printing, lithographic printing, and screen printing. The thickness of the electrode is not particularly limited, but is usually 20 to 500 nm, preferably 50 to 200.
[0045] (1 4)絶縁膜及びその形成工程  (14) Insulating film and formation process thereof
ゲート絶縁膜は、比較的に低い誘電率を有する低誘電体膜、及び比較的に高い誘 電率を有する強誘電体膜 (高誘電体膜)を積層した二層構造の膜である。但し、本実 施形態では、二層構造のゲート絶縁膜について説明する力 本発明の目的を阻害し ない範囲内で、ゲート絶縁膜は、二層以上の多層構造の膜であってもよい。この有機 薄膜トランジスタにおいては、低誘電体膜は有機半導体膜に接するように、強誘電体 膜はゲート電極に接するように、それぞれ形成するのが好適である。  The gate insulating film is a film having a two-layer structure in which a low dielectric film having a relatively low dielectric constant and a ferroelectric film (high dielectric film) having a relatively high dielectric constant are stacked. However, in the present embodiment, the power to explain the gate insulating film having a two-layer structure may be a film having a multilayer structure of two or more layers within a range not impairing the object of the present invention. In this organic thin film transistor, it is preferable that the low dielectric film is formed in contact with the organic semiconductor film, and the ferroelectric film is formed in contact with the gate electrode.
[0046] 低誘電体膜の比誘電率は、通常、 4以下の値に設定され、 3. 5以下の値で設定さ れること力 S好ましく、 3以下の値で設定されることがより好ましい。比誘電率の下限とし ては、通常、 2程度である。低誘電体膜の膜厚は、好ましくは 5nm〜500nm、より好 ましくは 10nm〜300nmに設定される。強誘電体膜の比誘電率は、通常、 5以上の 値に設定され、 7以上の値で設定されることが好ましぐ 10以上の値で設定されること 力 り好ましい。比誘電率の上限としては、通常、 50程度である。強誘電体膜の膜厚 は、好ましくは 5nm〜500nm、より好ましくは 10nm〜300nmに設定される。低誘電 体膜の比誘電率及び膜厚と、強誘電体膜の比誘電率及び膜厚を適宜に設定するこ とにより、ゲート絶縁膜全体としての有効誘電率を調節することができる。低誘電体膜 と強誘電体膜を積層したゲート絶縁膜全体としての膜厚は、絶縁性が保たれれば!/、 かなる厚さを用いてもよいが、一般に好適に用いられるのは、 10〜500nm、より好ま しくは 10〜300nmである。有機薄膜トランジスタ素子のサイズの微小化に従って、で きるだけ薄くするのが望ましレ、。  [0046] The relative dielectric constant of the low dielectric film is normally set to a value of 4 or less, and is preferably set to a value of 3.5 or less. Force S is preferable, and is more preferably set to a value of 3 or less. . The lower limit of the dielectric constant is usually around 2. The film thickness of the low dielectric film is preferably set to 5 nm to 500 nm, more preferably 10 nm to 300 nm. The relative dielectric constant of the ferroelectric film is normally set to a value of 5 or more, and is preferably set to a value of 7 or more, and is preferably set to a value of 10 or more. The upper limit of the relative dielectric constant is usually about 50. The film thickness of the ferroelectric film is preferably set to 5 nm to 500 nm, more preferably 10 nm to 300 nm. The effective dielectric constant of the entire gate insulating film can be adjusted by appropriately setting the relative dielectric constant and film thickness of the low dielectric film and the relative dielectric constant and film thickness of the ferroelectric film. The total thickness of the gate insulating film formed by laminating the low dielectric film and the ferroelectric film may be any thickness as long as the insulating property is maintained. 10 to 500 nm, more preferably 10 to 300 nm. It is desirable to make it as thin as possible as the size of organic thin-film transistor elements becomes smaller.
[0047] (1 4 1)低誘電体膜  [0047] (1 4 1) Low dielectric film
ゲート絶縁膜を構成する低誘電体膜は、非共有電子対を有する官能基を持たず且 つ分子構造内に兀電子結合を持たない有機高分子化合物を含んでなる膜である。 ここで、「官能基」とは有機高分子化合物の主鎖の骨格構造の形成に関与していな い、主鎖に結合し主鎖から分枝した原子団をレ、う。 The low dielectric film constituting the gate insulating film is a film containing an organic polymer compound that does not have a functional group having an unshared electron pair and does not have a negative electron bond in the molecular structure. Here, the “functional group” is not involved in the formation of the skeleton structure of the main chain of the organic polymer compound. The atomic group that is bonded to the main chain and branched off from the main chain.
[0048] ここで、非共有電子対とは、原子の最外郭電子のうち、他の原子との結合にあずか らないで、二つずつ対になっている電子である。孤立電子対や非結合電子対とも呼 ばれるものである。本実施形態において非共有電子対を有する官能基は、主鎖に結 合し主鎖から分枝した基であり、主鎖自体が基となっているものを含まない。例えば ポリオキシエチレンのごとく主鎖自体にエーテル基( O )がある場合のエーテル 基や、ポリアミンのごとく主鎖自体にイミノ基(〉NH)が在る場合のイミノ基は非共有 電子対を有する官能基に含まれない。ポリアクリロニトリルのごとき主鎖に結合した二 トリル基が有る場合の二トリル基や、ポリテトラフルォロエチレンのごとき主鎖に結合し たフッ素基がある場合のフッ素基は非共有電子対を有する官能基に含まれる。  [0048] Here, the unshared electron pair is an electron that is paired with two of the outermost electrons of the atom without involving a bond with another atom. It is also called a lone pair or a non-bonded pair. In this embodiment, the functional group having an unshared electron pair is a group bonded to the main chain and branched from the main chain, and does not include those based on the main chain itself. For example, an ether group in the case where the main chain itself has an ether group (O) such as polyoxyethylene, and an imino group in the case where the main chain itself exists in the main chain itself such as polyamine has an unshared electron pair. Not included in the functional group. A nitrile group having a nitrile group bonded to the main chain such as polyacrylonitrile or a fluorine group having a fluorine group bonded to the main chain such as polytetrafluoroethylene has an unshared electron pair. Included in functional group.
[0049] π電子結合とは、 π軌道に属する電子によってつくられる結合をいう。 π軌道とは、 分子内の電子を収容する軌道の一種であり、ひとつの結合の原子核を結ぶ軸(結合 軸)に対して、垂直な方向に分布を有する軌道同士が分子面の上下でそれぞれ横 方向に重なってつくる電子軌道である。 π電子結合を有する結合の具体例としては、 炭素 炭素間の二重結合及び三重結合、窒素と炭素間の三重結合、炭素と酸素間 の二重結合、ベンゼンやナフタレンの二重結合などが挙げられる。  [0049] A π-electron bond is a bond formed by electrons belonging to a π orbit. A π orbital is a type of orbit that accommodates electrons in a molecule, and orbitals that are distributed in a direction perpendicular to the axis connecting the nuclei of one bond (bonding axis) are above and below the molecular plane. It is an electron orbit created by overlapping in the horizontal direction. Specific examples of bonds having a π-electron bond include carbon-carbon double bonds and triple bonds, nitrogen-carbon triple bonds, carbon-oxygen double bonds, and benzene and naphthalene double bonds. It is done.
[0050] 低誘電体膜に含まれる有機高分子化合物は、上記のような、非共有電子対を有す る官能基を持たず且つ分子構造内に兀電子結合を持たない化合物である。かかる 化合物はいずれも本発明の所望の効果を奏し得る。本実施形態に使用する有機高 分子化合物は比誘電率が小さぐ通常、 3以下である。なお、本実施形態において、 比誘電率は LCRメーター(アジレントテクノロジ一社製、品番 4284Α)を用いた容量 法により測定することができる。このような有機高分子化合物としては、ポリエチレン、 ポリプロピレン、ポリブテンなどのポリオレフイン;脂環式ォレフインポリマー;ポリアミン ;ポリエーテル;などが挙げられる。これらのうち、誘電率の周波数依存性が小さいと いう観点から脂環式ォレフインポリマーが好適である。  [0050] The organic polymer compound contained in the low dielectric film is a compound that does not have a functional group having an unshared electron pair and does not have a negative electron bond in the molecular structure as described above. Any of these compounds can achieve the desired effects of the present invention. The organic high molecular compound used in this embodiment has a small relative dielectric constant and is usually 3 or less. In this embodiment, the relative dielectric constant can be measured by a capacitance method using an LCR meter (manufactured by Agilent Technologies, part number 4284Α). Examples of such organic polymer compounds include polyolefins such as polyethylene, polypropylene, and polybutene; alicyclic polyolefin polymers; polyamines; polyethers; Of these, alicyclic polyolefin polymers are preferred from the viewpoint that the frequency dependence of the dielectric constant is small.
[0051] 脂環式ォレフインポリマーは、主鎖及び/又は側鎖にシクロアルカン構造を有する 重合体である。機械的強度や耐熱性などの観点から、主鎖にシクロアルカン構造を 含有する重合体が好適である。また、シクロアルカン構造としては、単環や多環 (縮 合多環、橋架け環など)が挙げられる。シクロアルカン構造の一単位を構成する炭素 原子数は、格別な制限はないが、通常 4〜30個、好ましくは 5〜20個、より好ましくは 5〜; 15個の範囲であるときに、機械的強度、耐熱性、及び成形性の諸特性が高度に ノ ランスされ好適である。また、本実施形態で使用される脂環式ォレフインポリマーは 、通常、熱可塑性の樹脂である。 [0051] The alicyclic olefin polymer is a polymer having a cycloalkane structure in the main chain and / or side chain. From the viewpoint of mechanical strength and heat resistance, a polymer containing a cycloalkane structure in the main chain is preferred. Cycloalkane structures can be monocyclic or polycyclic (condensed). Multi-rings, bridge rings, etc.). The number of carbon atoms constituting one unit of the cycloalkane structure is not particularly limited, but is usually 4 to 30, preferably 5 to 20, more preferably 5 to 15; Various characteristics such as mechanical strength, heat resistance, and moldability are highly known and suitable. In addition, the alicyclic olefin polymer used in the present embodiment is usually a thermoplastic resin.
[0052] 脂環式ォレフインポリマーは、通常、シクロアルカン構造を有する繰り返し単位を脂 環式ォレフインポリマーの主鎖における全繰り返し単位中に通常 30〜; 100重量%、 好ましくは 50〜100重量。 /0、より好ましくは 70〜; 100重量%有する。シクロアルカン 構造を有する繰り返し単位の割合がこれらの範囲にあれば耐熱性に優れる。 [0052] In the alicyclic olefin polymer, the repeating unit having a cycloalkane structure is usually 30 to 100% by weight in all the repeating units in the main chain of the alicyclic olefin polymer, preferably 50 to 50%. 100 weight. / 0 , more preferably from 70 to 100% by weight. If the ratio of the repeating unit having a cycloalkane structure is within these ranges, the heat resistance is excellent.
[0053] 脂環式ォレフインポリマーは、通常、環構造を有するォレフィンを付加重合又は開 環重合し、そして必要に応じて不飽和結合部分及び芳香環部分を水素化することに よって得られる。  [0053] The alicyclic olefin polymer is usually obtained by addition polymerization or ring-opening polymerization of olefin having a ring structure, and hydrogenating the unsaturated bond portion and the aromatic ring portion as necessary. .
[0054] 脂環式ォレフインポリマーを得るために使用される環構造を有するォレフィンとして は、ノルボルネン、ジシクロペンタジェン、テトラシクロドデセン、ェチルテトラシクロド デセン、ェチリデンテトラシクロドデセン、テトラシクロ〔7· 4. 0. 110, 13. 02, 7〕トリ デカー 2, 4, 6, 11ーテトラェンなどの多環構造の不飽和炭化水素及びその誘導体 ;シクロブテン、シクロペンテン、シクロへキセン、 3, 4—ジメチルシクロペンテン、 3— メチノレシクロへキセン、 2 (2—メチノレブチノレ) 1ーシクロへキセン、シクロオタテン 、 3a, 5, 6, 7a—テトラヒドロー 4、 7—メタノー 1H—インデン、シクロヘプテン、シクロ ペンタジェン、シクロへキサジェンなどの単環構造の不飽和炭化水素及びその誘導 体;スチレン、 α—メチルスチレン、ジビュルベンゼンなどの芳香族ビュル化合物;ビ ニノレシクロへキサン、ビニノレシクロへキセン、ビニノレシクロペンタン、ビニノレシクロペン テンなどの脂環族ビュル化合物等が挙げられる。環構造を有するォレフィンは、それ ぞれ単独で、あるレ、は 2種以上を組み合わせて用いることができる。  [0054] Olefins having a ring structure used to obtain an alicyclic olefin polymer include norbornene, dicyclopentagen, tetracyclododecene, ethyltetracyclododecene, and ethylidenetetracyclodone. Decene, tetracyclo [7 · 4.0.110, 13. 02, 7] trideca 2, 4, 6, 11-tetracene unsaturated hydrocarbons and their derivatives; cyclobutene, cyclopentene, cyclohexene, 3,4-Dimethylcyclopentene, 3-Methylenocyclohexene, 2 (2-Methylolebutinole) 1-Cyclohexene, Cyclooctene, 3a, 5, 6, 7a-Tetrahydro-4, 7-methanol 1H-indene, cycloheptene, cyclopentagen, cyclo Monocyclic unsaturated hydrocarbons such as hexagen and derivatives thereof; styrene, α-methylstyrene, dibi Aromatic Bulle compounds such Rubenzen; hexane bi Ninoreshikuro, hexene Bininoreshikuro, vinyl Honoré cyclopentane, alicyclic Bulle compounds such as vinyl Honoré cyclopentene, and the like. Olefins having a ring structure can be used alone or in combination of two or more.
[0055] 環構造を有するォレフィンと共重合可能な単量体を必要に応じて付加共重合させ ること力 Sできる。そのような単量体の具体例として、エチレン、プロピレン、 1ーブテン、 1—ペンテン、 1—へキセン、 3—メチル 1—ブテン、 3—メチル 1—ペンテン、 3— ェチルー 1 ペンテン、 4ーメチルー 1 ペンテン、 4ーメチルー 1一へキセン、 4, 4 ジメチルー 1一へキセン、 4, 4 ジメチルー 1 ペンテン、 4ーェチルー 1一へキセ ン、 3—ェチル 1—へキセン、 1—オタテン、 1—デセン、 1—ドデセン、 1—テトラデ セン、 1一へキサデセン、 1ーォクタデセン、 1 エイコセンなどの炭素数 2〜20のェ チレン又は α—ォレフイン; 1 , 4一へキサジェン、 4ーメチルー 1 , 4一へキサジェン、 5—メチルー 1 , 4一へキサジェン、 1 , 7—ォクタジェンなどの非共役ジェン;1 , 3— ブタジエン、イソプレンなどの共役ジェン等が挙げられる。これらの単量体は、それぞ れ単独で、ある!/、は 2種以上を組み合わせて使用することができる。 [0055] It is possible to perform addition copolymerization of a monomer copolymerizable with olefin having a ring structure, if necessary. Specific examples of such monomers include ethylene, propylene, 1-butene, 1-pentene, 1-hexene, 3-methyl 1-butene, 3-methyl 1-pentene, 3-ethylyl 1 pentene, 4-methyl 1 Pentene, 4-methyl-one hexene, 4, 4 Dimethyl 1-hexene, 4, 4 Dimethyl-1 pentene, 4-ethyl 1-hexene, 3-ethyl 1-hexene, 1-octene, 1-decene, 1-dodecene, 1-tetradecene, 1 monohexadecene , 1-octadecene, 1 eicosene, etc., C 2-20 ethylene or α-olefin; 1, 4 monohexagen, 4-methyl-1, 4 monohexagen, 5-methyl-1, 4 monohexagen, 1, 7 —Non-conjugated gens such as octagen; 1,3-Conjugated gens such as butadiene and isoprene. These monomers can be used alone or in combination of two or more.
[0056] 環構造を有するォレフィンの重合は公知の方法に従って行うことができる。重合温 度、圧力等は特に限定されないが、通常 50°C〜; 100°Cの重合温度、 0〜5MPaの 重合圧力で重合させる。水素化反応は、公知の水素化触媒の存在下で、水素を吹き 込んで行う。 [0056] Polymerization of olefin having a ring structure can be carried out according to a known method. The polymerization temperature, pressure and the like are not particularly limited, but the polymerization is usually carried out at a polymerization temperature of 50 ° C to 100 ° C and a polymerization pressure of 0 to 5 MPa. The hydrogenation reaction is carried out by blowing hydrogen in the presence of a known hydrogenation catalyst.
[0057] 脂環式ォレフインポリマーの具体例としては、ノルボルネン系単量体の開環重合体 の水素化物、ノルボルネン系単量体の付加重合体及びその水素化物、ノルボルネン 系単量体とビュル化合物(エチレンや、 α—ォレフインなど)との付加重合体及びそ の水素化物、単環シクロアルケンの重合体及びその水素化物、脂環式共役ジェン系 単量体の重合体及びその水素化物、ビュル脂環式炭化水素系単量体の重合体及 びその水素化物、芳香族ビュル化合物の重合体の芳香環を水素化した物などが挙 げられる。これらの中でも、ノルボルネン系単量体の開環重合体の水素化物、ノルボ ルネン系単量体の付加重合体、ノルボルネン系単量体とビュル化合物(エチレンや a一才レフインなど)との付加重合体、芳香族ォレフイン重合体の芳香環水素化物が 好ましぐ特にノルボルネン系単量体の開環重合体の水素化物が好ましい。前記の 脂環式ォレフインポリマーは、それぞれ単独で、あるいは 2種以上を組み合わせて用 いること力 Sできる。なお、ここでノルボルネン系単量体とは化 1に示すようなノルボルネ ン構造を有する単量体のことである。ノルボルネン系単量体を開環重合すると化 2の ような繰り返し単位を持つポリマーが得られ、これを水素化すると化 3に示すような繰 り返し単位を持つポリマーが得られる。  [0057] Specific examples of the alicyclic olefin polymer include a hydride of a ring-opening polymer of a norbornene monomer, an addition polymer of a norbornene monomer and a hydride thereof, and a norbornene monomer. Addition polymers with butyl compounds (ethylene, α-olefin, etc.) and their hydrides, polymers of monocyclic cycloalkenes and their hydrides, polymers of alicyclic conjugation monomers and their hydrides Examples thereof include polymers of bullyalicyclic hydrocarbon monomers and their hydrides, and hydrogenated aromatic rings of polymers of aromatic bur compounds. Among these, hydrides of ring-opening polymers of norbornene monomers, addition polymers of norbornene monomers, addition weights of norbornene monomers and bur compounds (such as ethylene and a 1-year-old refin). Preferred are aromatic ring hydrides of polymers and aromatic olefin polymers, particularly hydrides of ring-opening polymers of norbornene monomers. The above alicyclic olefin polymers can be used singly or in combination of two or more. Here, the norbornene monomer is a monomer having a norbornene structure as shown in Chemical Formula 1. When the norbornene monomer is ring-opening polymerized, a polymer having a repeating unit as shown in Chemical Formula 2 is obtained, and when this is hydrogenated, a polymer having a repeating unit as shown in Chemical Formula 3 is obtained.
[0058] [化 1] [0058] [Chemical 1]
Figure imgf000022_0001
Figure imgf000022_0001
[0059] [化 2] [0059] [Chemical 2]
§^0060 § ^ 0060
Figure imgf000023_0001
Figure imgf000023_0001
Figure imgf000024_0001
Figure imgf000024_0001
[0061] 但し、化 3中の Rl及び R2は、非共有電子対を有さず且つ π電子結合の無い置換 基を示し、 R1と R2とが結合して環を形成してもよい。化 1及び化 2中の R1及び R2は 、種々の製造工程を経て、最終的に得られる脂環式ォレフインポリマーが非共有電 子対を有する官能基を持たず且つ π電子結合を持たないものになるのであれば、特 に制限されないが、好ましくは、非共有電子対を有さず且つ π電子結合の無い置換 基を示し、 R1と R2とが結合して環を形成してもよい。 [0061] However, Rl and R2 in Chemical Formula 3 represent a substituent having no unshared electron pair and having no π-electron bond, and R1 and R2 may be bonded to form a ring. R1 and R2 in Chemical Formula 1 and Chemical Formula 2 are subjected to various production processes, and the finally obtained alicyclic olefin polymer does not have a functional group having an unshared electron pair and has a π-electron bond. Is not particularly limited, but preferably represents a substituent having no unshared electron pair and no π-electron bond, and R1 and R2 may be bonded to form a ring. Good.
[0062] 本実施形態に用いる脂環式ォレフインポリマーは、その分子量によって特に制限さ れない。脂環式ォレフインポリマーの分子量は、シクロへキサンを溶媒とするゲルパ 一ミエーシヨンクロマトグラフィー (GPC)で測定されるポリスチレン換算の重量平均分 子量(Mw)で、通常 1 , 000—1 , 000, 000、好まし <は 5, 000—500, 000、より好 ましくは 10, 000— 250, 000の範囲である。脂環式ォレフインポリマーの重量平均 分子量 (Mw)がこの範囲にあるときには、耐熱性、接着性、表面平滑性などがバラン スされ好適である。 [0063] 脂環式ォレフインポリマーの分子量分布は、シクロへキサンを溶媒とする GPCで測 定される重量平均分子量(Mw)と数平均分子量(Mn)との比(Mw/Mn)で、通常 5 以下、好ましくは 4以下、より好ましくは 3以下である。脂環式ォレフインポリマーのガラ ス転移温度は、好ましくは 70°C以上、より好ましくは 120°C以上、最も好ましくは 140 °C以上である。なお、ガラス転移温度は示差走査熱量計により測定することができる[0062] The alicyclic olefin polymer used in the present embodiment is not particularly limited by the molecular weight. The molecular weight of an alicyclic olefin polymer is a polystyrene-equivalent weight average molecular weight (Mw) measured by gel permeation chromatography (GPC) using cyclohexane as a solvent, and is usually 1,000— 1, 000,000, preferably <is in the range of 5,000-500,000, more preferably in the range of 10,000-250,000. When the weight average molecular weight (Mw) of the alicyclic olefin polymer is in this range, heat resistance, adhesiveness, surface smoothness and the like are balanced, which is preferable. [0063] The molecular weight distribution of the alicyclic olefin polymer is the ratio (Mw / Mn) of the weight average molecular weight (Mw) and the number average molecular weight (Mn) measured by GPC using cyclohexane as a solvent. Usually, it is 5 or less, preferably 4 or less, more preferably 3 or less. The glass transition temperature of the alicyclic olefin polymer is preferably 70 ° C or higher, more preferably 120 ° C or higher, and most preferably 140 ° C or higher. The glass transition temperature can be measured with a differential scanning calorimeter.
Yes
[0064] 低誘電体膜には、本発明の所望の効果の発現が阻害されない範囲であれば、非 共有電子対を有する官能基を持たず且つ分子構造内に 71電子結合を持たなレ、有 機高分子化合物の他、その他の公知の有機高分子化合物が含まれて!/、てもよ!/、。 非共有電子対を有する官能基を持たず且つ分子構造内に 71電子結合を持たなレヽ 有機高分子化合物のゲート絶縁膜中の含有量としては、好ましくは 70〜; 100重量% [0064] The low dielectric film has no functional group having an unshared electron pair and has 71 electronic bonds in the molecular structure as long as expression of the desired effect of the present invention is not inhibited. In addition to organic polymer compounds, other known organic polymer compounds are included! The content of the organic polymer compound in the gate insulating film that does not have a functional group having an unshared electron pair and has 71 electronic bonds in the molecular structure is preferably 70 to 100% by weight
、より好ましくは 90〜; 100重量%である。また、その他、顔料や染料のごとき着色剤、 蛍光増白剤、分散剤、熱安定剤、光安定剤、紫外線吸収剤、耐電防止剤、酸化防 止剤、滑剤、溶剤などの配合剤を適宜配合したものであってもよい。 , More preferably 90 to 100% by weight. In addition, colorants such as pigments and dyes, optical brighteners, dispersants, heat stabilizers, light stabilizers, UV absorbers, antistatic agents, antioxidants, lubricants, solvents, and other compounding agents are used as appropriate. You may mix | blend.
[0065] 低誘電体膜の成膜 (形成)方法としては、真空蒸着法、分子線ェピタキシャル成長 法、イオンクラスタービーム法、低エネルギーイオンビーム法、イオンプレーティング 法、 CVD法、スパッタリング法、プラズマ重合法、電解重合法、化学重合法、スプレ 一コート法、スピンコート法、ブレードコート法、ディップコート法、キャスト法、ローノレコ ート法、バーコート法、ダイコート法及び LB法等が挙げられる。これらのうち、湿式法 が好ましい。湿式法とは、低誘電体膜を構成する前記の有機高分子化合物及び所 望により前記配合剤を溶媒に溶かし溶液を得、該溶液を流延させた後、溶媒を除去 し、成膜する方法である。使用する溶媒は、使用する有機高分子化合物等に応じて 公知の溶媒から適宜選択すればよい。湿式法としては、例えば、スピンコート法、ブ レードコート法、ディップコート法、ロールコート法、バーコート法、ダイコート法、スクリ ーン印刷法、インクジェット印刷法等が挙げられる。また、マイクロコンタクトプリンティ ング、マイクロモルディングなどのソフトリソグラフィ一と呼ばれる印刷法などを適応す ることもできる。これらの湿式法のうち、スピンコート法が特に好ましい。  [0065] Low dielectric film formation (formation) methods include vacuum deposition, molecular beam epitaxy, ion cluster beam, low energy ion beam, ion plating, CVD, sputtering, Examples include plasma polymerization method, electrolytic polymerization method, chemical polymerization method, spray coating method, spin coating method, blade coating method, dip coating method, casting method, Rhino recording method, bar coating method, die coating method and LB method. . Of these, the wet method is preferred. In the wet method, the organic polymer compound constituting the low dielectric film and the compounding agent are dissolved in a solvent as desired to obtain a solution, and after casting the solution, the solvent is removed to form a film. Is the method. The solvent to be used may be appropriately selected from known solvents according to the organic polymer compound to be used. Examples of the wet method include spin coating, blade coating, dip coating, roll coating, bar coating, die coating, screen printing, and ink jet printing. It is also possible to apply a printing method called soft lithography such as microcontact printing and micromolding. Of these wet methods, the spin coating method is particularly preferable.
[0066] (1 4 2)強誘電体膜 ゲート絶縁膜を構成する強誘電体膜の材料は、特に限定されないが、通常、絶縁 性有機高分子単独、又は絶縁性有機高分子と無機金属酸化物もしくは高誘電性絶 縁体のナノ粒子との混合物を用いることができる。絶縁性有機高分子の選択や、絶 縁性有機高分子と前記ナノ粒子の間の質量比を調節することによって、誘電率を調 節すること力 Sできる。このような材料を用い、上述した低誘電体膜と同様の形成方法 に従って強誘電体膜を形成することができる。この強誘電体膜の形成においても、上 述した形成方法のうち、湿式法が好ましぐスピンコート法が特に好ましい。 [0066] (1 4 2) Ferroelectric film The material of the ferroelectric film constituting the gate insulating film is not particularly limited. Usually, the insulating organic polymer alone, or the insulating organic polymer and the inorganic metal oxide or high dielectric insulator nanoparticles are used. Can be used. The dielectric constant can be adjusted by selecting an insulating organic polymer and adjusting the mass ratio between the insulating organic polymer and the nanoparticles. Using such a material, a ferroelectric film can be formed according to the same formation method as that of the low dielectric film described above. Also in the formation of the ferroelectric film, among the above-described forming methods, the spin coating method is particularly preferable, which is preferable to the wet method.
[0067] 絶縁性有機高分子としては、例えば、ポリエステル、ポリカーボネート、ポリビニール アルコール、ポリビニールブチラール、ポリアセタール、ポリアリレート、ポリアミド、ポリ アミドイミド、ポリエーテルイミド、ポリフエ二レンエーテル、ポリフエ二レンスルファイド、 ポリエーテルスルホン、ポリエーテルケトン、ポリフタノレアミド、ポリエーテル二トリル、ポ リエーテルスルホン、ポリべンズイミダゾール、ポリカルポジイミド、ポリシロキサン、ポリ メチルメタタリレート、ポリメタクリルアミド、二トリルゴム、アクリルゴム、ポリエチレンテト ラフルオリド、エポキシ樹脂、フエノール樹脂、メラミン樹脂、ゥレア樹脂、ポリブテン、 ポリペンテン、エチレン プロピレン共重合体、エチレンーブテン ジェン共重合体 、ポリブタジエン、ポリイソプレン、エチレン プロピレン ジェン共重合体、プチルゴ ム、ポリメチルペンテン、ポリスチレン、スチレンーブタイジェン共重合体、水添スチレ ンーブタジエン共重合体、水添ポリイソプレン、水添ポリブタジエン、及びシァノエチ ル化セルロースからなる群より選択された 1種以上の物質を用いることができる。  [0067] Examples of the insulating organic polymer include polyester, polycarbonate, polyvinyl alcohol, polyvinyl butyral, polyacetal, polyarylate, polyamide, polyamidoimide, polyetherimide, polyphenylene ether, polyphenylene sulfide, Polyethersulfone, polyetherketone, polyphthalanolamide, polyethernitrile, polyethersulfone, polybenzimidazole, polycarpositimide, polysiloxane, polymethylmethacrylate, polymethacrylamide, nitrile rubber, acrylic rubber , Polyethylene tetrafluoride, epoxy resin, phenol resin, melamine resin, urea resin, polybutene, polypentene, ethylene-propylene copolymer, ethylene-butene copolymer Polymer, polybutadiene, polyisoprene, ethylene propylene copolymer, butyl rubber, polymethylpentene, polystyrene, styrene-butadiene copolymer, hydrogenated styrene-butadiene copolymer, hydrogenated polyisoprene, hydrogenated polybutadiene, and One or more substances selected from the group consisting of cyanocelluloses can be used.
[0068] 無機金属酸化物のナノ粒子としては、特に制限はないが、例えば、 Ta O 、 Y O 、  [0068] The inorganic metal oxide nanoparticles are not particularly limited, and examples thereof include Ta 2 O 3, Y 2 O 3,
2 5 2 3 2 5 2 3
TiO 、 CeO及び ZrOなどのナノ粒子が挙げられる。高誘電性絶縁体のナノ粒子とNanoparticles such as TiO 2, CeO and ZrO can be mentioned. High dielectric insulator nanoparticles and
2 2 2 2 2 2
しては、特に制限はないが、例えば、 Ba Sr TiO (式中、 dは 0く dく 1を満たす。 ; d 1 d 3  For example, Ba Sr TiO (where d is 0 and d satisfies 1); d 1 d 3
BST)、PbZr Ti O (式中、 eは 0く eく 1を満たす。 ; PZT)、Bi Ti〇 、 BaMgF  BST), PbZr Ti O (wherein e is 0 and e satisfies 1; PZT), Bi TiO, BaMgF
e 1 e 3 4 3 12 4 e 1 e 3 4 3 12 4
、 SrBi (Ta Nb ) O (式中、 fは 0く fく 1を満たす。)、 Ba (Zr Ti ) 0 (式中、 g , SrBi (Ta Nb) O (where f is 0 and f satisfies 1), Ba (Zr Ti) 0 (where g
2 1 -f f 2 9 1 g g 3 は 0く gく 1を満たす。 ; BZT)、 BaTiO 、 SrTiO及び Bi Ti O などのナノ粒子が  2 1 -f f 2 9 1 g g 3 satisfies 0 and g Nanoparticles such as BZT), BaTiO 3, SrTiO 2 and Bi Ti 2 O 3
3 3 4 3 12  3 3 4 3 12
挙げられる。なお、 Ba Sr TiOは、 Barium Strontium Titanateと呼称される d 1 d 3  Can be mentioned. Ba Sr TiO is called Barium Strontium Titanate d 1 d 3
ものであり、通常、 BaTiOと SrTiOとを重量比(BaTiO : SrTiO )で 1 : 9〜9 : 1の  Usually, the weight ratio of BaTiO and SrTiO (BaTiO: SrTiO) is 1: 9 to 9: 1
3 3 3 3  3 3 3 3
割合で混合して得られる。これらのナノ粒子は、それぞれ単独で、又は 2種以上を混 合して用いること力 Sできる。前記ナノ粒子としては、誘電率が 5以上のものが好ましぐ かかる観点から、通常、高誘電性絶縁体のナノ粒子が好適に用いられる。ナノ粒子 の平均粒子径は、通常、 50nm以下、好ましくは;!〜 50nm、より好ましくは;!〜 30nm である。なお、誘電率は JIS K 6911に従って、平均粒子径は動的光散乱法により 測定すること力でさる。 It is obtained by mixing at a ratio. These nanoparticles may be used alone or in combination of two or more. It can be used together. As the nanoparticles, those having a dielectric constant of 5 or more are preferable. From the viewpoint of achieving this, normally, nanoparticles of a high dielectric insulator are preferably used. The average particle size of the nanoparticles is usually 50 nm or less, preferably !!-50 nm, more preferably !!-30 nm. The dielectric constant is measured according to JIS K 6911, and the average particle size is measured by the dynamic light scattering method.
[0069] 強誘電体膜の材料としては、上述したような絶縁性有機高分子に、前記ナノ粒子に 代えて、チタニウム化合物、ジルコニウム化合物、ハフニウム化合物及びアルミニウム 化合物からなる群より選択された少なくとも一種の有機金属化合物を混合したものを 用いてもよい。この場合にも、 5以上の比誘電率を有する有機金属化合物を用いるの が好ましい。  [0069] As the material of the ferroelectric film, at least one selected from the group consisting of a titanium compound, a zirconium compound, a hafnium compound, and an aluminum compound, instead of the nanoparticle, instead of the insulating organic polymer as described above. A mixture of these organometallic compounds may also be used. Also in this case, it is preferable to use an organometallic compound having a relative dielectric constant of 5 or more.
[0070] (1 5)保護膜、基板及びその形成工程  [0070] (1 5) Protective film, substrate and formation process thereof
本実施形態の有機薄膜トランジスタは、最外層に保護膜 (例えば、図 la,図 lb,図 2a,図 2bにおける保護膜 23)を有してもよい。保護膜は、例えば、 CVD法ゃスパッタ リング法によって形成した酸化シリコン膜、窒化シリコン膜又は酸窒化シリコン膜;熱 C VD法によって形成したポリパラキシレン膜;あるいは、前記のような湿式法に従って 形成したポリイミド膜、脂環式ォレフインポリマー膜、紫外線硬化エポキシ樹脂膜、ァ クリル系樹脂膜等が好ましい。該保護膜の膜厚としては、通常、 lOOnm〜; ίθ πιが 好ましい。  The organic thin film transistor of this embodiment may have a protective film (for example, the protective film 23 in FIGS. La, lb, 2a, and 2b) as the outermost layer. The protective film is formed by, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film formed by a CVD method or a sputtering method; a polyparaxylene film formed by a thermal CVD method; or a wet method as described above Preferred are a polyimide film, an alicyclic olefin polymer film, an ultraviolet curable epoxy resin film, an acrylic resin film, and the like. The thickness of the protective film is usually preferably from lOOnm to ίθπι.
[0071] 本実施形態の有機薄膜トランジスタでは、薄膜状の有機薄膜トランジスタを支持す るために基板 11が用いられている。基板は特に限定されず、いかなる物を用いても 良い。基板として一般に好適に用いられる物は、ポリカーボネート、ポリイミドゃポリエ チレンテレフタレート(PET)の他、脂環式ォレフインポリマーなどの柔軟性のあるプラ スチック基板であるカ 、石英、ソーダガラス、無機アルカリガラスなどのガラス基板や シリコンウェハー等も用いることができる。  In the organic thin film transistor of this embodiment, the substrate 11 is used to support the thin film organic thin film transistor. The substrate is not particularly limited, and any material may be used. In general, polycarbonate, polyimide, polyethylene terephthalate (PET), and flexible plastic substrates such as alicyclic olefin polymers are used as substrates, such as glass, quartz, soda glass, and inorganic alkali. Glass substrates such as glass and silicon wafers can also be used.
[0072] 本実施形態の有機薄膜トランジスタは、前記基板及び/又は保護膜が、前述の脂 環式ォレフインポリマーからなるものであることが好ましい。脂環式ォレフインポリマー は透湿度やガス透過度が低!/、ので、前記基板及び/又は保護膜が前述の脂環式 ォレフィンポリマーからなるものであれば、有機半導体膜の劣化を防止する効果が高 い。 [0072] In the organic thin film transistor of this embodiment, it is preferable that the substrate and / or the protective film is made of the above-described alicyclic polyolefin polymer. Since the alicyclic olefin polymer has low moisture permeability and gas permeability! /, If the substrate and / or the protective film is made of the above alicyclic olefin polymer, the organic semiconductor film is not deteriorated. High effect to prevent Yes.
[0073] (1 6)下引き層及びその形成方法  [0073] (16) Undercoat layer and formation method thereof
図 la及び図 lb、並びに及び図 2a及び図 2bに示す有機薄膜トランジスタにおいて は、ポリマー又は無機酸化物及び無機窒化物から選ばれる化合物を含有する下引 き層 12が設けられている。  In the organic thin film transistor shown in FIGS. La and lb and FIGS. 2a and 2b, an undercoat layer 12 containing a compound selected from a polymer or an inorganic oxide and an inorganic nitride is provided.
[0074] 下引き層に含有される無機酸化物としては、酸化ケィ素、酸化アルミニウム、酸化タ ンタル等が挙げられる。また無機窒化物としては窒化ケィ素、窒化アルミニウム等が 挙げられる。それらのうち好ましいのは、酸化ケィ素、窒化ケィ素である。  [0074] Examples of the inorganic oxide contained in the undercoat layer include silicon oxide, aluminum oxide, and tantalum oxide. Examples of the inorganic nitride include silicon nitride and aluminum nitride. Of these, preferred are silicon oxide and nitride nitride.
[0075] ポリマーを含む下引き層に用いるポリマーとしては、ポリエステル樹脂、ポリカーボ ネート樹脂、セルロース樹脂、アクリル樹脂、ポリウレタン樹脂、ポリエチレン樹脂、ポ リプロピレン樹脂、ポリスチレン樹脂、フエノキシ樹脂、ノルボルネン樹脂、エポキシ樹 脂、塩化ビュル 酢酸ビュル共重合体、塩化ビュル樹脂、酢酸ビュル樹脂、酢酸ビ ニルとビュルアルコールの共重合体、部分加水分解した塩化ビュル 酢酸ビュル共 重合体、塩化ビュル一塩化ビニリデン共重合体、塩化ビュル アクリロニトリル共重 合体、エチレン ビュルアルコール共重合体、ポリビュルアルコール、塩素化ポリ塩 化ビュル、エチレン一塩化ビュル共重合体、エチレン 酢酸ビュル共重合体等のビ ニル系重合体、ポリアミド樹脂、エチレン ブタジエン樹脂、ブタジエン アタリロニト リル樹脂等のゴム系樹脂、シリコーン樹脂、フッ素系樹脂、脂環式ォレフイン樹脂等 を挙げること力 Sでさる。  [0075] Polymers used for the undercoat layer containing the polymer include polyester resin, polycarbonate resin, cellulose resin, acrylic resin, polyurethane resin, polyethylene resin, polypropylene resin, polystyrene resin, phenoxy resin, norbornene resin, epoxy resin. Fat, butyl chloride, butyl acetate copolymer, butyl chloride resin, butyl acetate resin, copolymer of vinyl acetate and butyl alcohol, partially hydrolyzed butyl chloride copolymer, butyl chloride chloride vinylidene chloride copolymer, Vinyl polymers such as butyl acrylonitrile chloride copolymer, ethylene butyl alcohol copolymer, poly butyl alcohol, chlorinated poly chlorinated butyl, ethylene monochloride butyl copolymer, ethylene butyl acetate copolymer, polyamide resin, Ethylene butadiene resin Rubber-based resins such as butadiene Atarironito Lil resin, silicone resin, leaving a fluorine-based resin, it forces mentioned alicyclic Orefuin resin S.
[0076] 下引き層はその形成方法によって特に制限されない。下引き層の形成方法として は、例えば、真空蒸着法、分子線ェピタキシャル成長法、イオンクラスタービーム法、 低エネルギーイオンビーム法、イオンプレーティング法、 CVD法、スパッタリング法、 大気圧プラズマ法などのドライプロセスや、スプレーコート法、スピンコート法、ブレー ドコート法、ディップコート法、キャスト法、ロールコート法、バーコート法、ダイコート法 などの塗布による方法、印刷やインクジェットなどのパターユングによる方法などのゥ エツトプロセスが挙げられる。  [0076] The undercoat layer is not particularly limited by the formation method. Examples of the method for forming the undercoat layer include vacuum deposition, molecular beam epitaxy, ion cluster beam, low energy ion beam, ion plating, CVD, sputtering, and atmospheric pressure plasma. Such as dry processes, spray coating, spin coating, blade coating, dip coating, dip coating, casting, roll coating, bar coating, die coating, and other methods such as printing and ink jet patterning. There is a wet process.
[0077] (1 7)表示装置 [0077] (17) Display device
本実施形態の表示装置は、前記有機薄膜トランジスタを備えて構成される。この表 示装置をより具体的に説明するために、有機 EL表示装置を一例にして説明する。こ の有機 EL表示装置は、基板上にマトリクス配列して形成された各画素力 少なくとも 1つの有機 EL素子と、該有機 EL素子を駆動するための少なくとも 2つの有機薄膜ト ランジスタとを有するものである。そして、該有機薄膜トランジスタの少なくとも 1つは 前述の有機薄膜トランジスタである。 The display device of this embodiment includes the organic thin film transistor. This table In order to describe the display device more specifically, an organic EL display device will be described as an example. This organic EL display device has at least one organic EL element with each pixel force formed in a matrix arrangement on a substrate, and at least two organic thin film transistors for driving the organic EL element. is there. At least one of the organic thin film transistors is the aforementioned organic thin film transistor.
[0078] 有機 EL素子は、特に制限されず、例えば陽極となる正孔注入電極と陰極となる電 子注入電極との間に正孔輸送層と発光材料層とが形成された構造(SH— A構造)の もの、正孔注入電極と電子注入電極との間に発光材料層と電子輸送層とが形成され た構造(SH— B構造)のもの、又は正孔注入電極と電子注入電極との間に、正孔輸 送層と発光材料層と電子輸送層とが形成された構造 (DH構造)のものなどが挙げら れる。いずれの構造の場合でも、有機 EL素子は正孔注入電極(陽極)から注入され た正孔と電子注入電極(陰極)から注入された電子が、発光材料層と正孔(又は電子 )輸送層の界面、及び発光材料層内で再結合して発光するという原理で作動する。  [0078] The organic EL element is not particularly limited. For example, a structure in which a hole transport layer and a light emitting material layer are formed between a hole injection electrode serving as an anode and an electron injection electrode serving as a cathode (SH--). A structure), a structure in which a light emitting material layer and an electron transport layer are formed between a hole injection electrode and an electron injection electrode (SH-B structure), or a hole injection electrode and an electron injection electrode Among them, a structure in which a hole transport layer, a light emitting material layer, and an electron transport layer are formed (DH structure) is included. Regardless of the structure, the organic EL element has a light emitting material layer and a hole (or electron) transport layer formed by the holes injected from the hole injection electrode (anode) and the electrons injected from the electron injection electrode (cathode). It operates on the principle that light is emitted by recombination within the interface and the light emitting material layer.
[0079] 図 3に典型的な有機 EL素子の構成例を示す。図 3に示す有機 EL素子は、透明基 板 1 、下部電極層(陽極) 54、発光材料層 62、上部電極層(陰極) 55とから構成さ れている。また最外層として保護膜 23が設けられている。透明基板 11 'としては、 40 0〜700nmの可視領域の光の透過率が、 50%以上で、平滑であり、かつ電極や有 機 EL素子の各層を形成する際に特性が変化しな!/、ものであることが好まし!/、。  FIG. 3 shows a configuration example of a typical organic EL element. The organic EL element shown in FIG. 3 includes a transparent substrate 1, a lower electrode layer (anode) 54, a light emitting material layer 62, and an upper electrode layer (cathode) 55. A protective film 23 is provided as the outermost layer. The transparent substrate 11 ′ has a visible light transmittance of 400 to 700 nm of 50% or more, is smooth, and does not change its characteristics when forming each layer of electrodes and organic EL elements! /, I prefer to be a thing!
[0080] 透明基板 11 'は、プラスチック、ガラス、石英、シリコン及びセラミックよりなる群から 選択された材料で形成することができる。特に、基板材料としてプラスチックを用いる と、フレキシブルで軽量な有機 ELディスプレイを得ることができる。プラスチックとして は、ポリカーボネート樹脂、ポリエーテルスルホン樹脂、ポリエチレンテレフタレート樹 脂、ポリイミド樹脂、ポリメチルメタタリレート樹脂及び脂環式ォレフインポリマーよりな る群から選択されると、好適である。基板の平均厚みは、通常 30 111〜3111111で好ま しく ίま 50〜300〃111である。  [0080] The transparent substrate 11 'can be formed of a material selected from the group consisting of plastic, glass, quartz, silicon, and ceramic. In particular, when plastic is used as the substrate material, a flexible and lightweight organic EL display can be obtained. The plastic is preferably selected from the group consisting of polycarbonate resin, polyethersulfone resin, polyethylene terephthalate resin, polyimide resin, polymethyl methacrylate resin, and alicyclic olefin polymer. The average thickness of the substrate is usually 30 111 to 3111111, preferably 50 to 300 mm 111.
[0081] 下部電極層 54を構成する材料としては、下部電極層から光を出光させるための材 料が挙げられ、具体的には導電性の金属酸化物や半透明の金属又はその積層体が 挙げられる。具体的には、酸化インジウム、酸化亜鉛、酸化スズ、及びそれらの複合 体である酸化インジウム'スズ (ITO)、酸化インジウム ·亜鉛等からなる導電性ガラス( NESAなど)や、金、白金、銀、銅等が用いられ、中でも ITO、酸化インジウム '亜鉛、 酸化スズが好ましい。また下部電極層として、ポリア二リン若しくはその誘導体、ポリチ ォフェンなどの有機の透明導電膜を用いてもよい。 [0081] Examples of the material constituting the lower electrode layer 54 include materials for emitting light from the lower electrode layer. Specifically, a conductive metal oxide, a translucent metal, or a laminate thereof is used. Can be mentioned. Specifically, indium oxide, zinc oxide, tin oxide, and composites thereof Conductive glass (NESA, etc.) made of indium oxide (tin) (ITO), indium oxide, zinc, etc., gold, platinum, silver, copper, etc. are used. Among them, ITO, indium oxide (zinc oxide, tin oxide) are used. preferable. As the lower electrode layer, an organic transparent conductive film such as polyaniline or a derivative thereof or polythiophene may be used.
[0082] 下部電極層の平均厚みは、光の透過性と電気伝導度とを考慮して、適宜選択する ことができる力 通常 lOnm〜; lO ^ mであり、好ましくは 100〜500nmである。下部 電極層は透明又は半透明であることが、発光の取出し効率がよく好都合である。下 部電極層の作製方法としては、真空蒸着法、スパッタリング法、金属薄膜を熱圧着す るラミネート法が挙げられる。  [0082] The average thickness of the lower electrode layer can be selected as appropriate in consideration of light transmittance and electrical conductivity. Usually, lOnm to lO ^ m, preferably 100 to 500 nm. It is convenient that the lower electrode layer is transparent or translucent because the emission efficiency of light emission is good. Examples of the method for producing the lower electrode layer include a vacuum deposition method, a sputtering method, and a laminating method in which a metal thin film is thermocompression bonded.
[0083] 発光材料層 62を構成する材料は、特に制限はなぐ有機 EL素子における発光材 料として公知のものを用いることができる。このような発光材料の具体例としては、ベ ンゾチアゾール系、ベンゾイミダゾール系、ベンゾォキサゾール系などの蛍光増白剤 や、金属キレート化ォキシノイド化合物、スチリルベンゼン系化合物、ジスチリルピラ ジン誘導体、芳香族ジメチリジン化合物などが挙げられる。発光材料層に 2種類以上 の発光材料を混合して使用してもよぐ 2層以上の発光材料層が積層されていてもよ い。発光材料層の作製方法としては、真空蒸着法、キャスト法などが挙げられる。発 光材料層の平均厚みは、用いる材料によって最適値が異なり、駆動電圧と発光効率 が適度な値となるように選択すればよいが、通常は 11 111〜1 111であり、好ましくは 2 nm〜 500nmで ¾>る。  [0083] As the material constituting the light emitting material layer 62, a known material can be used as a light emitting material in the organic EL element without particular limitation. Specific examples of such light-emitting materials include fluorescent brighteners such as benzothiazole, benzimidazole, and benzoxazole, metal chelated oxinoid compounds, styrylbenzene compounds, distyrylpyrazine derivatives, and aromatic dimethylidine. Compound etc. are mentioned. Two or more kinds of light emitting materials may be mixed and used in the light emitting material layer. Two or more light emitting material layers may be laminated. Examples of a method for manufacturing the light emitting material layer include a vacuum deposition method and a casting method. The average thickness of the light-emitting material layer varies depending on the material used, and may be selected so that the drive voltage and the light emission efficiency are moderate values, but is usually 11 111 to 1 111, preferably 2 nm. ~ 500nm.
[0084] 上部電極層 55 (陰極)を構成する材料としては、仕事関数の小さ!/、材料が好ましく 、発光材料層から上部電極層側に向かう発光光を反射させ、下部電極層側に向か わせるため鏡面体であることがさらに好ましい。具体的には、リチウム、ナトリウム、カリ ゥム、ノレビジゥム、セシウム、ベリリウム、マグネシウム、カノレシゥム、ストロンチウム、ノ リウム、ァノレミニゥム、スカンジウム、ノ ナジゥム、亜 イットリウム、インジウム、セリウ ム、サマリウム、ユーロピウム、テルビウム、イッテルビウムなどの金属、及びこれらから 選ばれる 2つ以上の金属の合金、若しくはこれらから選ばれる 1つ以上の金属と、金、 銀、白金、銅、マンガン、チタン、コバルト、ニッケル、タングステン、及び錫の中から 選ばれる 1つ以上の金属との合金、グラフアイト若しくはグラフアイト層間化合物等が 用いられる。合金の具体例としては、マグネシウム 銀合金、マグネシウム インジゥ ム合金、マグネシウム アルミニウム合金、インジウム 銀合金、リチウム アルミユウ ム合金、リチウム マグネシウム合金、リチウム インジウム合金、カルシウム アルミ ニゥム合金などが挙げられる。上部電極層は 2層以上の積層構造としてもよい。上部 電極層の作製方法としては、真空蒸着法、スパッタリング法、イオンプレーティング法 、メツキ法などが挙げられる。上部電極層の平均厚みは、電気伝導度や耐久性を考 慮して、適宜選択することができるが、通常 10nm〜; 10 111、好ましくは 100〜500n mである。 [0084] The material constituting the upper electrode layer 55 (cathode) is preferably a material having a small work function! /, Which reflects light emitted from the light emitting material layer toward the upper electrode layer and is directed toward the lower electrode layer. Therefore, a mirror body is more preferable. Specifically, lithium, sodium, potassium, norebium, cesium, beryllium, magnesium, canolecium, strontium, norium, anoleminium, scandium, nonadium, yttrium, indium, sericium, samarium, europium, terbium, ytterbium And an alloy of two or more metals selected from these, or one or more metals selected from these, and gold, silver, platinum, copper, manganese, titanium, cobalt, nickel, tungsten, and tin. An alloy with one or more metals selected from among, a graphite or a graphite intercalation compound, etc. Used. Specific examples of the alloy include magnesium silver alloy, magnesium indium alloy, magnesium aluminum alloy, indium silver alloy, lithium aluminum alloy, lithium magnesium alloy, lithium indium alloy, and calcium aluminum alloy. The upper electrode layer may have a laminated structure of two or more layers. Examples of the method for producing the upper electrode layer include a vacuum deposition method, a sputtering method, an ion plating method, and a plating method. The average thickness of the upper electrode layer can be appropriately selected in consideration of electric conductivity and durability, but is usually 10 nm to 10111, preferably 100 to 500 nm.
[0085] 有機 EL素子には、透明基板 11 'と、下部電極層 54、発光材料層 62、上部電極層  [0085] The organic EL element includes a transparent substrate 11 ', a lower electrode layer 54, a light emitting material layer 62, an upper electrode layer.
55、及び保護膜 23のほかに他の層を有していてもよい。他の層としては、正孔注入 層、正孔輸送層、電子輸送層、電子注入層が挙げられる。正孔注入層とは、陽極に 隣接して設ける層であり、陽極からの正孔注入効率を改善する機能を有する層をレ、う 。正孔注入層の平均厚みは、通常 lnm〜; 100nm、好ましくは 2nm〜50nmである。 正孔輸送層とは、正孔を輸送する機能を有する層をいう。正孔輸送層の厚さは、用 いる材料によって最適値が異なり、駆動電圧と発光効率が適度な値となるように選択 すればよいが、少なくともピンホールが発生しないような厚さが必要であり、あまり厚い と、素子の駆動電圧が高くなり好ましくない。したがって、正孔輸送層の平均厚みは、 通常11 111〜1 111、好ましくは 2nm〜500nmである。正孔注入層ゃ正孔輸送層に 用いる材料としては、有機 EL素子における正孔伝達化合物として公知のものが挙げ られる。  In addition to 55 and the protective film 23, another layer may be provided. Examples of the other layer include a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. The hole injection layer is a layer provided adjacent to the anode, and is a layer having a function of improving the hole injection efficiency from the anode. The average thickness of the hole injection layer is usually 1 nm to 100 nm, preferably 2 nm to 50 nm. The hole transport layer refers to a layer having a function of transporting holes. The thickness of the hole transport layer differs depending on the material used, and it may be selected so that the drive voltage and luminous efficiency are appropriate. If it is too thick, the drive voltage of the element increases, which is not preferable. Therefore, the average thickness of the hole transport layer is usually 11 111 to 1111, preferably 2 nm to 500 nm. Examples of materials used for the hole injection layer and the hole transport layer include those known as hole transport compounds in organic EL devices.
[0086] 電子輸送層とは、電子を輸送する機能を有する層を!/、う。電子輸送層の厚さは、用 いる材料によって最適値が異なり、駆動電圧と発光効率が適度な値となるように選択 すればよいが、少なくともピンホールが発生しないような厚さが必要であり、あまり厚い と、有機 EL素子の駆動電圧が高くなり好ましくない。したがって、電子輸送層の平均 厚さは、通常11 111〜1 111、好ましくは 2nm〜500nmである。電子注入層とは、陰極 に隣接して設けた層であって、陰極からの電子注入効率を改善する機能を有し、素 子の駆動電圧を下げる効果を有するものをいう。電子注入層の平均厚みは、通常 In m〜; !OOnmであり、好ましくは 2nm〜50nmである。電子輸送層、電子注入層に用 いる材料としては、有機 EL素子における電子伝達化合物として公知のものが挙げら れる。以上のその他の層の作製方法としては、スピンコート法、キャスト法、真空蒸着 法などが挙げられる。 [0086] The electron transport layer is a layer having a function of transporting electrons. The thickness of the electron transport layer differs depending on the material used and may be selected so that the drive voltage and light emission efficiency are appropriate. However, the thickness should be at least sufficient to prevent pinholes. If it is too thick, the driving voltage of the organic EL element increases, which is not preferable. Therefore, the average thickness of the electron transport layer is usually 11 111 to 1111, preferably 2 nm to 500 nm. The electron injection layer is a layer provided adjacent to the cathode and has a function of improving the electron injection efficiency from the cathode and has an effect of lowering the driving voltage of the element. The average thickness of the electron injection layer is usually In m˜;! OOnm, preferably 2 nm˜50 nm. For electron transport layer and electron injection layer Examples of the material include those known as electron transfer compounds in organic EL devices. Examples of other methods for producing the layers include spin coating, casting, and vacuum deposition.
[0087] 図 4は本実施形態の有機 EL表示装置の一画素分の回路構成例である。有機 EL 表示装置の一画素分の構成としては、通常、少なくとも 1つの有機 EL素子に対し、該 EL素子を駆動するための有機薄膜トランジスタとして少なくとも 2つ、すなわち、駆動 トランジスタと書き込みトランジスタが必要である力 図 4の構成例では駆動トランジス タのみを示し、書き込みトランジスタは省略してある。駆動トランジスタと書き込みトラ ンジスタの少なくとも 1つは本実施形態の有機薄膜トランジスタにより構成される。  FIG. 4 is a circuit configuration example for one pixel of the organic EL display device of the present embodiment. As a configuration for one pixel of an organic EL display device, usually, at least two organic thin film transistors for driving the EL element are required for at least one organic EL element, that is, a driving transistor and a writing transistor. In the configuration example in Fig. 4, only the drive transistor is shown, and the write transistor is omitted. At least one of the drive transistor and the write transistor is constituted by the organic thin film transistor of this embodiment.
[0088] 図 4では、前記有機 EL素子 6の陽極 54と前記有機薄膜トランジスタ 5 (駆動トランジ スタ)のドレイン電極 14とが接続されている。そして、例えば図 5に示すようなァクティ ブマトリックス方式の回路にぉレ、て、水平駆動回路に接続された走査電極 1に順じ印 カロされた電圧により有機薄膜トランジスタ 2 (書き込みトランジスタ)がオン状態になり、 垂直駆動回路に接続されたデータ電極 3からの表示信号に応じた電荷量がコンデン サ 4に蓄積される。コンデンサ 4に蓄積された電荷量により駆動トランジスタ 5が動作し 、有機 EL素子 6に電流が供給され有機 EL素子が点灯する。走査電極 1に電圧が印 カロされるまでの間この点灯状態が保持されることになる。  In FIG. 4, the anode 54 of the organic EL element 6 and the drain electrode 14 of the organic thin film transistor 5 (drive transistor) are connected. Then, for example, the organic thin film transistor 2 (write transistor) is turned on by the voltage applied in sequence to the scan electrode 1 connected to the horizontal drive circuit, as compared with an active matrix circuit as shown in FIG. Thus, the charge amount corresponding to the display signal from the data electrode 3 connected to the vertical drive circuit is accumulated in the capacitor 4. The drive transistor 5 operates according to the amount of charge accumulated in the capacitor 4, current is supplied to the organic EL element 6, and the organic EL element is turned on. This lighting state is maintained until the voltage is applied to the scan electrode 1.
[0089] (2)第 2実施形態 [0089] (2) Second Embodiment
以下、第 2実施形態として、上述した本発明の第 2の観点に対応する有機複合電子 素子、その製造方法、及び有機複合電子素子を用いる有機半導体メモリについて説 明する。  Hereinafter, as a second embodiment, an organic composite electronic device corresponding to the above-described second aspect of the present invention, a manufacturing method thereof, and an organic semiconductor memory using the organic composite electronic device will be described.
[0090] (2— 1)有機複合電子素子の全体構成  [0090] (2-1) Overall structure of organic composite electronic device
(2 1 1)ボトムゲート'スタガー型  (2 1 1) Bottom gate 'Stagger type
図 6a〜図 6fは、ボトムゲート'スタガー型 (Bottom Gate Stagger type)のトランジスタ 及びキャパシタからなる有機複合電子素子の製造工程を示す図である。まず、基板 1 1上にトランジスタ用ゲート電極 Ga及びキャパシタ用対向電極の一方 CE1を同一の 工程で形成する第 1電極群形成工程を行う(図 6a)。なお、基板 11上に下引き層(不 図示)を形成し、該下引き層上にこれらの電極 Ga、 CE1を形成するようにしてもよい。 次に、これらの電極 Ga、 CElを含む基板 11上(下引き層を形成した場合には該下 引き層上)に絶縁膜 17を形成する絶縁膜形成工程を行う(図 6b)。この絶縁膜形成 工程には、強誘電体膜 17bを形成する強誘電体膜形成工程、及び強誘電体膜 17b 上に当該強誘電体膜 17bと比較して低誘電率を有する低誘電体膜 17aを形成する 低誘電体膜形成工程が含まれる。 FIGS. 6a to 6f are diagrams showing a manufacturing process of an organic composite electronic device including a bottom gate stagger type transistor and a capacitor. First, a first electrode group forming process is performed in which one of the transistor gate electrode Ga and the capacitor counter electrode CE1 is formed on the substrate 11 in the same process (FIG. 6a). Note that an undercoat layer (not shown) may be formed on the substrate 11, and these electrodes Ga and CE1 may be formed on the undercoat layer. Next, an insulating film forming step is performed in which an insulating film 17 is formed on the substrate 11 including these electrodes Ga and CEl (on the underlayer when the undercoat layer is formed) (FIG. 6b). The insulating film forming step includes a ferroelectric film forming step for forming the ferroelectric film 17b, and a low dielectric film having a low dielectric constant on the ferroelectric film 17b as compared with the ferroelectric film 17b. A low dielectric film forming step of forming 17a is included.
[0091] その後、低誘電体膜 17a上に有機半導体膜 16を形成する有機半導体膜形成工程 を行う(図 6c)。次に、低誘電体膜 17a及び有機半導体膜 16のキャパシタ用対向電 極 CE1に対応する部分 (その近傍を含んでもよ!/、)を除去する膜除去工程を行う。こ の膜除去工程には、有機半導体膜 16上にマスク MSを形成又は設置するマスク形 成工程(図 6d)と、エッチング等によりキャパシタ用対向電極 CE1に対応する部分を 除去するエッチング工程と、該マスク MSを除去するマスク除去工程とが含まれる。こ れにより、低誘電体膜 17a及び有機半導体膜 16のキャパシタ用対向電極 CE1に対 応する部分に除去部が形成される(図 6e)。  [0091] Thereafter, an organic semiconductor film forming step of forming the organic semiconductor film 16 on the low dielectric film 17a is performed (FIG. 6c). Next, a film removal step is performed to remove portions of the low dielectric film 17a and the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 (including the vicinity thereof! /). In this film removal process, a mask formation process (FIG. 6d) for forming or placing a mask MS on the organic semiconductor film 16, an etching process for removing a portion corresponding to the capacitor counter electrode CE1 by etching or the like, And a mask removing step for removing the mask MS. As a result, removal portions are formed in portions of the low dielectric film 17a and the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 (FIG. 6e).
[0092] 次に、強誘電体膜 17b、低誘電体膜 17a及び有機半導体膜 16を挟んでトランジス タ用ゲート電極 Gaと所定の位置関係でトランジスタを構成するようにトランジスタ用ソ ース電極 So、ドレイン電極 Drを、及び強誘電体膜 17bを挟んでキャパシタを構成す るようにキャパシタ用対向電極 CE1に対応してキャパシタ用対向電極 CE2を同一の 工程で形成する第 2電極群形成工程を行う(図 6f)。その後、図示は省略しているが 、保護膜形成工程を行って保護膜を形成する。これにより、強誘電体膜 17b及び低 誘電体膜 17aをゲート絶縁膜 17とした有機薄膜トランジスタ Tr、及び強誘電体膜 17 bを絶縁膜とした高誘電体キャパシタ Caを備える有機複合電子素子が製造される。  [0092] Next, the transistor source electrode So is configured so that the transistor is configured in a predetermined positional relationship with the transistor gate electrode Ga across the ferroelectric film 17b, the low dielectric film 17a, and the organic semiconductor film 16. A second electrode group forming step of forming the capacitor counter electrode CE2 corresponding to the capacitor counter electrode CE1 in the same process so as to form a capacitor with the drain electrode Dr and the ferroelectric film 17b interposed therebetween. Perform (Figure 6f). Thereafter, although not shown, a protective film is formed by forming a protective film. As a result, an organic composite electronic device including an organic thin film transistor Tr having the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and a high dielectric capacitor Ca having the ferroelectric film 17b as the insulating film is manufactured. Is done.
[0093] なお、ここでは、低誘電体膜形成工程で低誘電体膜 17aを形成し、有機半導体膜 形成工程で有機半導体膜 16を形成した後に、低誘電体膜 17a及び有機半導体膜 1 6のキャパシタを形成する部分を除去するようにした力 S、低誘電体膜形成工程でキヤ パシタを形成する部分を除いて低誘電体膜 17aを形成し、その後有機半導体膜形成 工程で同じくキャパシタを形成する部分を除いて有機半導体膜 16を形成するように してもよい。  [0093] Here, after forming the low dielectric film 17a in the low dielectric film formation step and forming the organic semiconductor film 16 in the organic semiconductor film formation step, the low dielectric film 17a and the organic semiconductor film 16 are formed. The force S that removes the capacitor forming part S, the low dielectric film 17a is formed except the capacitor forming part in the low dielectric film forming process, and then the capacitor is formed in the organic semiconductor film forming process. The organic semiconductor film 16 may be formed except for the portion to be formed.
[0094] また、膜除去工程では低誘電体膜 17aを除去せずに、有機半導体膜 16のみを除 去するようにしてもよい。この場合、強誘電体膜 17b及び低誘電体膜 17aをゲート絶 縁膜 17とした有機薄膜トランジスタ Tr、並びに強誘電体膜 17b及び低誘電体膜 17a を絶縁膜 17とした高誘電体キャパシタ Caを備える有機複合電子素子が製造される。 また、低誘電体膜 17aのキャパシタ用対向電極 CE1に対応する部分の除去は、その 厚さ方向の全てではなぐ一部のみを除去するようにしてもよい。 [0094] Further, in the film removal step, only the organic semiconductor film 16 is removed without removing the low dielectric film 17a. You may make it leave. In this case, the organic thin film transistor Tr having the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and the high dielectric capacitor Ca having the ferroelectric film 17b and the low dielectric film 17a as the insulating film 17 are formed. An organic composite electronic device is provided. In addition, the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 may be removed by removing only a portion of the low dielectric film 17a in the thickness direction.
[0095] (2— 1 2)ボトムゲート'コプレナ一型  [0095] (2 — 1 2) Bottom Gate 'Coplanar Type
図 7a〜図 7fは、ボトムゲート'コプレナ一型 (Bottom Gate Coplanar type)のトランジ スタ及びキャパシタからなる有機複合電子素子の製造工程を示す図である。まず、基 板 11上にトランジスタ用ゲート電極 Ga及びキャパシタ用対向電極の一方 CE1を同 一の工程で形成する第 1電極群形成工程を行う(図 7a)。なお、基板 11上に下引き 層(不図示)を形成し、該下引き層上にこれらの電極 Ga、 CE1を形成するようにして もよい。次に、これらの電極 Ga、 CE1を含む基板 11上(下引き層を形成した場合に は該下引き層上)に絶縁膜 17を形成する絶縁膜形成工程を行う(図 7b)。この絶縁 膜形成工程には、強誘電体膜 17bを形成する強誘電体膜形成工程、及び強誘電体 膜 17b上に当該誘電体膜 17bと比較して低誘電率を有する低誘電体膜 17aを形成 する低誘電体膜形成工程が含まれる。  FIG. 7a to FIG. 7f are diagrams illustrating a manufacturing process of an organic composite electronic device including a bottom gate coplanar type transistor and a capacitor. First, a first electrode group forming process is performed in which one of the transistor gate electrode Ga and the capacitor counter electrode CE1 is formed on the substrate 11 in the same process (FIG. 7a). An undercoat layer (not shown) may be formed on the substrate 11, and these electrodes Ga and CE1 may be formed on the undercoat layer. Next, an insulating film forming step is performed in which an insulating film 17 is formed on the substrate 11 including these electrodes Ga and CE1 (on the undercoat layer when the undercoat layer is formed) (FIG. 7b). The insulating film forming process includes a ferroelectric film forming process for forming the ferroelectric film 17b, and a low dielectric film 17a having a low dielectric constant on the ferroelectric film 17b as compared with the dielectric film 17b. Forming a low dielectric film.
[0096] 次に、低誘電体膜 17aのキャパシタ用対向電極 CE1に対応する部分 (その近傍を 含んでもよ!/、)を除去する低誘電体膜除去工程を行う。この低誘電体膜除去工程に は、低誘電体膜 17a上にマスク MS1を形成又は設置するマスク形成工程(図 7b)と、 エッチング等によりキャパシタ用対向電極 CE1に対応する部分を除去するエツチン グ工程と、該マスク MS1を除去するマスク除去工程とが含まれる。これにより、低誘電 体膜 17aのキャパシタ用対向電極 CE1に対応する部分に除去部が形成される(図 7  Next, a low dielectric film removal step is performed to remove a portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 (including the vicinity thereof! /). This low dielectric film removal process includes a mask formation process (FIG. 7b) in which a mask MS1 is formed or placed on the low dielectric film 17a, and an etching process that removes a portion corresponding to the capacitor counter electrode CE1 by etching or the like. And a mask removing step for removing the mask MS1. As a result, a removal portion is formed in the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 (FIG. 7).
[0097] 次に、強誘電体膜 17b、及び低誘電体膜 17aを挟んでトランジスタ用ゲート電極 Ga と所定の位置関係でトランジスタを構成するようにトランジスタ用ソース電極 So、ドレイ ン電極 Drを、及び強誘電体膜 17bを挟んでキャパシタを構成するようにキャパシタ用 対向電極 CE1に対応してキャパシタ用対向電極 CE2を形成する第 2電極群形成ェ 程を行い、その上に有機半導体膜 16を形成する有機半導体膜形成工程を行う(図 7 d) 0 Next, the transistor source electrode So and the drain electrode Dr are formed so as to form a transistor in a predetermined positional relationship with the transistor gate electrode Ga across the ferroelectric film 17b and the low dielectric film 17a. And a second electrode group forming step of forming a capacitor counter electrode CE2 corresponding to the capacitor counter electrode CE1 so as to constitute a capacitor with the ferroelectric film 17b interposed therebetween, and the organic semiconductor film 16 is formed thereon The organic semiconductor film formation process to be formed is performed (Fig. 7 d) 0
[0098] 次に、有機半導体膜 16のキャパシタ用対向電極 CE1に対応する部分 (その近傍を 含んでもよい)を除去する有機半導体膜除去工程を行う。この膜除去工程には、有機 半導体膜 16上にマスク MS2を形成又は設置するマスク形成工程(図 7e)と、エッチ ング等によりキャパシタ用対向電極 CE1に対応する部分を除去するエッチング工程 と、該マスク MS2を除去するマスク除去工程とが含まれる。これにより、有機半導体 膜 16のキャパシタ用対向電極 CE1に対応する部分に除去部が形成される(図 7f)。 その後、図示は省略しているが、保護膜形成工程を行って保護膜を形成する。これ により、強誘電体膜 17b及び低誘電体膜 17aをゲート絶縁膜 17とした有機薄膜トラン ジスタ Tr、及び強誘電体膜 17bを絶縁膜とした高誘電体キャパシタ Caを備える有機 複合電子素子が製造される。  [0098] Next, an organic semiconductor film removal step is performed to remove a portion of the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 (which may include the vicinity thereof). This film removing step includes a mask forming step (FIG. 7e) for forming or placing a mask MS2 on the organic semiconductor film 16, an etching step for removing a portion corresponding to the capacitor counter electrode CE1 by etching or the like, And a mask removing process for removing the mask MS2. As a result, a removal portion is formed in the portion of the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 (FIG. 7f). Then, although illustration is abbreviate | omitted, a protective film formation process is performed and a protective film is formed. As a result, an organic composite electronic device including an organic thin film transistor Tr having the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and a high dielectric capacitor Ca having the ferroelectric film 17b as the insulating film is obtained. Manufactured.
[0099] なお、ここでは、低誘電体膜形成工程で低誘電体膜 17aを形成した後に、低誘電 体膜除去工程で低誘電体膜 17aのキャパシタを形成する部分を除去するようにした 力 低誘電体膜形成工程でキャパシタを形成する部分を除いて低誘電体膜 17aを形 成するようにしてもよい。同様に、有機半導体膜形成工程で有機半導体膜 16を形成 した後に、有機半導体膜除去工程で有機半導体膜 16のキャパシタを形成する部分 を除去するようにしたが、有機半導体膜形成工程でキャパシタを形成する部分を除 いて有機半導体膜 16を形成するようにしてもよい。また、低誘電体膜 17aのキャパシ タ用対向電極 CE1に対応する部分の除去は、その厚さ方向の全てではなぐ一部の みを除去するようにしてもよ!/、。  [0099] Here, after the low dielectric film 17a is formed in the low dielectric film formation process, the portion of the low dielectric film 17a in which the capacitor is formed is removed in the low dielectric film removal process. The low dielectric film 17a may be formed except for the part where the capacitor is formed in the low dielectric film forming step. Similarly, after forming the organic semiconductor film 16 in the organic semiconductor film forming process, the portion of the organic semiconductor film 16 in which the capacitor is formed is removed in the organic semiconductor film removing process, but the capacitor is removed in the organic semiconductor film forming process. The organic semiconductor film 16 may be formed except for the portion to be formed. In addition, the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 may be removed by removing only a part of the thickness in the thickness direction! /.
[0100] (2 1 3)トップゲート'スタガー型  [0100] (2 1 3) Top gate stagger type
図 8a〜図 8fは、トップゲート'スタガー型 (Top Gate Stagger type)のトランジスタ及 びキャパシタからなる有機複合電子素子の製造工程を示す図である。まず、基板 11 上にトランジスタ用ソース電極 So、ドレイン Dr及びキャパシタ用対向電極の一方 CE 1を同一の工程で形成する第 1電極群形成工程を行!、、その上に有機半導体膜 16 を形成する有機半導体膜形成工程を行う(図 8a)。なお、基板 11上に下引き層(不 図示)を形成し、該下引き層上にこれらの電極 So、 Dr、 CE1を形成するようにしても よい。次に、有機半導体膜 16のキャパシタ用対向電極 CE1に対応する部分及びそ の周囲部分を除去する有機半導体膜除去工程を行う。この有機半導体膜除去工程 には、有機半導体膜 16上にマスク MS1を形成又は設置するマスク形成工程(図 8a) と、エッチング等によりキャパシタ用対向電極 CE1に対応する部分を除去するエッチ ング工程と、該マスク MS1を除去するマスク除去工程とが含まれる。これにより、有機 半導体膜 16のキャパシタ用対向電極 CE1に対応する部分及びその周囲部分に除 去部が形成される(図 8b)。 8a to 8f are diagrams showing a manufacturing process of an organic composite electronic device including a top gate stagger type transistor and a capacitor. First, a first electrode group forming step is performed in which one of the transistor source electrode So, drain Dr, and capacitor counter electrode CE 1 is formed in the same step on the substrate 11, and the organic semiconductor film 16 is formed thereon. An organic semiconductor film forming step is performed (FIG. 8a). An undercoat layer (not shown) may be formed on the substrate 11, and these electrodes So, Dr, and CE1 may be formed on the undercoat layer. Next, a portion of the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 and its portion. An organic semiconductor film removing step is performed to remove the surrounding portion of the substrate. This organic semiconductor film removing step includes a mask forming step (FIG. 8a) for forming or placing a mask MS1 on the organic semiconductor film 16, and an etching step for removing a portion corresponding to the capacitor counter electrode CE1 by etching or the like. And a mask removing process for removing the mask MS1. As a result, a removal portion is formed in the portion corresponding to the counter electrode CE1 for the capacitor of the organic semiconductor film 16 and its surrounding portion (FIG. 8b).
[0101] 次に、後述の強誘電体膜 17bと比較して低誘電率を有する低誘電体膜 17aを形成 する低誘電体膜形成工程を行う(図 8c。その後、低誘電体膜 17aのキャパシタ用対 向電極 CE1に対応する部分 (その近傍を含んでもよ!/、)を除去する低誘電体膜除去 工程を行う。この低誘電体膜除去工程には、低誘電体膜 17a上にマスク MS2を形成 又は設置するマスク形成工程(図 8c)と、エッチング等によりキャパシタ用対向電極 C E1に対応する部分を除去するエッチング工程と、該マスク MS2を除去するマスク除 去工程とが含まれる。これにより、低誘電体膜 17aのキャパシタ用対向電極 CE1に対 応する部分に除去部が形成される(図 8d)。  [0101] Next, a low dielectric film forming step is performed to form a low dielectric film 17a having a lower dielectric constant than that of a ferroelectric film 17b described later (FIG. 8c. A low dielectric film removal step is performed to remove the portion corresponding to the capacitor counter electrode CE1 (may include the vicinity thereof! /), Which is performed on the low dielectric film 17a. This includes a mask formation step (FIG. 8c) for forming or placing the mask MS2, an etching step for removing a portion corresponding to the capacitor counter electrode CE1 by etching or the like, and a mask removal step for removing the mask MS2. As a result, a removal portion is formed in the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 (FIG. 8d).
[0102] 次に、強誘電体膜 17bを形成する強誘電体膜形成工程を行う(図 8e)。その後、有 機半導体膜 16、低誘電体膜 17a、及び強誘電体膜 17bを挟んでトランジスタ用ソー ス電極 So及びドレイン電極 Drと所定の位置関係でトランジスタを構成するようにトラ ンジスタ用ゲート電極 Gaを、及び強誘電体膜 17bを挟んでキャパシタを構成するよう にキャパシタ用対向電極 CE1に対応してキャパシタ用対向電極 CE2を同一の工程 で形成する第 2電極群形成工程を行う(図 8f)。その後、図示は省略しているが、保 護膜形成工程を行って保護膜を形成する。これにより、低誘電体膜 17a及び強誘電 体膜 17bをゲート絶縁膜 17とした有機薄膜トランジスタ Tr、及び強誘電体膜 17bを 絶縁膜とした高誘電体キャパシタ Caを備える有機複合電子素子が製造される。  Next, a ferroelectric film forming step for forming the ferroelectric film 17b is performed (FIG. 8e). Thereafter, a transistor gate electrode is formed so that the transistor is configured in a predetermined positional relationship with the transistor source electrode So and the drain electrode Dr across the organic semiconductor film 16, the low dielectric film 17a, and the ferroelectric film 17b. A second electrode group forming step is performed in which the capacitor counter electrode CE2 is formed in the same process corresponding to the capacitor counter electrode CE1 so as to constitute a capacitor with Ga and the ferroelectric film 17b interposed therebetween (FIG. 8f). ). After that, although not shown, a protective film is formed by performing a protective film forming step. As a result, an organic composite electronic device including an organic thin film transistor Tr having the low dielectric film 17a and the ferroelectric film 17b as the gate insulating film 17 and a high dielectric capacitor Ca having the ferroelectric film 17b as the insulating film is manufactured. The
[0103] なお、ここでは、有機半導体膜形成工程で有機半導体膜 16を形成した後に、有機 半導体膜除去工程で有機半導体膜 16のキャパシタを形成する部分を除去するよう にしたが、有機半導体膜形成工程でキャパシタを形成する部分を除いて有機半導体 膜 16を形成するようにしてもよい。同様に、低誘電体膜形成工程で低誘電体膜 17a を形成した後に、低誘電体膜除去工程で低誘電体膜 17aのキャパシタを形成する部 分を除去するようにしたが、低誘電体膜形成工程でキャパシタを形成する部分を除 いて低誘電体膜 17aを形成するようにしてもよい。また、低誘電体膜 17aのキャパシタ 用対向電極 CE1に対応する部分の除去は、その厚さ方向の全てではなぐ一部の みを除去するようにしてもよ!/、。 [0103] Here, after forming the organic semiconductor film 16 in the organic semiconductor film forming step, the portion of the organic semiconductor film 16 in which the capacitor is formed is removed in the organic semiconductor film removing step. The organic semiconductor film 16 may be formed except for the part where the capacitor is formed in the forming process. Similarly, after the low dielectric film 17a is formed in the low dielectric film formation step, the capacitor of the low dielectric film 17a is formed in the low dielectric film removal step. However, the low dielectric film 17a may be formed by removing the portion where the capacitor is formed in the low dielectric film forming step. Also, the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 may be removed by removing only a portion of the thickness direction! / ,.
[0104] (2— 1 4)トップゲート'コプレナ一型 [0104] (2 — 1 4) Top gate coplanar type
図 9a〜図 9fは、トップゲート'コプレナ一型 (Top Gate Coplanar type)のトランジスタ 及びキャパシタからなる有機複合電子素子の製造工程を示す図である。まず、基板 1 1上に有機半導体膜 16を形成する有機半導体膜形成工程を行う(図 9a)。なお、基 板 11上に下引き層(不図示)を形成し、該下引き層上にこの有機半導体膜 16を形成 するようにしてもよい。次に、有機半導体膜 16のキャパシタ用対向電極 CE1に対応 する部分及びその周囲部分を除去する有機半導体膜除去工程を行う。この有機半 導体膜除去工程には、有機半導体膜 16上にマスク MS1を形成又は設置するマスク 形成工程(図 9a)と、エッチング等によりキャパシタ用対向電極 CE1に対応する部分 を除去するエッチング工程と、該マスク MS1を除去するマスク除去工程とが含まれる 。これにより、有機半導体膜 16のキャパシタ用対向電極 CE1に対応する部分及びそ の周囲部分に除去部が形成される(図 9b)。その後、トランジスタ用ソース電極 So、ド レイン Dr及びキャパシタ用対向電極の一方 CE1を形成する第 1電極群形成工程を 行う(図 9b)。  FIG. 9a to FIG. 9f are diagrams showing a manufacturing process of an organic composite electronic device including a transistor and a capacitor of a top gate coplanar type. First, an organic semiconductor film forming step for forming the organic semiconductor film 16 on the substrate 11 is performed (FIG. 9a). An undercoat layer (not shown) may be formed on the substrate 11 and the organic semiconductor film 16 may be formed on the undercoat layer. Next, an organic semiconductor film removing step is performed to remove the portion of the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 and the surrounding portion thereof. This organic semiconductor film removal step includes a mask formation step (FIG. 9a) for forming or placing a mask MS1 on the organic semiconductor film 16, and an etching step for removing a portion corresponding to the capacitor counter electrode CE1 by etching or the like. And a mask removing process for removing the mask MS1. As a result, a removal portion is formed in the portion of the organic semiconductor film 16 corresponding to the capacitor counter electrode CE1 and the surrounding portion (FIG. 9b). Thereafter, a first electrode group forming step is performed to form one of the transistor source electrode So, the drain Dr, and the capacitor counter electrode CE1 (FIG. 9b).
[0105] 次に、後述の強誘電体膜 17bと比較して低誘電率を有する低誘電体膜 17aを形成 する低誘電体膜形成工程を行う(図 9c)。その後、低誘電体膜 17aのキャパシタ用対 向電極 CE1に対応する部分 (その近傍を含んでもよ!/、)を除去する低誘電体膜除去 工程を行う。この低誘電体膜除去工程には、低誘電体膜 17a上にマスク MS2を形成 又は設置するマスク形成工程(図 9c)と、エッチング等によりキャパシタ用対向電極 C E1に対応する部分を除去するエッチング工程と、該マスク MS2を除去するマスク除 去工程とが含まれる。これにより、低誘電体膜 17aのキャパシタ用対向電極 CE1に対 応する部分に除去部が形成される(図 9d)。  Next, a low dielectric film forming step for forming a low dielectric film 17a having a lower dielectric constant than that of a ferroelectric film 17b described later is performed (FIG. 9c). Thereafter, a low dielectric film removal step is performed to remove a portion of the low dielectric film 17a corresponding to the counter electrode CE1 for the capacitor (including the vicinity thereof! /). This low dielectric film removal process includes a mask formation process (FIG. 9c) for forming or placing a mask MS2 on the low dielectric film 17a, and an etching process for removing a portion corresponding to the capacitor counter electrode CE1 by etching or the like. A process and a mask removing process for removing the mask MS2. As a result, a removal portion is formed in the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 (FIG. 9d).
[0106] 次に、強誘電体膜 17bを形成する強誘電体膜形成工程を行う(図 )。その後、低 誘電体膜 17a及び強誘電体膜 17bを挟んでトランジスタ用ソース電極 So及びドレイ ン電極 Drと所定の位置関係でトランジスタを構成するようにトランジスタ用ゲートス電 極 Gaを、及び強誘電体膜 17bを挟んでキャパシタを構成するようにキャパシタ用対 向電極 CE1に対応してキャパシタ用対向電極 CE2を同一の工程で形成する第 2電 極群形成工程を行う(図 9f)。その後、図示は省略しているが、保護膜形成工程を行 つて保護膜を形成する。これにより、低誘電体膜 17a及び強誘電体膜 17bをゲート絶 縁膜 17とした有機薄膜トランジスタ Tr、及び強誘電体膜 17bを絶縁膜とした高誘電 体キャパシタ Caを備える有機複合電子素子が製造される。 Next, a ferroelectric film forming step for forming the ferroelectric film 17b is performed (FIG. 1). After that, the transistor source electrode So and drain are sandwiched between the low dielectric film 17a and the ferroelectric film 17b. The transistor gate electrode Ga is configured so as to configure the transistor in a predetermined positional relationship with the transistor electrode Dr, and the capacitor corresponding to the capacitor counter electrode CE1 so as to configure the capacitor sandwiching the ferroelectric film 17b. A second electrode group forming process is performed in which the counter electrode CE2 is formed in the same process (FIG. 9f). Thereafter, although not shown, a protective film is formed by performing a protective film forming step. As a result, an organic composite electronic device including an organic thin film transistor Tr having a low dielectric film 17a and a ferroelectric film 17b as a gate insulating film 17 and a high dielectric capacitor Ca having a ferroelectric film 17b as an insulating film is manufactured. Is done.
[0107] なお、ここでは、有機半導体膜形成工程で有機半導体膜 16を形成した後に、有機 半導体膜除去工程で有機半導体膜 16のキャパシタを形成する部分を除去するよう にしたが、有機半導体膜形成工程でキャパシタを形成する部分及びその周囲部分を 除いて有機半導体膜 16を形成するようにしてもよい。同様に、低誘電体膜形成工程 で低誘電体膜 17aを形成した後に、低誘電体膜除去工程で低誘電体膜 17aのキヤ パシタを形成する部分を除去するようにしたが、低誘電体膜形成工程でキャパシタを 形成する部分を除いて低誘電体膜 17aを形成するようにしてもよい。また、低誘電体 膜 17aのキャパシタ用対向電極 CE1に対応する部分の除去は、その厚さ方向の全て ではなぐ一部のみを除去するようにしてもよい。  Here, after forming the organic semiconductor film 16 in the organic semiconductor film forming step, the portion of the organic semiconductor film 16 in which the capacitor is formed is removed in the organic semiconductor film removing step. The organic semiconductor film 16 may be formed excluding the portion where the capacitor is formed and the surrounding portion in the forming step. Similarly, after forming the low dielectric film 17a in the low dielectric film formation process, the low dielectric film 17a removes the capacitor forming portion of the low dielectric film 17a. The low dielectric film 17a may be formed except for the part where the capacitor is formed in the film forming process. In addition, the portion of the low dielectric film 17a corresponding to the capacitor counter electrode CE1 may be removed by removing only a portion of the thickness in the thickness direction.
[0108] (2— 2)有機半導体膜及びその形成工程  (2-2) Organic semiconductor film and formation process thereof
第 2実施形態の有機複合電子素子の薄膜トランジスタを構成する有機半導体膜の 形成材料やその成膜 (形成)方法等は、上述した第 1実施形態と同様である。  The material for forming the organic semiconductor film constituting the thin film transistor of the organic composite electronic device of the second embodiment, the method of forming (forming) the same, and the like are the same as those of the first embodiment described above.
[0109] (2— 3)電極及びその形成工程  [2109] Electrode and formation process thereof
第 2実施形態の有機複合電子素子の薄膜トランジスタを構成するゲート電極、ソー ス電極及びドレイン電極、並びに高誘電体キャパシタを構成する一対の対向電極の 形成材料、及びその成膜 (形成)方法等は、上述した第 1実施形態と同様である。  The material for forming the gate electrode, the source electrode and the drain electrode constituting the thin film transistor of the organic composite electronic device of the second embodiment, and the pair of counter electrodes constituting the high dielectric capacitor, and the film formation (formation) method thereof are as follows: This is the same as the first embodiment described above.
[0110] (2— 4)絶縁膜及びその形成工程  [2-10] Insulating film and its formation process
第 2実施形態の有機複合電子素子では、トランジスタ用のゲート絶縁膜として、強 誘電体膜と比較して低誘電率を有する低誘電体膜及び強誘電体膜を積層した二層 構造の膜を用い、キャパシタ用の絶縁膜として強誘電体膜力 なる一層の膜を用い る。但し、キャパシタ用の絶縁膜として該トランジスタと同様に低誘電体膜及び強誘電 体膜を積層した二層構造の膜を用いてもよ!/、。低誘電体膜及び強誘電体膜の比誘 電率、形成材料、及びその成膜 (形成)方法等は、上述した第 1実施形態と同様であ In the organic composite electronic device of the second embodiment, a film having a two-layer structure in which a low dielectric film having a low dielectric constant compared to a ferroelectric film and a ferroelectric film are stacked as a gate insulating film for a transistor. A single-layer film having a ferroelectric film force is used as an insulating film for a capacitor. However, as the insulating film for the capacitor, the low dielectric film and the ferroelectric film are the same as the transistor. You can also use a two-layered film with body layers stacked! /. The relative dielectric constant of the low dielectric film and the ferroelectric film, the forming material, the film formation (formation) method, and the like are the same as those in the first embodiment described above.
[0111] なお、上述した除去部を形成する場合の低誘電体膜の形成方法としては、上述し たスピンコート法等を用いて一様な膜を成膜した後に、その上にフォトレジストでマス クパターンを形成し、あるいはメタルマスク等のマスクを設置し、エッチングにより不要 な部分を除去する方法を用いることができる。エッチング法としては、ドライエッチング 、ウエットエッチングのいずれを用いてもよいが、ドライエッチングが好ましい。ドライエ ツチング法としては、ガスエッチング、イオンエッチング、プラズマエッチング、 ICP (In ductively Coupled Plasma誘導結合方式)、ラジカルイオンエッチング(RIE)等を例 示できる。但し、このように成膜後にエッチング等により除去する方法の他、当該除去 部を除いて成膜する方法を用いてもよい。例えば、低誘電体材料の溶液あるいは分 散液を直接インクジェット法等により必要な部分のみに形成してもよいし、不要な部 分をマスクして印刷法等を用いて形成した後に該マスクを除去するようにしてもよい。 [0111] As a method of forming the low dielectric film when forming the removal portion described above, a uniform film is formed by using the spin coating method described above, and then a photoresist is formed thereon. A method can be used in which a mask pattern is formed or a mask such as a metal mask is provided and unnecessary portions are removed by etching. As an etching method, either dry etching or wet etching may be used, but dry etching is preferable. Examples of dry etching methods include gas etching, ion etching, plasma etching, ICP (Inductively Coupled Plasma Inductive Coupling), radical ion etching (RIE), and the like. However, in addition to the method of removing by etching or the like after the film formation, a method of forming a film by removing the removal portion may be used. For example, a solution or a dispersion liquid of a low dielectric material may be formed only on a necessary portion by a direct ink jet method or the like, or after unnecessary portions are masked and formed using a printing method or the like, the mask is formed. You may make it remove.
[0112] (2— 5)保護膜、基板及びその形成工程  [0112] (2-5) Protective film, substrate and formation process thereof
第 2実施形態の有機複合電子素子の保護膜及び基板の形成材料、及その成膜( 形成)方法又は製造方法等は、上述した第 1実施形態と同様である。  The protective film and substrate forming material of the organic composite electronic device of the second embodiment, and the film forming (forming) method or manufacturing method thereof are the same as those of the first embodiment described above.
[0113] (2— 6)下引き層及びその形成方法 [2-13] Undercoat layer and formation method thereof
第 2実施態様の有機複合電子素子においては、基板上に、ポリマー又は無機酸化 物及び無機窒化物から選ばれる化合物を含有する下引き層を設けてもよい。下引き 層の形成材料、及びその成膜 (形成)方法等は、上述した第 1実施形態と同様である  In the organic composite electronic device of the second embodiment, an undercoat layer containing a compound selected from a polymer or an inorganic oxide and an inorganic nitride may be provided on the substrate. The material for forming the undercoat layer, the film formation (formation) method, and the like are the same as in the first embodiment described above.
[0114] なお、下引き層に含有される無機酸化物としては、上述した第 1実施形態で例示し た酸化ケィ素、酸化アルミニウム、酸化タンタルの他、酸化チタン、酸化スズ、酸化バ ナジゥム、チタン酸バリウムストロンチウム、ジルコニウム酸チタン酸バリウム、ジルコ二 ゥム酸チタン酸鈴、チタン酸鈴ランタン、チタン酸ストロンチウム、チタン酸バリウム、フ ツイ匕ノ リウムマグネシウム,チタン酸ビスマス、チタン酸ストロンチウムビスマス、タンタ ル酸ストロンチウムビスマス、タンタル酸ニオブ酸ビスマス、トリオキサイドイットリウム等 も例示できる。 [0114] The inorganic oxide contained in the undercoat layer includes titanium oxide, tin oxide, vanadium oxide, as well as the silicon oxide, aluminum oxide, and tantalum oxide exemplified in the first embodiment. Barium strontium titanate, barium zirconate titanate, zirconium titanate bell, lanthanum titanate, strontium titanate, barium titanate, sodium magnesium magnesium, bismuth titanate, strontium bismuth titanate, tantalum Strontium bismuth oxalate, bismuth tantalate niobate, yttrium trioxide, etc. Can also be illustrated.
[0115] 以上のようにして製造される有機複合電子素子は、信号の書き込み特性と電荷を 蓄える特性とを有しており、従って、例えば、メモリ、特に無線伝送タグ用信号回路な どの製造に好適に用いることができる。  [0115] The organic composite electronic device manufactured as described above has a signal writing characteristic and a charge storing characteristic. Therefore, for example, it is suitable for manufacturing a memory, particularly a signal circuit for a wireless transmission tag. It can be used suitably.
[0116] (2— 7)有機半導体メモリ  [0116] (2-7) Organic semiconductor memory
上述したように製造された有機複合電子素子を基板上にマトリックス状に配列形成 することにより、キャパシタタイプの有機半導体メモリを構成することができる。図 10は 1T1C (1トランジスタ · 1キャパシタ)型の有機半導体メモリセルの回路を示す図であ る。なお、センスアンプは図示を省略している。書き込みは、該当するセルの WL (ヮ ード線)をアクティブにして FET (Tr)を ON状態にし、 BL (ビット線)と PL (プレート線 )の間に電圧を印加することで実行される。 BLを Vcc PLを GND (OV)とするとキヤ パシタ Caの上部が + (プラス)、下部が (マイナス)の分極となり「1」が書き込まれ、 BLを GND PLを Vccとするとキャパシタの上部が 下部が +となり「0」が書き込ま れたことになる。なお、本実施形態に係る有機複合電子素子は、このような 1T1C型 の高誘電体メモリセルの他、 2T2C (2トランジスタ · 2キャパシタ)型の高誘電体メモリ セルに適用することも可能である。  A capacitor type organic semiconductor memory can be configured by arranging the organic composite electronic elements manufactured as described above in a matrix on a substrate. FIG. 10 is a diagram showing a circuit of an organic semiconductor memory cell of 1T1C (1 transistor · 1 capacitor) type. The sense amplifier is not shown. Writing is performed by activating the WL (lead line) of the corresponding cell, turning on the FET (Tr), and applying a voltage between BL (bit line) and PL (plate line). . When BL is Vcc PL is GND (OV), the upper part of the capacitor Ca is + (plus) and the lower part is (minus) polarization, and "1" is written. When BL is GND PL and Vcc, the upper part of the capacitor is at the bottom. Becomes + and "0" is written. The organic composite electronic device according to the present embodiment can be applied to a 2T2C (2-transistor / 2-capacitor) type high-dielectric memory cell in addition to such a 1T1C-type high-dielectric memory cell. .
[0117] (3)第 3実施形態  [0117] (3) Third Embodiment
以下、第 3実施形態として、上述した本発明の第 3の観点に対応する有機複合電子 素子、有機複合電子素子の製造方法、及び有機複合電子素子を用いる強誘電体メ モリの実施形態について説明する。  Hereinafter, as a third embodiment, an embodiment of an organic composite electronic device corresponding to the above-described third aspect of the present invention, a method for manufacturing the organic composite electronic device, and a ferroelectric memory using the organic composite electronic device will be described. To do.
[0118] (3 1)有機複合電子素子の全体構成  [0118] (3 1) Overall structure of organic composite electronic device
(3 1 1)ボトムゲート'スタガー型  (3 1 1) Bottom gate 'Stagger type
図 11a〜図 l lfは、ボトムゲート'スタガー型 (Bottom Gate Stagger type)のトランジス タを備える有機複合電子素子の製造工程を示す図である。まず、基板 11上に第 1ト ランジスタ用ゲート電極 Gal及び第 2トランジスタ用ゲート電極 Ga2を同一の工程で 形成する第 1電極群形成工程を行う(図 11a)。なお、基板 11上に下引き層(不図示) を形成し、該下引き層上にこれらの電極 Gal Ga2を形成するようにしてもよい。次に 、これらの電極 Gal Ga2を含む基板 11上(下引き層を形成した場合には該下引き 層上)に絶縁膜 17を形成する絶縁膜形成工程を行う(図 l lb)。この絶縁膜形成ェ 程には、強誘電体膜 17bを形成する強誘電体膜形成工程、及び強誘電体膜 17b上 に低誘電率を有する低誘電体膜 17aを形成する低誘電体膜形成工程が含まれる。 FIGS. 11a to l lf are diagrams illustrating a manufacturing process of an organic composite electronic device including a bottom gate stagger type transistor. First, a first electrode group forming step is performed in which the first transistor gate electrode Gal and the second transistor gate electrode Ga2 are formed on the substrate 11 in the same step (FIG. 11a). An undercoat layer (not shown) may be formed on the substrate 11, and these electrodes GalGa2 may be formed on the undercoat layer. Next, on the substrate 11 containing these electrodes Gal Ga2 (if an undercoat layer is formed, the undercoat An insulating film forming step for forming an insulating film 17 on the layer is performed (FIG. 1 lb). In this insulating film forming process, a ferroelectric film forming step for forming the ferroelectric film 17b, and a low dielectric film formation for forming the low dielectric film 17a having a low dielectric constant on the ferroelectric film 17b are performed. A process is included.
[0119] 次に、第 2トランジスタ用ゲート電極 Ga2と所定の位置関係で後述のソース'ドレイン 電極を形成するために低誘電体膜 17aの一部を除去する低誘電体膜除去工程を行 う。この低誘電体膜除去工程には、低誘電体膜 17a上にマスク MSを形成又は設置 するマスク形成工程(図 11c)と、エッチング等により前記低誘電体膜 17aの一部を除 去するエッチング工程と、該マスク MSを除去するマスク除去工程とが含まれる。これ により、第 2トランジスタ用ゲート電極 Ga2と所定の位置関係で後述のソース'ドレイン 電極を形成するための低誘電体膜 17aの除去部が形成される(図 l id)。その後、低 誘電体膜 17a上に有機半導体膜 16を形成する有機半導体膜形成工程を行う(図 11 e)。 [0119] Next, a low dielectric film removal step is performed to remove a part of the low dielectric film 17a in order to form a later-described source / drain electrode in a predetermined positional relationship with the second transistor gate electrode Ga2. . This low dielectric film removal process includes a mask formation process (FIG. 11c) for forming or placing a mask MS on the low dielectric film 17a, and an etching process for removing a part of the low dielectric film 17a by etching or the like. A step and a mask removing step of removing the mask MS. As a result, a removal portion of the low dielectric film 17a for forming a later-described source / drain electrode in a predetermined positional relationship with the second transistor gate electrode Ga2 is formed (FIG. Id). Thereafter, an organic semiconductor film forming step for forming the organic semiconductor film 16 on the low dielectric film 17a is performed (FIG. 11e).
[0120] 次に、強誘電体膜 17b、低誘電体膜 17a及び有機半導体膜 16を挟んで第 1トラン ジスタ用ゲート電極 Galと所定の位置関係でトランジスタを構成するように第 1トラン ジスタ用ソース電極 Sol、ドレイン電極 Drlを、及び強誘電体膜 17bと有機半導体膜 16とを挟んで第 2トランジスタ用ゲート電極 Ga2と所定の位置関係でトランジスタを構 成するように第 2トランジスタ用ソース電極 So2、ドレイン電極 Dr2を同一の工程で形 成する第 2電極群形成工程を行う(図 1 If)。その後、図示は省略しているが、保護膜 形成工程を行って保護膜を形成する。これにより、強誘電体膜 17b及び低誘電体膜 17aをゲート絶縁膜 17とした有機薄膜トランジスタ Trl、及び強誘電体膜 17bをグー ト絶縁膜とした有機薄膜トランジスタ Tr2を備える有機複合電子素子が製造される。  [0120] Next, for the first transistor, a transistor is configured in a predetermined positional relationship with the gate electrode Gal for the first transistor across the ferroelectric film 17b, the low dielectric film 17a, and the organic semiconductor film 16. Source electrode Sol, drain electrode Drl, and second transistor source electrode so that the transistor is configured in a predetermined positional relationship with second transistor gate electrode Ga2 across ferroelectric film 17b and organic semiconductor film 16 A second electrode group forming process is performed in which So2 and drain electrode Dr2 are formed in the same process (FIG. 1, If). Thereafter, although not shown, a protective film is formed by performing a protective film forming step. As a result, an organic composite electronic device including an organic thin film transistor Trl using the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and an organic thin film transistor Tr2 using the ferroelectric film 17b as the gate insulating film is manufactured. The
[0121] なお、ここでは、低誘電体膜形成工程で低誘電体膜 17aを成膜した後に、低誘電 体膜 17aの第 2トランジスタを形成する部分 (前記低誘電体膜 17aの一部)を除去す るようにしたが、低誘電体膜形成工程で第 2トランジスタを形成する部分を除いて低 誘電体膜 17aを形成するようにしてもよい。また、低誘電体膜除去工程では前記低誘 電体膜 17aの一部の除去は、その厚さ方向の全てではなぐ一部のみを除去するよう にしてもよい。  [0121] Here, after forming the low dielectric film 17a in the low dielectric film formation step, the portion of the low dielectric film 17a where the second transistor is formed (part of the low dielectric film 17a) However, the low dielectric film 17a may be formed except for the portion where the second transistor is formed in the low dielectric film formation step. In the low dielectric film removal step, a part of the low dielectric film 17a may be removed not only in the thickness direction.
[0122] (3— 1 2)ボトムゲート'コプレナ一型 図 12a〜図 12fは、ボトムゲート'コプレナ一型 (Bottom Gate Coplanar type)のトラン ジスタを備える有機複合電子素子の製造工程を示す図である。まず、基板 11上に第 1トランジスタ用ゲート電極 Gal及び第 2トランジスタ用ゲート電極 Ga2を同一の工程 で形成する第 1電極群形成工程を行う(図 12a)。なお、基板 11上に下引き層(不図 示)を形成し、該下引き層上にこれらの電極 Gal、 Ga2を形成するようにしてもよい。 次に、これらの電極 Gal、 Ga2を含む基板 11上(下引き層を形成した場合には該下 引き層上)に絶縁膜 17を形成する絶縁膜形成工程を行う(図 12b)。この絶縁膜形成 工程には、強誘電体膜 17bを形成する強誘電体膜形成工程、及び強誘電体膜 17b 上に低誘電率を有する低誘電体膜 17aを形成する低誘電体膜形成工程が含まれる[0122] (3 — 1 2) Bottom Gate 'Coplanar Type 1 FIGS. 12a to 12f are diagrams illustrating a manufacturing process of an organic composite electronic device including a bottom gate coplanar type transistor. First, a first electrode group forming process is performed in which the first transistor gate electrode Gal and the second transistor gate electrode Ga2 are formed on the substrate 11 in the same process (FIG. 12a). An undercoat layer (not shown) may be formed on the substrate 11, and these electrodes Gal and Ga2 may be formed on the undercoat layer. Next, an insulating film forming step is performed in which an insulating film 17 is formed on the substrate 11 including these electrodes Gal and Ga2 (on the undercoat layer when the undercoat layer is formed) (FIG. 12b). The insulating film forming process includes a ferroelectric film forming process for forming the ferroelectric film 17b and a low dielectric film forming process for forming the low dielectric film 17a having a low dielectric constant on the ferroelectric film 17b. Is included
Yes
[0123] 次に、第 2トランジスタ用ゲート電極 Ga2と所定の位置関係で後述のソース'ドレイン 電極を形成するために低誘電体膜 17aの一部を除去する低誘電体膜除去工程を行 う。この低誘電体膜除去工程には、低誘電体膜 17a上にマスク MSを形成又は設置 するマスク形成工程(図 12c)と、エッチング等により前記低誘電体膜 17aの一部を除 去するエッチング工程と、該マスク MSを除去するマスク除去工程とが含まれる。これ により、第 2トランジスタ用ゲート電極 Ga2と所定の位置関係で後述のソース'ドレイン 電極を形成するための低誘電体膜 17aの除去部が形成される(図 12d)。  [0123] Next, a low dielectric film removal step is performed to remove a part of the low dielectric film 17a in order to form a later-described source / drain electrode in a predetermined positional relationship with the second transistor gate electrode Ga2. . This low dielectric film removal process includes a mask formation process (FIG. 12c) for forming or placing a mask MS on the low dielectric film 17a, and an etching process for removing a part of the low dielectric film 17a by etching or the like. A step and a mask removing step of removing the mask MS. As a result, a removed portion of the low dielectric film 17a for forming a later-described source / drain electrode in a predetermined positional relationship with the second transistor gate electrode Ga2 is formed (FIG. 12d).
[0124] その後、強誘電体膜 17b及び低誘電体膜 17aを挟んで第 1トランジスタ用ゲート電 極 Galと所定の位置関係でトランジスタを構成するように第 1トランジスタ用ソース電 極 Sol、ドレイン電極 Drlを、及び強誘電体膜 17bを挟んで第 2トランジスタ用ゲート 電極 Ga2と所定の位置関係でトランジスタを構成するように第 2トランジスタ用ソース 電極 So2、ドレイン電極 Dr2を同一の工程で形成する第 2電極群形成工程を行う(図 12e) 0次に、各電極 Sol、 Drl、 So2、 Dr2を含む低誘電体膜 17a上に有機半導体 膜 16を形成する有機半導体膜形成工程を行う(図 12f)。その後、図示は省略してい るが、保護膜形成工程を行って保護膜を形成する。これにより、強誘電体膜 17b及び 低誘電体膜 17aをゲート絶縁膜 17とした有機薄膜トランジスタ Trl、及び強誘電体膜 17bをゲート絶縁膜とした有機薄膜トランジスタ Tr2を備える有機複合電子素子が製 造される。 [0125] なお、ここでは、低誘電体膜形成工程で低誘電体膜 17aを成膜した後に、低誘電 体膜 17aの第 2トランジスタを形成する部分 (前記低誘電体膜 17aの一部)を除去す るようにしたが、低誘電体膜形成工程で第 2トランジスタを形成する部分を除いて低 誘電体膜 17aを形成するようにしてもよい。また、低誘電体膜除去工程では前記低誘 電体膜 17aの一部の除去は、その厚さ方向の全てではなぐ一部のみを除去するよう にしてもよい。 [0124] Thereafter, the first transistor source electrode Sol and the drain electrode are formed so as to form a transistor in a predetermined positional relationship with the first transistor gate electrode Gal across the ferroelectric film 17b and the low dielectric film 17a. The second transistor source electrode So2 and the drain electrode Dr2 are formed in the same process so that the transistor is configured in a predetermined positional relationship with the second transistor gate electrode Ga2 across the Drl and the ferroelectric film 17b. performing two electrodes forming step (Fig. 12e) 0 Next, each electrode Sol, Drl, So2, performs the organic semiconductor film forming step of forming an organic semiconductor film 16 on the low dielectric film 17a containing Dr2 (Figure 12f ). Thereafter, although not shown, a protective film is formed by performing a protective film forming step. As a result, an organic composite electronic device including the organic thin film transistor Trl having the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and the organic thin film transistor Tr2 having the ferroelectric film 17b as the gate insulating film is manufactured. The [0125] Here, after forming the low dielectric film 17a in the low dielectric film formation step, the portion of the low dielectric film 17a where the second transistor is formed (part of the low dielectric film 17a) However, the low dielectric film 17a may be formed except for the portion where the second transistor is formed in the low dielectric film formation step. In the low dielectric film removal step, a part of the low dielectric film 17a may be removed not only in the thickness direction.
[0126] (3— 1 3)トップゲート'スタガー型  [0126] (3 — 1 3) Top gate stagger type
図 13a〜図 13fは、トップゲート'スタガー型 (Top Gate Stagger type)のトランジスタ を備える有機複合電子素子の製造工程を示す図である。まず、基板 11上に第 1トラ ンジスタ用ソース電極 Sol、ドレイン電極 Drl及び第 2トランジスタ用ソース電極 So2 、ドレイン電極 Dr2を同一の工程で形成する第 1電極群形成工程を行う(図 13a)。な お、基板 11上に下引き層(不図示)を形成し、該下引き層上にこれらの電極 Sol、Dr 1、 So2、 Dr2を形成するようにしてもよい。次に、これらの電極 Sol、 Drl , So2、 Dr 2を含む基板 11上 (下引き層を形成した場合には該下引き層上)に、有機半導体膜 16を形成する有機半導体膜形成工程、及び低誘電体膜 17aを形成する低誘電体 膜形成工程を行う(図 13b)。  FIG. 13a to FIG. 13f are diagrams illustrating a manufacturing process of an organic composite electronic device including a top gate stagger type transistor. First, a first electrode group forming process is performed in which the first transistor source electrode Sol, the drain electrode Drl, the second transistor source electrode So2, and the drain electrode Dr2 are formed on the substrate 11 in the same process (FIG. 13a). An undercoat layer (not shown) may be formed on the substrate 11, and these electrodes Sol, Dr1, So2, and Dr2 may be formed on the undercoat layer. Next, an organic semiconductor film forming step of forming the organic semiconductor film 16 on the substrate 11 containing these electrodes Sol, Drl, So2, Dr 2 (on the undercoat layer when the undercoat layer is formed), Then, a low dielectric film forming step for forming the low dielectric film 17a is performed (FIG. 13b).
[0127] 次に、第 2トランジスタ用ソース電極 So2、ドレイン電極 Dr2と所定の位置関係で後 述のゲート電極を形成するために低誘電体膜 17aの一部を除去する低誘電体膜除 去工程を行う。この低誘電体膜除去工程には、低誘電体膜 17a上にマスク MSを形 成又は設置するマスク形成工程(図 13c)と、エッチング等により前記低誘電体膜 17a の一部を除去するエッチング工程と、該マスク MSを除去するマスク除去工程とが含 まれる。これにより、第 2トランジスタ用ソース電極 So2、ドレイン電極 Dr2と所定の位 置関係で後述のゲート電極を形成するための低誘電体膜 17aの除去部が形成され る(図 13d)。その後、除去部を含む低誘電体膜 17a上に強誘電体膜 17bを形成する 強誘電体膜形成工程を行う(図 13e)。  [0127] Next, the low dielectric film removal is performed to remove a part of the low dielectric film 17a in order to form the gate electrode described later in a predetermined positional relationship with the source electrode So2 and the drain electrode Dr2 for the second transistor. Perform the process. This low dielectric film removal step includes a mask formation step (FIG. 13c) for forming or placing a mask MS on the low dielectric film 17a, and an etching for removing a part of the low dielectric film 17a by etching or the like. And a mask removing step for removing the mask MS. As a result, a removal portion of the low dielectric film 17a for forming a gate electrode described later in a predetermined positional relationship with the source electrode So2 and the drain electrode Dr2 for the second transistor is formed (FIG. 13d). Thereafter, a ferroelectric film forming step of forming a ferroelectric film 17b on the low dielectric film 17a including the removed portion is performed (FIG. 13e).
[0128] 次に、有機半導体膜 16、低誘電体膜 17a、及び強誘電体膜 17bを挟んで第 1トラ ンジスタ用ソース電極 Sol、ドレイン電極 Drlと所定の位置関係でトランジスタを構成 するように第 1トランジスタ用ゲート電極 Galを、及び強誘電体膜 17bと有機半導体 膜 16とを挟んで第 2トランジスタ用ソース電極 So2、ドレイン電極 Dr2と所定の位置関 係でトランジスタを構成するように第 2トランジスタ用ゲート電極 Ga2を同一の工程で 形成する第 2電極群形成工程を行う(図 13f)。その後、図示は省略しているが、保護 膜形成工程を行って保護膜を形成する。これにより、強誘電体膜 17b及び低誘電体 膜 17aをゲート絶縁膜 17とした有機薄膜トランジスタ Trl、及び強誘電体膜 17bをゲ ート絶縁膜とした有機薄膜トランジスタ Tr2を備える有機複合電子素子が製造されるNext, a transistor is configured in a predetermined positional relationship with the source electrode Sol and the drain electrode Drl for the first transistor across the organic semiconductor film 16, the low dielectric film 17a, and the ferroelectric film 17b. First transistor gate electrode Gal, ferroelectric film 17b and organic semiconductor Second electrode group forming step in which the second transistor gate electrode Ga2 is formed in the same process so as to form a transistor with a predetermined positional relationship with the second transistor source electrode So2 and drain electrode Dr2 across the film 16. (Fig. 13f). Thereafter, although not shown, a protective film is formed by performing a protective film forming step. As a result, an organic composite electronic device including an organic thin film transistor Trl using the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and an organic thin film transistor Tr2 using the ferroelectric film 17b as the gate insulating film is manufactured. Be done
Yes
[0129] なお、ここでは、低誘電体膜形成工程で低誘電体膜 17aを成膜した後に、低誘電 体膜 17aの第 2トランジスタを形成する部分 (前記低誘電体膜 17aの一部)を除去す るようにしたが、低誘電体膜形成工程で第 2トランジスタを形成する部分を除いて低 誘電体膜 17aを形成するようにしてもよい。また、低誘電体膜除去工程では前記低誘 電体膜 17aの一部の除去は、その厚さ方向の全てではなぐ一部のみを除去するよう にしてもよい。  Here, after forming the low dielectric film 17a in the low dielectric film formation step, the portion of the low dielectric film 17a where the second transistor is formed (part of the low dielectric film 17a) However, the low dielectric film 17a may be formed except for the portion where the second transistor is formed in the low dielectric film formation step. In the low dielectric film removal step, a part of the low dielectric film 17a may be removed not only in the thickness direction.
[0130] (3— 1 4)トップゲート'コプレナ一型  [0130] (3 — 1 4) Top gate coplanar type
図 14a〜図 14fは、トップゲート'コプレナ一型 (Top Gate Coplanar type)のトランジ スタを備える有機複合電子素子の製造工程を示す図である。まず、基板 1 1上に、有 機半導体膜 16を形成する有機半導体膜形成工程を行い、その上に第 1トランジスタ 用ソース電極 Sol、ドレイン電極 Drl及び第 2トランジスタ用ソース電極 So2、ドレイン 電極 Dr2を同一の工程で形成する第 1電極群形成工程を行う(図 14a)。なお、基板 11上に下引き層(不図示)を形成し、該下引き層上に有機半導体膜 16を形成するよ うにしてもよい。その後、これらの電極 Sol、 Drl , So2、 Dr2を含む有機半導体膜 16 上に、低誘電体膜 17aを形成する低誘電体膜形成工程を行う(図 14b)。  FIG. 14a to FIG. 14f are diagrams illustrating a manufacturing process of an organic composite electronic device including a transistor of a top gate coplanar type. First, the organic semiconductor film forming process for forming the organic semiconductor film 16 is performed on the substrate 11, and then the source electrode Sol for the first transistor, the drain electrode Drl, the source electrode So2 for the second transistor, the drain electrode Dr2 A first electrode group forming step is performed in which the steps are formed in the same step (FIG. 14a). An undercoat layer (not shown) may be formed on the substrate 11 and the organic semiconductor film 16 may be formed on the undercoat layer. Thereafter, a low dielectric film forming step for forming a low dielectric film 17a on the organic semiconductor film 16 containing these electrodes Sol, Drl, So2, and Dr2 is performed (FIG. 14b).
[0131] 次に、第 2トランジスタ用ソース電極 So2、ドレイン電極 Dr2と所定の位置関係で後 述のゲート電極を形成するために低誘電体膜 17aの一部を除去する低誘電体膜除 去工程を行う。この低誘電体膜除去工程には、低誘電体膜 17a上にマスク MSを形 成又は設置するマスク形成工程(図 14c)と、エッチング等により前記低誘電体膜 17a の一部を除去するエッチング工程と、該マスク MSを除去するマスク除去工程とが含 まれる。これにより、第 2トランジスタ用ソース電極 So2、ドレイン電極 Dr2と所定の位 置関係で後述のゲート電極を形成するための低誘電体膜 17aの除去部が形成され る(図 14d)。その後、除去部を含む低誘電体膜 17a上に強誘電体膜 17bを形成する 強誘電体膜形成工程を行う(図 14e)。 [0131] Next, the low dielectric film removal is performed to remove a part of the low dielectric film 17a in order to form the gate electrode described later in a predetermined positional relationship with the source electrode So2 and the drain electrode Dr2 for the second transistor. Perform the process. This low dielectric film removal process includes a mask formation process (FIG. 14c) for forming or placing a mask MS on the low dielectric film 17a, and an etching process for removing a part of the low dielectric film 17a by etching or the like. And a mask removing step for removing the mask MS. As a result, the second transistor source electrode So2 and drain electrode Dr2 Due to the arrangement, a removed portion of the low dielectric film 17a for forming a gate electrode described later is formed (FIG. 14d). Thereafter, a ferroelectric film forming step of forming a ferroelectric film 17b on the low dielectric film 17a including the removed portion is performed (FIG. 14e).
[0132] 次に、低誘電体膜 17a及び強誘電体膜 17bを挟んで第 1トランジスタ用ソース電極 Sol ,ドレイン電極 Drlと所定の位置関係でトランジスタを構成するように第 1トランジ スタ用ゲート電極 Galを、及び強誘電体膜 17bを挟んで第 2トランジスタ用ソース電 極 So2、ドレイン電極 Dr2と所定の位置関係でトランジスタを構成するように第 2トラン ジスタ用ゲート電極 Ga2を同一の工程で形成する第 2電極群形成工程を行う(図 14f )。その後、図示は省略しているが、保護膜形成工程を行って保護膜を形成する。こ れにより、強誘電体膜 17b及び低誘電体膜 17aをゲート絶縁膜 17とした有機薄膜ト ランジスタ Trl、及び強誘電体膜 17bをゲート絶縁膜とした有機薄膜トランジスタ Tr2 を備える有機複合電子素子が製造される。  [0132] Next, the first transistor gate electrode is configured so that the transistor is configured in a predetermined positional relationship with the first transistor source electrode Sol and the drain electrode Drl with the low dielectric film 17a and the ferroelectric film 17b interposed therebetween. The second transistor gate electrode Ga2 is formed in the same process so that the transistor is configured in a predetermined positional relationship with the source electrode So2 and drain electrode Dr2 of the second transistor across Gal and the ferroelectric film 17b. The second electrode group forming step is performed (FIG. 14f). Then, although illustration is abbreviate | omitted, a protective film formation process is performed and a protective film is formed. Thus, an organic composite electronic device including an organic thin film transistor Trl having the ferroelectric film 17b and the low dielectric film 17a as the gate insulating film 17 and an organic thin film transistor Tr2 having the ferroelectric film 17b as the gate insulating film is obtained. Manufactured.
[0133] なお、ここでは、低誘電体膜形成工程で低誘電体膜 17aを形成した後に、低誘電 体膜 17aの第 2トランジスタを形成する部分 (前記低誘電体膜 17aの一部)を除去す るようにしたが、低誘電体膜形成工程で第 2トランジスタを構成する部分を除いて低 誘電体膜 17aを形成するようにしてもよい。また、低誘電体膜除去工程では前記低誘 電体膜 17aの一部の除去は、その厚さ方向の全てではなぐ一部のみを除去するよう にしてもよい。  [0133] Here, after forming the low dielectric film 17a in the low dielectric film formation step, a portion of the low dielectric film 17a for forming the second transistor (a part of the low dielectric film 17a) is formed. Although removed, the low dielectric film 17a may be formed in the low dielectric film forming step except for the portion constituting the second transistor. In the low dielectric film removal step, a part of the low dielectric film 17a may be removed not only in the thickness direction.
[0134] (3— 2)有機半導体膜及びその形成工程  (3-2) Organic semiconductor film and formation process thereof
第 3実施形態の有機複合電子素子の有機薄膜トランジスタを構成する有機半導体 膜の形成材料やその成膜 (形成)方法等は、上述した第 1又は第 2実施形態と同様 である。  The material for forming the organic semiconductor film constituting the organic thin film transistor of the organic composite electronic device of the third embodiment, the film formation (formation) method, and the like are the same as those in the first or second embodiment described above.
[0135] (3— 3)電極及びその形成工程  [3-3] Electrode and formation process thereof
第 3実施形態の有機複合電子素子の第 1及び第 2有機薄膜トランジスタをそれぞれ 構成するゲート電極、ソース電極及びドレイン電極の形成材料、及びその成膜 (形成 )方法は上述した第 1又は第 2実施形態と同様である。  The material for forming the gate electrode, the source electrode and the drain electrode, and the method for forming (forming) the first and second organic thin film transistors constituting the first and second organic thin film transistors of the organic composite electronic device of the third embodiment are the same as those described in the first or second embodiment. It is the same as the form.
[0136] (3— 4)絶縁膜及びその形成工程 [0136] (3-4) Insulating film and formation process thereof
第 3実施形態の有機複合電子素子では、第 1トランジスタ用のゲート絶縁膜として、 低い誘電率を有する低誘電体膜及び強誘電体膜を積層した二層構造の膜を用い、 第 2トランジスタ用のゲート絶縁膜として強誘電体膜力もなる一層の膜を用いる。低誘 電体膜及び強誘電体膜の比誘電率、形成材料、及びその成膜 (形成)方法等は、上 述した第 1又は第 2実施形態と同様である。なお、上述した除去部を形成する場合の 低誘電体膜の形成方法としては、上述した第 2実施形態で説明したのと同様の方法 を用いるようにしてもよい。 In the organic composite electronic device of the third embodiment, as a gate insulating film for the first transistor, A two-layered film in which a low dielectric constant film having a low dielectric constant and a ferroelectric film are stacked is used, and a single layer film having a ferroelectric film force is used as a gate insulating film for the second transistor. The relative dielectric constant, the forming material, the film forming (forming) method, and the like of the low dielectric film and the ferroelectric film are the same as those in the first or second embodiment described above. As a method for forming the low dielectric film when forming the removal portion described above, the same method as described in the second embodiment may be used.
[0137] (3— 5)保護膜、基板及びその形成工程  [0137] (3-5) Protective film, substrate and formation process thereof
第 3実施形態の有機複合電子素子の保護膜及び基板の形成材料、及びその成膜 (形成)方法又は製造方法等は、上述した第 1又は第 2実施形態と同様である。  The material for forming the protective film and substrate of the organic composite electronic device of the third embodiment, the film forming (forming) method, the manufacturing method, and the like are the same as those in the first or second embodiment described above.
[0138] (3— 6)下引き層及びその形成方法  (3-6) Undercoat layer and formation method thereof
第 3実施態様の有機複合電子素子においては、基板上に、ポリマー又は無機酸化 物及び無機窒化物から選ばれる化合物を含有する下引き層を設けてもよい。下引き 層の形成材料、及びその成膜 (形成)方法等は、上述した第 1又は第 2実施形態と同 様である。  In the organic composite electronic device of the third embodiment, an undercoat layer containing a compound selected from a polymer or an inorganic oxide and an inorganic nitride may be provided on the substrate. The material for forming the undercoat layer, the film formation (formation) method, and the like are the same as those in the first or second embodiment described above.
[0139] (3— 7)強誘電体メモリ  [0139] (3-7) Ferroelectric memory
上述したように製造された有機複合電子素子の第 2トランジスタは、 1T (1トランジス タ)型の強誘電体メモリ素子として用いることができ、該有機複合電子素子を基板上 にマトリックス状に配列形成することにより、強誘電体メモリ (FeRAM:Ferroelectric Ran dom Access Memory)を構成することができる。図 15は IT型の強誘電体メモリ素子の 回路を示す図である。同図において、 BLはビット線を、 WLはワード線、 Tr2は第 2有 機薄膜トランジスタである。なお、センスアンプは図示を省略している。上述した有機 複合電子素子の第 1トランジスタを駆動トランジスタとして用いることにより、 1DT/1 TFeRAM ( 1駆動トランジスタ / 1トランジスタ強誘電体メモリ )を構成することも可能 である。  The second transistor of the organic composite electronic device manufactured as described above can be used as a 1T (1 transistor) type ferroelectric memory device, and the organic composite electronic device is arranged in a matrix on the substrate. By doing so, a ferroelectric memory (FeRAM: Ferroelectric Random Access Memory) can be configured. FIG. 15 is a diagram showing a circuit of an IT type ferroelectric memory element. In the figure, BL is a bit line, WL is a word line, and Tr2 is a second organic thin film transistor. The sense amplifier is not shown. By using the first transistor of the organic composite electronic element described above as a drive transistor, it is possible to configure a 1DT / 1 TFeRAM (1 drive transistor / 1 transistor ferroelectric memory).
実施例  Example
[0140] 以下、本発明の実施例を具体的に説明する。本実施例では、本発明を適用して、 図 2aに示すようなボトムゲート'スタガー型の有機薄膜トランジスタ (TFT)を備える有 機電子素子を製造した。また、図 6fに示すようなボトムゲート'スタガー型の有機薄膜 トランジスタ (Tr)及び高誘電体キャパシタ(Ca)を備える有機複合電子素子を製造し た。さらに、図 1 Ifに示すようなボトムゲート'スタガー型の 2つの有機薄膜トランジスタ (Trl , Tr2)を備える有機複合電子素子を製造した。 [0140] Examples of the present invention will be specifically described below. In this example, the present invention was applied to manufacture an organic electronic device including a bottom-gate staggered organic thin film transistor (TFT) as shown in FIG. 2a. Also, bottom gate staggered organic thin film as shown in Figure 6f An organic composite electronic device with a transistor (Tr) and a high dielectric capacitor (Ca) was manufactured. Furthermore, an organic composite electronic device having two bottom gate / stagger type organic thin film transistors (Trl, Tr2) as shown in FIG. 1 If was manufactured.
[0141] それぞれにおいて、基板として、ポリエチレンテレフタレートフィルム基板(25mm X lOmm X O. 5mmの大きさ)を用いた。ゲート電極(及びコンデンサ用電極)は基板 上にアルミニウムを蒸着して形成した。アルミニウムの蒸着は、真空度が 1 X 10- 2P a未満、基板の温度が RT (室温)で、膜厚が約 200nmになるように行った。  [0141] In each case, a polyethylene terephthalate film substrate (25 mm x 10 mm x O. 5 mm in size) was used as the substrate. The gate electrode (and capacitor electrode) was formed by vapor-depositing aluminum on the substrate. The aluminum was deposited so that the degree of vacuum was less than 1 × 10-2 Pa, the substrate temperature was RT (room temperature), and the film thickness was about 200 nm.
[0142] 二層構造を有する絶縁膜の 1層目である強誘電体膜は、シァノエチル化セルロー ス (信越化学社製:シァノレジン CR— S (商品名))をシクロペンタノンに溶解させて、 3〜 7重量%の濃度の溶液を製造した。この溶液を、回転数 3000rpmで 30秒間、ス ピンコート法を用いて塗布し、 100°Cで 2分間、乾燥させることにより形成した。この強 誘電体膜の膜厚は約 300nm、比誘電率は 17であった。  [0142] The ferroelectric film, which is the first layer of the insulating film having a two-layer structure, is prepared by dissolving cyanoethylated cellulose (manufactured by Shin-Etsu Chemical Co., Ltd .: Cyanoresin CR—S (trade name)) in cyclopentanone Solutions with a concentration of 3-7% by weight were produced. This solution was formed by applying the spin coat method at a rotational speed of 3000 rpm for 30 seconds and drying at 100 ° C. for 2 minutes. This ferroelectric film had a thickness of about 300 nm and a relative dielectric constant of 17.
[0143] 絶縁膜の 2層目である低誘電体膜は、脂環式ォレフインポリマー(日本ゼオン社製: ZEONEX (登録商標) 480R)の 5%シクロへキサン溶液 5mlを回転数 5000rpmで 3 0秒間、スピンコート法を用いて塗布し、 60°Cで 2分間、乾燥させることにより形成した 。この低誘電体膜の膜厚は約 300nm、比誘電率は 2. 2であった。  [0143] The low dielectric film which is the second layer of the insulating film is a 5% cyclohexane solution of alicyclic olefin polymer (manufactured by Nippon Zeon Co., Ltd .: ZEONEX (registered trademark) 480R) at a rotational speed of 5000 rpm. It was formed by applying for 30 seconds using a spin coating method and drying at 60 ° C. for 2 minutes. The thickness of this low dielectric film was about 300 nm and the relative dielectric constant was 2.2.
[0144] 有機半導体膜は、絶縁膜上にペンタセンを蒸着して形成した。ペンタセンの蒸着は 、真空度が 2 X 10— 3Pa未満、基板温度が RT (室温)、蒸着温度が 185°C、蒸着速 度が 0. 06nm/sで膜厚が約 50nmになるように行った。ソース電極及びドレイン電 極(W= 5mm; L = 20— 70 m)は、有機半導体膜上にメタルマスクを覆い、そこに 金を蒸着して形成した。金の蒸着は、真空度が 1 X 10— 2Pa未満、基板の温度が R T (室温)で、膜厚が約 200nmになるように行った。  [0144] The organic semiconductor film was formed by vapor-depositing pentacene on the insulating film. Pentacene deposition is performed so that the degree of vacuum is less than 2 X 10-3 Pa, the substrate temperature is RT (room temperature), the deposition temperature is 185 ° C, the deposition rate is 0.06 nm / s, and the film thickness is about 50 nm. It was. The source electrode and drain electrode (W = 5 mm; L = 20-70 m) were formed by covering a metal mask on the organic semiconductor film and depositing gold on it. Gold was deposited so that the degree of vacuum was less than 1 × 10-2 Pa, the substrate temperature was R T (room temperature), and the film thickness was about 200 nm.
[0145] このようにして製造した強誘電体膜及び低誘電体膜の二層の絶縁膜をゲート絶縁 膜とした有機薄膜トランジスタ(有機 TFT)の電気的特性を電流一電圧曲線の測定よ り評価し、その結果を図 16及び図 17に示す。測定装置は R6425 2 Channel C urrent— Voltage Source/Monitorで、ある。  [0145] The electrical characteristics of the organic thin film transistor (organic TFT) using the two-layered insulating film of the ferroelectric film and the low dielectric film manufactured as described above as the gate insulating film were evaluated by measuring the current-voltage curve. The results are shown in FIGS. The measuring device is R6425 2 Channel Current—Voltage Source / Monitor.
[0146] 図 16は、 VGを一定状態で VDを + 10Vと 30Vとの間で変化させたときの VD I D泉図であり、図 17は VDを一定状態( 30V)で VGを + 10Vと 30Vとの間で変 化させたときの VG— ID線図である。これらの結果から、本実施例の強誘電体膜及び 低誘電体膜の二層の絶縁膜をゲート絶縁膜とした有機トランジスタ (Tr, Trl)は、低 V、駆動電圧で動作させることができ、ヒステリシス性の非常に少ない良好な特性をも つことが分かる。 [0146] Fig. 16 is a VD ID fountain diagram when VD is changed between + 10V and 30V with VG kept constant, and Fig. 17 shows VG with + 10V when VD is kept constant (30V). Change between 30V It is a VG-ID diagram when it is made to be. From these results, the organic transistor (Tr, Trl) in which the two-layer insulating film of the ferroelectric film and the low dielectric film of this example is used as a gate insulating film can be operated at a low V and a driving voltage. It can be seen that it has good characteristics with very little hysteresis.
[0147] また、このようにして製造した 2つのトランジスタを有する有機複合電子素子の第 2ト ランジスタ (Tr2)、即ち単層の強誘電体膜をゲート絶縁膜とした有機薄膜トランジスタ (有機 TFT)の電気的特性を電流 電圧曲線の測定より評価し、その結果を図 18に 示す。第 2トランジスタ (Tr2)は、低い駆動電圧で動作させることができ、大きなヒステ リシスを有することから強誘電体メモリに用いて好適であることが分かる。  [0147] Further, the second transistor (Tr2) of the organic composite electronic device having two transistors manufactured as described above, that is, an organic thin film transistor (organic TFT) having a single-layer ferroelectric film as a gate insulating film. The electrical characteristics were evaluated by measuring the current-voltage curve, and the results are shown in Fig.18. It can be seen that the second transistor (Tr2) can be operated with a low driving voltage and has a large hysteresis, so that it is suitable for use in a ferroelectric memory.
[0148] なお、以上説明した各実施形態及び実施例は、本発明の理解を容易にするために 記載されたものであって、本発明を限定するために記載されたものではない。従って 、上記の実施形態又は実施例に開示された各要素は、本発明の技術的範囲に属す る全ての設計変更や均等物をも含む趣旨である。  [0148] It should be noted that the embodiments and examples described above are described for facilitating the understanding of the present invention, and are not described for limiting the present invention. Therefore, each element disclosed in the above embodiment or example is intended to include all design changes and equivalents belonging to the technical scope of the present invention.
[0149] 本開示は、 2006年 11月 27日にそれぞれ提出された日本国特許出願第 2006— 3 19184号、第 2006 319185号、及び第 2006 319186号 ίこ含まれた主題 ίこ関 連し、その開示の全てはここに参照事項として明白に組み込まれる。  [0149] This disclosure relates to Japanese patent application Nos. 2006-3 19184, 2006 319185, and 2006 319186, each filed on November 27, 2006. The entire disclosure of which is expressly incorporated herein by reference.

Claims

請求の範囲 The scope of the claims
[1] 基板上に、ゲート電極、ゲート絶縁膜、有機半導体膜、ソース電極、及びドレイン電 極を備える有機薄膜トランジスタであって、  [1] An organic thin film transistor comprising a gate electrode, a gate insulating film, an organic semiconductor film, a source electrode, and a drain electrode on a substrate,
前記ゲート絶縁膜は、強誘電体膜、及び該強誘電体膜と前記有機半導体膜との間 に介装される、強誘電体膜と比較して低誘電率を有する低誘電体膜を有し、 前記低誘電体膜は、非共有電子対を有する官能基を持たず且つ分子構造内に兀 電子結合を持たない有機高分子化合物を含む有機薄膜トランジスタ。  The gate insulating film includes a ferroelectric film and a low dielectric film having a low dielectric constant compared to the ferroelectric film interposed between the ferroelectric film and the organic semiconductor film. And the said low dielectric material film is an organic thin-film transistor containing the organic polymer compound which does not have a functional group which has an unshared electron pair, and does not have a negative electron bond in molecular structure.
[2] 前記強誘電体膜の比誘電率は 5以上であり、前記低誘電体膜の比誘電率は 4以下 である請求項 1に記載の有機薄膜トランジスタ。  [2] The organic thin film transistor according to [1], wherein the ferroelectric film has a relative dielectric constant of 5 or more, and the low dielectric film has a relative dielectric constant of 4 or less.
[3] さらに保護膜を有する請求項 1又は 2に記載の有機薄膜トランジスタ。 3. The organic thin film transistor according to claim 1 or 2, further comprising a protective film.
[4] 基板上にゲート電極を形成する第 1工程と、 [4] a first step of forming a gate electrode on the substrate;
前記ゲート電極を含む前記基板上に強誘電体膜を形成する第 2工程と、 前記強誘電体膜上に強誘電体膜と比較して低誘電率を有する低誘電体膜を形成 する第 3工程と、  A second step of forming a ferroelectric film on the substrate including the gate electrode; and a third step of forming a low dielectric film having a lower dielectric constant than the ferroelectric film on the ferroelectric film. Process,
前記低誘電体膜上に有機半導体膜を形成する第 4工程と、  A fourth step of forming an organic semiconductor film on the low dielectric film;
前記有機半導体膜上にソース電極及びドレイン電極を形成する第 5工程とを備え、 前記第 3工程は、非共有電子対を有する官能基を持たず且つ分子構造内に兀電 子結合を持たな!/、有機高分子化合物を溶媒に溶かし溶液を得る工程、及び該溶液 を流延させた後、溶媒を除去する工程を有する有機薄膜トランジスタの製造方法。  A fifth step of forming a source electrode and a drain electrode on the organic semiconductor film, wherein the third step does not have a functional group having an unshared electron pair and has no negative electron bond in the molecular structure. ! /, A method for producing an organic thin film transistor, comprising: a step of dissolving an organic polymer compound in a solvent to obtain a solution; and a step of casting the solution and then removing the solvent.
[5] 基板上にマトリクス配列して形成された各画素力 少なくとも 1つの有機 EL素子と、 該有機 EL素子を駆動するための少なくとも 2つの有機薄膜トランジスタとを有し、 該有機薄膜トランジスタの少なくとも 1つが請求項 1又は 2に記載の有機薄膜トラン ジスタである有機 EL表示装置。 [5] Each pixel force formed in a matrix arrangement on a substrate has at least one organic EL element, and at least two organic thin film transistors for driving the organic EL element, and at least one of the organic thin film transistors is An organic EL display device, which is the organic thin film transistor according to claim 1.
[6] 基板上にトランジスタ及びキャパシタを備える有機複合電子素子の製造方法であつ て、 [6] A method of manufacturing an organic composite electronic device comprising a transistor and a capacitor on a substrate,
トランジスタ用第 1電極群及びキャパシタ用第 1電極群を形成する第 1電極群形成 工程と、  A first electrode group forming step for forming a first electrode group for transistors and a first electrode group for capacitors;
強誘電体膜を形成する強誘電体膜形成工程と、 強誘電体膜と比較して低誘電率を有する低誘電体膜を形成する低誘電体膜形成 工程と、 A ferroelectric film forming step of forming a ferroelectric film; A low dielectric film forming process for forming a low dielectric film having a low dielectric constant compared to a ferroelectric film;
前記キャパシタを形成する部分を除き、前記トランジスタを形成する部分を含んで、 有機半導体膜を形成する有機半導体膜形成工程と、  An organic semiconductor film forming step of forming an organic semiconductor film including a portion for forming the transistor, excluding a portion for forming the capacitor;
前記強誘電体膜及び前記低誘電体膜を少なくとも挟んで前記トランジスタ用第 1電 極群と所定の位置関係でトランジスタ用第 2電極群を、及び前記強誘電体膜を少なく とも挟んで前記キャパシタ用第 1電極群に対応してキャパシタ用第 2電極群を形成す る第 2電極群形成工程と  The second electrode group for transistors in a predetermined positional relationship with the first electrode group for transistors across at least the ferroelectric film and the low dielectric film, and the capacitor across at least the ferroelectric film Forming a second electrode group for the capacitor corresponding to the first electrode group for forming a second electrode group;
を備える有機複合電子素子の製造方法。  A method for producing an organic composite electronic device comprising:
[7] 基板上にトランジスタ及びキャパシタを備える有機複合電子素子であって、 [7] An organic composite electronic device comprising a transistor and a capacitor on a substrate,
強誘電体膜と、  A ferroelectric film;
強誘電体膜と比較して低誘電率を有する低誘電体膜と、  A low dielectric film having a low dielectric constant compared to a ferroelectric film;
有機半導体膜と、  An organic semiconductor film;
前記強誘電体膜及び前記低誘電体膜を少なくとも挟んで所定の位置関係で配置 されたトランジスタ用ゲート電極及びトランジスタ用ソース'ドレイン電極と、  A transistor gate electrode and a transistor source and drain electrode disposed in a predetermined positional relationship with at least the ferroelectric film and the low dielectric film interposed therebetween;
前記強誘電体膜を少なくとも挟んで対向配置された一対のキャパシタ用電極と を備える有機複合電子素子。  An organic composite electronic device comprising: a pair of capacitor electrodes arranged to face each other with at least the ferroelectric film interposed therebetween.
[8] 請求項 7に記載の有機複合電子素子を備える有機半導体メモリ。 [8] An organic semiconductor memory comprising the organic composite electronic device according to claim 7.
[9] 基板上に第 1トランジスタ及び第 2トランジスタを備える有機複合電子素子の製造方 法であって、 [9] A method of manufacturing an organic composite electronic device comprising a first transistor and a second transistor on a substrate,
第 1トランジスタ用第 1電極群及び第 2トランジスタ用第 1電極群を形成する第 1電極 群形成工程と、  A first electrode group forming step for forming a first electrode group for the first transistor and a first electrode group for the second transistor;
強誘電体膜を形成する強誘電体膜形成工程と、  A ferroelectric film forming step of forming a ferroelectric film;
前記第 2トランジスタを形成する部分を除き、前記第 1トランジスタを形成する部分を 含んで、強誘電体膜と比較して低誘電率を有する低誘電体膜を形成する低誘電体 膜形成工程と、  A low dielectric film forming step of forming a low dielectric film having a low dielectric constant compared to a ferroelectric film, including a part forming the first transistor, excluding a part forming the second transistor; ,
有機半導体膜を形成する有機半導体膜形成工程と、  An organic semiconductor film forming step of forming the organic semiconductor film;
前記強誘電体膜及び前記低誘電体膜を少なくとも挟んで前記第 1トランジスタ用第 1電極群と所定の位置関係で第 1トランジスタ用第 2電極群を、及び前記強誘電体膜 を少なくとも挟んで前記第 2トランジスタ用第 1電極群と所定の位置関係で第 2トラン ジスタ用第 2電極群を形成する第 2電極群形成工程と The first transistor second film is interposed between at least the ferroelectric film and the low dielectric film. A second electrode group for the first transistor in a predetermined positional relationship with the first electrode group, and a second transistor group for the second transistor in a predetermined positional relationship with the first electrode group for the second transistor at least across the ferroelectric film. A second electrode group forming step for forming two electrode groups;
を備える有機複合電子素子の製造方法。  A method for producing an organic composite electronic device comprising:
[10] 基板上に第 1トランジスタ及び第 2トランジスタを備える有機複合電子素子であって [10] An organic composite electronic device comprising a first transistor and a second transistor on a substrate,
強誘電体膜と、 A ferroelectric film;
強誘電体膜と比較して低誘電率を有する低誘電体膜と、  A low dielectric film having a low dielectric constant compared to a ferroelectric film;
有機半導体膜と、  An organic semiconductor film;
前記強誘電体膜及び前記低誘電体膜を少なくとも挟んで所定の位置関係で配置 された第 1トランジスタ用ゲート電極及び第 1トランジスタ用ソース'ドレイン電極と、 前記強誘電体膜を少なくとも挟んで所定の位置関係で配置された第 2トランジスタ 用ゲート電極及び第 2トランジスタ用ソース'ドレイン電極と  A first transistor gate electrode and a first transistor source / drain electrode disposed in a predetermined positional relationship with at least the ferroelectric film and the low dielectric film interposed therebetween; and a predetermined with at least the ferroelectric film interposed therebetween The second transistor gate electrode and the second transistor source'drain electrode arranged in a positional relationship of
を備える有機複合電子素子。  An organic composite electronic device comprising:
[11] 請求項 10に記載の有機複合電子素子を備える有機強誘電体メモリ。 [11] An organic ferroelectric memory comprising the organic composite electronic device according to claim 10.
PCT/JP2007/072424 2006-11-27 2007-11-20 Organic thin film transistor, organic composite electronic element, method for manufacturing such transistor and element, and display device and memory WO2008065927A1 (en)

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