JPH09129846A - Dynamic memory element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prolong the period of a refreshing operation and reduce electric consumption power, by forming a bit line of a first wiring material and a second wiring material whose Fermi level is higher than the first wiring material. SOLUTION: When a first wiring material 41 is formed of semiconductor and a second wiring material 42 is formed of metal as conductor, a current flows from the second wiring material 42 to the first wiring material 41, and a phenomenon that heat is absorbed by the contact surface of the second wiring material 42 and the first wiring material 41 is generated. By forming a bit line of the first wiring material 41 and the second wiring material 42 whose Fermi level is higher than the first wiring material 41, heat is absorbed by the contact surface 43 of them, a transistor constituting a storage cell and minute capacitor 2 are cooled, leak or escape of charges from the minute capacitor 2 is reduced, and supply period of charges (period of refreshing operation) can be prolonged. Thus a dynamic memory element whose electric consumption power is small can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic memory device, and more particularly to reducing the power consumption of a refresh operation of a dynamic memory device.

[0002]

2. Description of the Related Art FIG. 2 is an equivalent circuit diagram of a memory cell of a dynamic memory device.

In a dynamic memory element, a plurality of storage cells for storing data are arranged in a grid pattern, and each storage cell is composed of one transistor 1 and a minute capacitance 12 for accumulating charges.

The control terminal of the transistor 1 of each memory cell is commonly connected to the word line 13, one operating terminal of the transistor 1 is the bit line 14, and the other operating terminal is one end of the minute capacitor 12. It is connected. The other end of the minute capacitance 12 is connected to the ground 15
(Ground potential).

In such a structure, when writing data, the voltage is applied to the selected word line 13 while the voltage is applied to the bit line 14. As a result, a voltage is applied to the control terminal of each transistor 1 connected to the selected word line 31 and the transistor 1
Is turned on and the minute capacitance 12 is charged with electric charge, so that writing is performed. At this time, the data is held by the electric charge stored in the minute capacitance 12. Moreover, when reading data, a voltage is applied to the word line 13 to be read,
This is performed by detecting the potential of each bit line 14 with the transistor 1 turned on. Here, the charge amount (potential) accumulated in the minute capacitance 12 is detected by a sense amplifier (not shown in FIG. 2) connected to the tip of the bit line 14.

[0006]

However, in the dynamic memory device as described above, in the case where the state in which the electric charge is accumulated in the minute capacitance is set to the logic "1", the charge is kept in order to maintain the logic "1". You have to keep it.
However, the charge of minute capacitance escapes through the word line or bit line, or directly to the periphery of minute capacitance,
Eventually it disappears and is inverted to logic "0". In order to hold the stored logic "1", a refresh operation is necessary to supplement the charge while the minute amount of charge can be distinguished from the charge amount of logic "0", that is, while the sense amplifier can determine the logic. is there. Most of the power consumed by the dynamic memory device is due to the supplement of charges by this refresh operation.

By the way, the time until the charge disappears is related to the temperature of the memory cell, and the higher the temperature, the shorter the disappearance time. Since the conventional dynamic memory device does not have any means for lowering the temperature, the refresh operation cycle is short and the power consumption is large.

The present invention has been made in order to solve the above-mentioned problems of the conventional technique, and an object of the present invention is to provide a dynamic memory device in which a refresh operation period is extended to reduce power consumption. And

[0009]

In order to achieve the above object, a dynamic memory device of the present invention includes a transistor having a control terminal and two operating terminals, and one operating terminal of the transistor, which is connected to an electric charge. A memory cell having a small capacity for storage, a word line connected to a control terminal of the transistor and applied with a control voltage for controlling on / off between two operation terminals of the transistor, and the operation of the other of the transistors. A bit line made of a first wiring material connected to a terminal, and a second wiring material that has a contact surface and is in contact with the first wiring material and has a higher Fermi level than the first wiring material. And having.

At this time, the first wiring material and the second wiring material
It is desirable that the contact surface with the wiring material is disposed at a position where heat is transmitted to the memory cell in the shortest time.

Further, the first wiring material may be formed of a semiconductor, and the second wiring material may be formed of a metal which is a conductor.

In the dynamic memory device configured as described above, when a current flows through the first wiring material and the second wiring material which form the bit line, the Peltier effect absorbs heat at the contact surface. Occurs. Therefore,
Since the transistors and minute capacitances forming the memory cell are cooled and leakage and escape of charges accumulated in the minute capacitances are reduced, the refresh operation cycle of the dynamic memory element can be extended.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a memory cell showing the structure of the dynamic memory device of the present invention. The equivalent circuit of the dynamic memory device of the present invention is the same as the circuit shown in the conventional example, and the structure thereof is different from the conventional one.

In FIG. 1, the transistor is composed of a first electrode 11 and a second electrode 12 which are operating terminals formed on a Si (silicon) substrate 9 and a word line 3 which is a control terminal. By applying an electric field (voltage) of a certain strength or more between the word line 3 and the first electrode 11 or between the word line 3 and the second electrode 12, the first electrode 11 and the second electrode 12 are applied. There is conduction between and. Also, the second electrode 1
As shown in FIG. 1, a surface area facing the ground line 5 is formed in the area 2, and this surface area serves as the minute capacitance 2. A first wiring material 41 is connected to the first electrode 11, and a second wiring material 42 is electrically connected to the first wiring material 41 by a contact surface 43. The first wiring material 41 and the second wiring material 42 form a bit line.

In such a structure, when a voltage is applied to the bit line 4 and a voltage is applied to the word line 3 to bring the operating terminals of the transistors into conduction, the second wiring material 42 and the first wiring are formed. A current flows through the material 41 and the transistor, and positive charge is supplied to the minute capacitance 2.

Here, if the first wiring material 41 is formed of a semiconductor and the second wiring material 42 is formed of a metal that is a conductor, a current flows from the second wiring material 42 to the first wiring material 41. The flow causes a phenomenon of absorbing heat at the contact surface 43 between the second wiring material 42 and the first wiring material 41.

This phenomenon occurs when, for example, when the first wiring material 41 is a p-type semiconductor, when holes flow from the metal into the semiconductor, the holes move in the semiconductor with the energy of the difference in Fermi level. This is a phenomenon that occurs because the kinetic energy necessary for is necessary and the heat that becomes the energy is absorbed from the outside.

Such a phenomenon is called the Peltier effect,
This occurs because the Fermi level of the second wiring material 42, which is the source of the current, is higher than the Fermi level of the first wiring material 41.

In this way, the contact surface 4 of the two wiring materials
The heat of the transistor and the minute capacitance 2 is taken from 3 to cool the transistor and the minute capacitance 2 which form the memory cell.

Therefore, by forming the bit line with the first wiring material 41 and the second wiring material 42 having a Fermi level higher than that of the first wiring material 41, heat is generated at the contact surface 43 between them. Are absorbed and the transistor and the minute capacitance 2 which form the memory cell are cooled, so that the leakage or escape of the charge from the minute capacitance 2 is reduced, and the charge replenishment cycle (refresh operation cycle) can be extended. Therefore, a dynamic memory element with low power consumption can be obtained.

The first wiring material 41 and the second wiring material 42 should preferably be selected from materials having a large Fermi level difference, and the cooling effect can be further enhanced by forming the bit lines in this way. it can. Further, in order to efficiently transfer the heat absorption phenomenon generated in the contact surface 43 between the first wiring material 41 and the second wiring material 42 to the region of the transistor 1 and the minute capacitance 2, the contact surface 43 of the two wiring materials is It is desirable that the heat transfer from the transistor 1 and the minute capacitance 2 is arranged at a position where the time is shortest. By forming the contact surface 43 of the two wiring materials at such a position, the cooling effect is further enhanced.

[0023]

Since the present invention is constructed as described above, it has the following effects.

A transistor having a control terminal and two operation terminals, a memory cell connected to one operation terminal of the transistor and having a minute capacitance for accumulating electric charges, and a control terminal of the transistor are connected to each other. A word line to which a control voltage for controlling ON / OFF between two operation terminals is applied, a first wiring material connected to the other operation terminal of the transistor, and a contact surface having a contact surface However, by having a bit line made of a second wiring material having a higher Fermi level than that of the first wiring material, leakage or escape of charges from a minute capacitance is reduced, and a cycle of refresh operation is extended. Therefore, a dynamic memory element with low power consumption can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a memory cell showing a structure of a dynamic memory device of the present invention.

FIG. 2 is an equivalent circuit diagram of a memory cell of a dynamic memory device.

[Explanation of symbols]

 2 Microcapacity 3 Word line 5 Ground line 9 Si substrate 11 First electrode 12 Second electrode 41 First wiring material 42 Second wiring material 43 Contact surface

Claims (3)

[Claims] 1. A transistor having a control terminal and two operation terminals, a memory cell connected to one operation terminal of the transistor and having a minute capacitance for accumulating charges, and a control terminal of the transistor. A word line that is connected and to which a control voltage for controlling on / off between the two operation terminals of the transistor is applied, a first wiring material connected to the other operation terminal of the transistor, and the first wiring material A bit line made of a second wiring material having a Fermi level higher than that of the first wiring material, the bit line being in contact with the first wiring material. 2. The dynamic memory element according to claim 1, wherein a contact surface between the first wiring material and the second wiring material is arranged at a position where heat is transferred to the memory cell for a shortest time. A dynamic memory device characterized in that 3. The dynamic memory element according to claim 1, wherein the first wiring material is formed of a semiconductor, and the second wiring material is formed of a metal that is a conductor. And a dynamic memory device.