JPH06150647A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To realize a signal generation circuit such as a refresh timer which sets a refresh time interval being optimum for used temperature with a semiconductor integrated circuit having less transistors. CONSTITUTION:A signal generation circuit in a semiconductor memory circuit comprises a transistor Q1, a memory cell section for monitoring connecting to a capacitor C1 in series, and inverters Q2, Q3 to which potential of the capacitor C1 of the memory cell section for monitoring is inputted, and generates an output signal in accordance with potential of the capacitor 1. The output signal is made a start signal for refresh operation of a dynamic memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a refresh timing signal generating circuit for holding stored information of a memory cell in a dynamic circuit, for example, a pseudo static RAM (PSRAM; Pseudo Sta
tic Random Access Memory)
It relates to a technology that is particularly effective when used for such purposes.

[0002]

2. Description of the Related Art In a semiconductor memory circuit, as a memory storage element, a dynamic RAM or the like is known, which basically stores information by accumulating charges in a capacitive element. Since the accumulated charge of the memory cell of such a semiconductor memory circuit decreases with time due to junction leakage or the like, data loss is prevented by selecting a memory cell and performing a refresh operation at every predetermined time. .

A dynamic RA capable of high integration
There is a pseudo static RAM as a semiconductor memory having M as a basic configuration and having compatibility with a normal static RAM. This pseudo static RAM has two refresh modes in addition to the write and call modes. As one refresh mode, there is an auto-refresh mode in which a refresh operation is sporadically executed by external control, and as another refresh mode,
There is a self-refresh mode in which a refresh operation is autonomously and periodically executed at the time of battery backup.
The cycle of the refresh operation in the self-refresh mode is set so as to compensate for the minimum value of the information securing time of the memory cell.

A refresh address counter for sequentially designating addresses to be refreshed in the self refresh mode is incorporated. Further, the semiconductor memory circuit that performs the self-refresh operation has a refresh control circuit for controlling the self-refresh operation, and the refresh control circuit forms a signal for determining a time interval of the refresh operation at a predetermined cycle. It has a refresh timer.

In this refresh timer, one electrode of a capacitive element is coupled to a circuit such as a ring oscillator composed of an odd number of stages of inverters, and the capacitive element is charged to an initial level and then discharged. The oscillation frequency is controlled in a circuit such as the ring oscillator according to the discharge operation time until the output of the next-stage inverter is inverted, thereby forming a periodic signal.

The self-refresh time interval is controlled by this periodic signal. Therefore, the self-refresh time interval is determined by the discharge time for the capacitive element and the threshold voltage of the inverter. That is, the self-refresh time interval depends on the CR time constant determined by the capacitance component such as the capacitance of the capacitance element and the resistance component of the discharge path.

By the way, generally, the information retention time of the memory cell depends on the temperature, and the refresh time interval at which the memory information stored in the memory cell does not disappear, that is, the pause refresh time becomes shorter as the temperature rises, and has an extremely large temperature dependence. . Therefore, pseudo static RAM
The refresh interval time is set so that the information of the memory cell can be held even at the maximum temperature of use.
This results in that the refresh interval time of the pseudo-static RAM is set to a short time interval corresponding to the maximum value of the operating temperature, and the refresh operation is performed at a shorter cycle than necessary at the room temperature which is normally used. This causes increase in power consumption associated with the refresh operation.

In particular, the pseudo static RAM pursues the ease of use of the static RAM while taking advantage of the high density and low power consumption of the dynamic RAM, and the stored information may be self-re-flushed by battery backup. Due to the general situation, it is becoming more and more necessary to reduce the power consumption during standby. Therefore, in order to avoid the problem of increasing the power consumption by setting the refresh interval time at a cycle shorter than necessary, the refresh interval time is determined according to the time when the conventional capacitive element is discharged from the initial level. There has been proposed a signal generating circuit that does. As this conventional technique, for example, JP-A-3-195058 and JP-A-2-78 are available.
Japanese Patent No. 266 is known.

As a technique for changing the refresh interval time of a semiconductor memory circuit according to temperature, conventionally, the temperature is detected by an external circuit component such as a thermistor,
It is known that the refresh operation cycle is defined by the detected temperature. Further, there is known one in which the cycle of the refresh operation is defined based on the discharge time of the charges accumulated in the capacitive element.

Next, the refresh timer circuit for defining the cycle of the conventional refresh operation based on the discharge time of the charges accumulated in the capacitive element will be described with reference to the configuration diagram of the conventional semiconductor memory circuit of FIG. In FIG. 8, Q
1, Q3, Q4 and Q6 are p-channel MOS transistors, Q2, Q5 and Q7 are n-channel MOS transistors, C is a capacitive element, DL is a delay circuit, IN is an inverter circuit, and Vcc is a power supply voltage.

The operation of the refresh timer circuit shown in FIG. 8 will be described below. First, when the output signal of the inverter circuit IN is in the high level state and the p-channel MOS transistor Q
When 3 is turned off, the electric charge accumulated in the capacitive element C is discharged through the n-channel MOS transistor Q5. n-channel MOS transistor Q5 and n-channel M
Since the OS transistor Q2 constitutes a current mirror circuit, the currents flowing through the n-channel MOS transistor Q5 and the n-channel MOS transistor Q2 are equal.

Next, the electric charge accumulated in the capacitance element C is discharged, the potential of the capacitance element C becomes a predetermined potential, and the n-channel MOS transistor Q7 is turned off. When the n-channel MOS transistor Q7 is turned off, a current is supplied to the node of the delay circuit DL through the p-channel MOS transistor Q6 and goes high. Here, assuming that the delay circuit DL operates to delay and transmit only the falling change of the node on the input terminal side, the delay circuit D
The output signal of L sets the output of the inverter circuit IN to low level, and further turns on the p-channel MOS transistor Q3. By the ON state of the p-channel MOS transistor Q3, the capacitive element C is charged via the p-channel MOS transistors Q3 and Q4.

Next, when charge is accumulated in the capacitive element C, n
The channel MOS transistor Q7 is turned on, the node on the input terminal side of the delay circuit DL becomes low level,
This change of the low level is delayed for a predetermined time to turn off the p-channel MOS transistor Q3 via the inverter circuit IN, and the electric charge accumulated in the capacitive element C is started to be re-discharged.

Therefore, the timing signal φtm generated by the conventional refresh timer circuit shown in FIG.
The timer period is defined by the discharge time of the charge accumulated in the capacitive element C, and the timer period is defined only by the function of the capacitance value of the capacitive element C and the resistance value of the resistive element R.

[0015]

However, the conventional refresh timer circuit has the following problems. (1) In the conventional technology of detecting the temperature by an external circuit component such as the thermistor and defining the cycle of the refresh operation based on the detected temperature, the detection circuit such as the thermistor mounted on the board is located near the board or in the casing. Since the ambient temperature inside the body is detected, there is a difference from the temperature of the memory chip that directly receives heat generated by the power consumption of the circuit, the error in the cycle of the refresh operation becomes large, and only control with a large margin can be performed. Can not.

Therefore, the purpose of reducing the power consumption cannot be fully achieved. (2) For an external circuit component such as a thermistor, it takes time and effort to mount the circuit component, and it is necessary to provide a terminal for receiving the refresh control signal on the memory device. (3) In the conventional refresh timer circuit which is defined based on the discharge time of the charge accumulated in the capacitive element, the number of transistors to be used is about 10 to 16, which is a large number. Contrary to the convenience of the pseudo static RAM, which pursues the ease of use of the static RAM while taking advantage of the high density of the above, it is not possible to fully utilize its characteristics.

An object of the present invention is to eliminate the above-mentioned problems and to realize a signal generation circuit for setting an optimum refresh interval time for a use temperature by a semiconductor integrated circuit having a small number of transistors.

[0018]

SUMMARY OF THE INVENTION In order to overcome the above-mentioned problems, the present invention provides a signal generation circuit in a semiconductor memory circuit, in which a dynamic memory in which one transistor and one capacitor are connected in series, and a dynamic memory The dynamic memory is used as a dummy memory cell for monitoring, and an output signal is generated from the inverter section according to the potential of the capacitor. Then, the output signal can be used as a start signal of the refresh operation of the dynamic memory cell.

[0019]

According to the present invention, a dynamic memory formed by connecting one transistor and one capacitor in series is used as a dummy memory cell for monitoring, and the potential of the storage node of the capacitor of the dummy memory cell is monitored to perform the storage operation. When the potential of the node is equal to or lower than the set voltage value, the refresh operation start signal is generated through the inverter having a small number of transistors. As a result, the temperature characteristic of the dynamic memory can be monitored by the temperature characteristic of the capacitor in the dummy memory cell, and the refresh operation can be finely set according to the information retention performance corresponding to the temperature of the memory cell.

Moreover, since an inverter having a small number of transistors is used, the entire circuit area is reduced,
It does not impair the high density of the pseudo static RAM.

[0021]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration diagram of a refresh timer circuit of a semiconductor memory circuit of the present invention. In the figure, Q1 is an nMOS transistor, Q2 is an nMOS transistor, Q3 is a pMOS transistor, C1 is a capacitor, WO is a word line signal generation circuit, AD is an address generation circuit, Vsn is a storage node voltage of the capacitor C1, and Vcc is a power supply voltage. , Vp1 is the cell plate voltage, Vref
Is a reference voltage, φw is a word line signal, φm is a timing signal, and φreset is a reset signal.

The illustrated refresh timer circuit is composed of a dummy memory cell section and an inverter section, and the dummy memory cell section has a word line signal generation circuit W.
The word line signal φw is input from O, and the timing signal φm is output from the inverter section to the address generation circuit AD. The dummy memory cell portion has a one-transistor / one-capacitor configuration in which an nMOS transistor Q1 and a capacitor C1 are connected in series. The source of the nMOS transistor Q1 is connected to the power supply voltage Vcc, and nMO
The drain of the S transistor Q1 is connected to one electrode of the capacitor C1. The other electrode of the capacitor C1 is connected to the cell plate voltage Vp1.

Further, the gate of the nMOS transistor Q1 is connected to the word line signal generation circuit WO, and the word line signal φw is inputted. The nMOS transistor Q1
The threshold voltage of Vth1 is Vth1. On the other hand, the inverter section is formed by connecting a pMOS transistor Q3 and an nMOS transistor Q2 in series,
Is connected to the power supply voltage Vcc, and the drain of the pMOS transistor Q3 is connected to the drain of the nMOS transistor Q2. Then, the pMOS transistor Q3
Is grounded to GND.

The source of the nMOS transistor Q2 is connected to the reference voltage Vref, and the nMOS transistor Q2
The gate of 2 is connected to the contact between the drain of the nMOS transistor Q1 of the dummy memory cell section and one electrode of the capacitor C1, and the voltage Vsn at the connection point is input. This voltage Vsn is the storage node voltage of capacitor C1.

The connection point between the drain of the pMOS transistor Q3 and the drain of the nMOS transistor Q2 in the inverter section is connected to the address generating circuit AD,
The timing signal φm is output to the address generation circuit AD. The threshold voltage of the nMOS transistor Q2 is Vth2. The address generation circuit AD has an input terminal for receiving the timing signal φm from the inverter section, and an output terminal for outputting the address signals A0-An.
It has a RESET terminal that outputs a reset signal φreset.

The address signals A0 to An sequentially output addresses from A0 to An using the input of the timing signal φm as a trigger to select a memory cell of the semiconductor memory circuit and perform a refresh operation. In addition, the RESET terminal and the clear terminal CLR of the word line signal generation circuit WO
Connected to the reset signal φre from the RESET terminal
set is input to the clear terminal CLR.

Next, referring to the time chart of the refresh timer circuit of the semiconductor memory circuit of the present invention shown in FIG. 2 and the operation diagram of the refresh timer circuit of the semiconductor memory circuit of the present invention shown in FIGS. The operation of the refresh timer circuit of the semiconductor memory circuit of the invention will be described. In the time chart of FIG. 2, the storage node voltage Vsn of the capacitor C1, the timing signal .phi.m, the address signals A0 to An, and the reset signal .phi.re are arranged in order from the top.
set and word line signal φw are shown.

Hereinafter, the reference numerals given to the time chart of FIG. 2 correspond to the reference numerals given in FIGS. First, when the word line signal φw is in the low level state in FIG. 3, the nMOS transistor Q1 is in the off state, and the storage node voltage Vsn due to the charges accumulated in the capacitor C1 is shown in (1) of FIG. As it starts to decrease due to leakage current. While the storage node voltage Vsn is higher than Vref + Vth2 which is the sum of the reference voltage Vref and the threshold voltage Vth2 of the nMOS transistor Q2, the nMOS transistor Q2 is in the ON state.

Here, the pMOS forming the inverter section
Since the base of the transistor Q3 is connected to GND, the pMOS transistor Q3 is always on. Therefore, the timing signal φm, which is the voltage at the connection point between the drain of the pMOS transistor Q3 and the drain of the nMOS transistor Q2, is
If the on-resistances of the drain of No. 3 and the nMOS transistor Q2 are equal, (Vcc + Vref) / 2, which is low level. This voltage state is indicated by (2) in FIGS.

Next, the storage node voltage Vsn is shown in FIG.
It decreases from (1) to (3) of (Vref
+ Vth2) voltage value or less, nMO in FIG.
The S transistor Q2 is turned off. As described above, the pMOS transistor Q3 is always in the ON state,
When the nMOS transistor Q2 is turned off, the timing signal φm becomes (Vcc + Vref) / 2 as shown in (4).
Rises from the low level of Vcc to the high level of Vcc.

The address generation circuit AD starts sending address signals in order from A0 at the rise of the timing signal φm. A memory cell is designated by the transmission of this address signal and a refresh operation is performed. Due to the rise of the timing signal φm, the word line signal φw is changed from the low level to (Vcc + Vth1) after the delay time in the address generation circuit AD and the word line signal generation circuit WO elapses.
Rise to the high level of. This state is shown by (6) in FIGS.

Next, referring to FIG. 5, the nMOS transistor Q is driven by the rise of the word line signal φw in (6).
1 changes from the off state to the on state. When the nMOS transistor Q1 is turned on, the power supply voltage is applied to the capacitor C1 and the accumulation of charges in the capacitor C1 is started. Therefore, the storage node voltage Vsn of the capacitor C1 starts to rise from the time of (7), and the time constant of the rise of the voltage is a value determined by the capacitance of the capacitor C1 and the on-resistance of the nMOS transistor Q1.

When the voltage Vsn of the storage node of the capacitor C1 rises and exceeds the voltage of (Vcc + Vref),
As shown in (8), the nMOS transistor Q2 is turned on. When the nMOS transistor Q2 is turned on, the timing signal φm is transmitted to the drain of the pMOS transistor Q3 and the nMOS transistor Q2.
If the ON resistances of the two are equal, (Vcc + Vref) / 2, and fall to the low level. This state is shown by (9) in FIGS.

After that, the capacitor C1 continues to accumulate electric charges, and the storage node voltage V
sn rises, the capacitance of the capacitor C1 and nMO
The power supply voltage Vcc is reached after a time constant determined by the ON resistance of the S transistor Q1. Further, during that time, the address generating circuit AD continues to output the address signals A0 to An in order.

In FIG. 6, when the address signal generation circuit AD finishes transmitting the address signal, the address signal generation circuit AD resets the reset signal φreset from the reset terminal RESET to the clear terminal CLR of the word line signal generation circuit WO as shown in (11). Is sent. Word line signal generation circuit W
The O word line signal .phi.w falls from the high level of (Vcc + Vth1) to the low level by the reset signal .phi.reset as shown in (12).

By the fall of the word line signal φw to the low level, the nMOS transistor Q1 is turned off, the charge accumulated in the capacitor C1 starts to be discharged by the leak current, and the storage capacitor is again stored as shown in (13).
The decrease of the node voltage Vsn starts. The refresh operation is repeated by repeating this cycle.

Therefore, the start time of the refresh operation is determined by reflecting the temperature characteristic of the capacitor C1, so that the refresh operation can be set according to the information holding performance of the memory cell. Next, a structural example of the refresh timer circuit will be described with reference to the cross-sectional configuration diagram of the refresh timer circuit of the semiconductor memory circuit of the present invention in FIG.

In FIG. 7, 1 is a substrate of n ⁻ type conductivity type, 3 is a well region of p type conductivity type, 4a to 4d are element isolation regions, 6b and 13 are insulating films, 7 is a pMOS transistor, and 7a. , 7b, 8a, 8b, 9a, 9b, 10a are diffusion regions, 7c, 8c, 9c are gate electrodes, and 8 and 9 are n.
MOS transistor, 10 is a capacitor, 10b is a capacitor electrode, 12a to 12d, 14a and 14b are wirings,
Reference numeral 15 is a passivation film.

A p-type well region 3 is formed in a part of the substrate 1 from the surface to a predetermined depth, and element isolation regions 4a to 4d are formed on the surface of the substrate 1 at predetermined intervals. ing. Then, in the figure, the element isolation region 4
The inverter part and the dummy memory cell part are formed with the boundary c. The inverter part is composed of the element isolation regions 4a and 4
b, and an nMOS transistor 8 formed between the element isolation regions 4b and 4c, while the memory cell portion is an nMOS formed between the element isolation regions 4c and 4d. It is composed of a transistor 9 and a capacitor 10.

The structure of the pMOS transistor 7 and the nMOS transistor 8 in the inverter section is as follows. The pMOS transistor 7 forms diffusion regions 7a and 7b having a conductivity type of p ⁺ below the surface of the substrate 1 with a predetermined distance from each other and at a predetermined depth, and on the surface of the substrate 1 and the diffusion regions 7a and 7b. The gate electrode 7c is formed on the surface of the insulating film 6b so as to extend between the diffusion regions 7a and 7b.

The nMOS transistor 8 is connected to the substrate 1
Under the surface of the p-type well region 3, the diffusion regions 8a and 8b of n ⁺ conductivity type are formed with a predetermined depth from each other, and the surface of the substrate 1 and the diffusion regions 8a and 8b are formed.
The gate electrode 8c is formed on the surface of b so as to extend between the diffusion regions 8a and 8b with the insulating film 6b interposed therebetween.

On the other hand, the nMO of the dummy memory cell section is
The configurations of the S transistor 9 and the capacitor 10 are as follows. The nMOS transistor 9 has an element isolation region 4C.
And 4d, diffusion regions 9a and 9b having a conductivity type of n ⁺ are formed below the surface of the well region 3 with a predetermined depth from each other, and the surface of the well region 3 and the diffusion region 9a are formed. A gate electrode 9c is provided on the surface of 9b so as to extend between both diffusion regions 9a and 9b with an insulating film 6b interposed therebetween.

Further, the capacitor 10 is also adjacent to the nMOS transistor 9 between the element isolation regions 4C and 4d and under the surface of the well region 3 a diffusion region 1 of n ⁺ conductivity type.
0a is formed, and a capacitor electrode 10b is formed on the diffusion region 10a with an insulating film therebetween. The capacitor electrode 10b is formed by patterning the first polysilicon layer formed on the substrate 1, and the gate electrodes 7c, 8c and 9c of the pMOS transistor 7 and nMOS transistors 8 and 9 are formed on the substrate. The second polysilicon layer formed on the first layer is patterned.

In addition to polysilicon, a refractory metal such as tungsten or molybdenum can be used as the electrode material. The refresh timer circuit of the semiconductor memory circuit of the present invention comprises the dummy memory cell section and the inverter section as described above, and this configuration is provided at an arbitrary position of the memory cell section of the semiconductor memory circuit. You can

When the temperature condition differs depending on the positions of a plurality of memory cell portions in the semiconductor memory circuit, for example, the refresh timer circuit of the present invention is provided at a plurality of different positions in the semiconductor memory circuit, and the refresh interval therein. The refresh operation can be controlled by dividing it into short groups or several groups. Next, second to fourth embodiments of the refresh timer circuit of the semiconductor memory circuit of the present invention will be described.

FIG. 9 is a block diagram of the second embodiment of the refresh timer circuit of the semiconductor memory circuit of the present invention. In the second embodiment, the pMOS transistor Q3 of the inverter section in the first embodiment of the present invention is replaced by the resistance element R.
It is composed of. As shown in the first embodiment, the pMOS transistor Q3 in the inverter section is always in the ON state, so that the pMOS transistor Q3 can be replaced with the resistance element R.

The resistance element R can be formed of a polysilicon layer on the semiconductor substrate similarly to the refresh timer circuit of the first embodiment. In addition, FIG.
It is a block diagram of the 3rd Example of the refresh timer circuit of the semiconductor memory circuit of this invention. In the third embodiment, nM of the inverter section in the first embodiment of the present invention is used.
The voltage Vsn of the storage node of the capacitor C1 is applied to the gate of the OS transistor Q2 and the gate of the pMOS transistor Q3.

When the voltage Vsn of the storage node of the capacitor C1 is higher than the sum of the threshold voltage Vth2 of the nMOS transistor Q2 and the reference voltage Vref and higher than the threshold voltage Vth3 of the pMOS transistor Q3, which is higher than Vcc-Vth3. , The nMOS transistor Q2 is on, while the pMOS transistor Q3 is off, and the timing signal φm is the low level reference voltage Vref.
Becomes

The voltage Vsn of the storage node of the capacitor C1 is equal to the threshold value V of the nMOS transistor Q2.
It is lower than the sum of th2 and the reference voltage Vref, and Vcc-
When it is lower than Vth3, the nMOS transistor Q2 is in the off state, while the pMOS transistor Q3 is in the on state, and the timing signal φm becomes the high level power supply voltage Vcc.

The operations of the second to third embodiments of the refresh timer circuit of the semiconductor memory circuit of the present invention are the same as those of the first embodiment.
It is similar to the embodiment of. Next, another embodiment of the structure of the refresh timer circuit of the semiconductor memory circuit of the present invention will be described. FIG. 11 is a cross-sectional configuration diagram of another embodiment of the refresh timer circuit of the semiconductor memory circuit of the present invention.

In FIG. 11, 6 is an insulating film, and other reference numerals are the same as in FIG. A p-type well region 3 is formed in a part of the substrate 1 from the surface to a predetermined depth, and element isolation regions 4a to 4d are formed on the surface of the substrate 1 at predetermined intervals. Then, in the figure, the inverter portion and the dummy memory cell portion are formed with the element isolation region 4c as a boundary.

The element isolation region 4a is formed in the conductivity type n ⁻ type region of the substrate 1, and the element isolation regions 4b and 4d extend over the conductivity type n ⁻ type region of the substrate 1 and the p type region of the well region 3. The element isolation region 4c is formed in the p-type region of the well region 3. The inverter portion is composed of a pMOS transistor 7 formed between the element isolation regions 4a and 4b and an nMOS transistor 8 formed between the element isolation regions 4b and 4c, while the memory cell portion is formed of the element isolation region 4c. And 4d, an nMOS transistor 9 and a capacitor 10 are formed.

The structures of the pMOS transistor 7 and the nMOS transistor 8 in the inverter section are as follows. The pMOS transistor 7 forms diffusion regions 7a and 7b having a conductivity type of p ⁺ below the surface of the substrate 1 with a predetermined distance from each other and at a predetermined depth, and on the surface of the substrate 1 and the diffusion regions 7a and 7b. The gate electrode 7c is formed on the surface of the insulating film 6 so as to extend between the diffusion regions 7a and 7b.

The nMOS transistor 8 is formed on the substrate 1
Diffusion regions 8a and 8b of n ⁺ conductivity type are formed below the surface of the well region at a predetermined depth from each other, and are formed on the surface of the substrate 1 and the diffusion regions 8a and 8b. A gate electrode 8c is provided so as to extend between both diffusion regions 8a and 8b via an insulating film 6.

On the other hand, the structures of the nMOS transistor 9 and the capacitor 10 in the memory cell section are as follows.
The nMOS transistor 9 includes element isolation regions 4C and 4d.
The conductivity type is n ⁺ below the surface of the well region 3 between
Diffusion regions 9a and 9b are formed at a predetermined depth with a predetermined distance from each other and formed on the surface of the well region 3 and the diffusion regions 9a and 9b so as to extend between the diffusion regions 9a and 9b. It is configured by providing the gate electrode 9c via the insulating film 6.

Further, the capacitor 10 is likewise adjacent to the nMOS transistor 9 between the element isolation regions 4c and 4d, below the surface of the well region 3 and in the diffusion region 10 of n ⁺ conductivity type.
a is formed, and the capacitor electrode 10b is formed on the diffusion region 10a with the insulating film 6 interposed therebetween. The capacitor electrode 10b is formed by patterning the first polysilicon layer formed on the substrate 1, and the gate electrodes 7c, 8c and 9c of the pMOS transistor 7 and nMOS transistors 8 and 9 are also formed on the substrate. 1 is formed by patterning the first polysilicon layer formed on the first layer.

In addition to polysilicon, a refractory metal such as tungsten or molybdenum can be used as the electrode material. Gate electrodes 7c and 8 of pMOS transistor 7 and nMOS transistor 8 in the inverter section
c, the gate electrode 9c of the nMOS transistor 9 in the memory cell portion and the capacitor electrode 10b of the capacitor 10,
An insulating film 11 is formed and coated on the element isolation regions 4a to 4d and the entire surface of the insulating film 6.

Wirings 12a to 12 are formed on the insulating film 11.
d is formed by patterning the first aluminum layer. The wiring 12a is in contact with the diffusion region 7a of the pMOS transistor 7 through the contact holes formed in the insulating films 11 and 6, and the wiring 12b is also the insulating film 1 in the same manner.
The diffusion regions 7b of the pMOS transistor 7 and the nMOS transistor 8 through the contact holes drilled in
Is in contact with the diffusion area 8a.

The wirings 12c and 12d are connected to the nMOS transistor 8 through the contact holes formed in the insulating films 11 and 6.
Diffusion region 8b of the nMOS transistor 9
a are in contact with each other. And wiring 12a-12
An insulating film 13 is formed on the entire surface of the insulating film 11 and the insulating film 11, and wirings 14a and 14b are formed on the insulating film 13 by patterning a second aluminum layer.

The wirings 14a and 14b contact the wirings 12c and 12d through the contact holes formed in the insulating film 13, and the passivation film 15 is formed so as to cover the wirings 14a and 14b and the insulating film 13 entirely. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0061]

As described above, according to the present invention,
A refresh timer circuit of a semiconductor integrated circuit that performs a refresh operation at a timing suitable for the external operating temperature,
It can be realized by a small number of components such as a dynamic memory for a monitor and an inverter section, which are composed of a transistor and one capacitor, and the number of components can be significantly reduced as compared with the conventional refresh timer circuit that determines the refresh interval time. it can.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a refresh timer circuit of a semiconductor memory circuit of the present invention.

FIG. 2 is a time chart of the refresh timer circuit of the semiconductor memory circuit of the present invention.

FIG. 3 is an operation diagram of the refresh timer circuit of the semiconductor memory circuit of the present invention.

FIG. 4 is an operation diagram of the refresh timer circuit of the semiconductor memory circuit of the present invention.

FIG. 5 is an operation diagram of the refresh timer circuit of the semiconductor memory circuit of the present invention.

FIG. 6 is an operation diagram of the refresh timer circuit of the semiconductor memory circuit of the present invention.

FIG. 7 is a cross-sectional configuration diagram of a refresh timer circuit of a semiconductor memory circuit of the present invention.

FIG. 8 is a configuration diagram of a conventional semiconductor memory circuit.

FIG. 9 is a configuration diagram of a second embodiment of a refresh timer circuit of a semiconductor memory circuit of the present invention.

FIG. 10 is a configuration diagram of a third embodiment of a refresh timer circuit of a semiconductor memory circuit of the present invention.

FIG. 11 is a cross-sectional view showing another embodiment of the refresh timer circuit of the semiconductor memory circuit of the present invention.

[Explanation of symbols]

 Q1, Q2 nMOS transistor Q3 pMOS transistor C1 capacitor WO word line signal generation circuit AD address generation circuit Vsn storage node voltage Vcc power supply voltage Vp1 cell plate voltage Vref reference voltage φw word line signal φm timing signal φreset reset signal

Claims (2)

[Claims] 1. A signal generation circuit in a semiconductor memory circuit, wherein (a) a monitor dynamic memory in which a transistor and a capacitor are connected in series and (b) a potential of a capacitor of the monitor dynamic memory are input. A semiconductor memory circuit comprising an inverter and configured to generate an output signal according to (c) the potential of the capacitor. 2. The semiconductor memory circuit according to claim 1, wherein the output signal is a start signal of a refresh operation of a dynamic memory cell.