JPH02229468A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To relieve a local stress given by a filler contained in a sealing resin when a pair of MOS transistors constituting a differential circuit of a sense amplifier is sealed with resin and to prevent unbalance of electric characteristics between the transistors caused by such stress by covering the transistor pair with a layer having a lower elastic coefficient than a surface protecting film. CONSTITUTION:An interconnection layer 5 formed of a material having a low elastic coefficient such as aluminum is laid out to cover a sense amplifier transistor region 3. If a stress is given to the surface of a chip on the sense amplifier by a filler contained in a sealing resin, the stress is relieved by the interconnection layer 5 having a low elastic coefficient. In this manner, it is possible to minimize variation in electric characteristics of the transistors caused by such stress and to decrease unbalance of electric characteristics between the transistor pair of the sense amplifier. Thus, it is possible to provide a sense amplifier having high sensitivity without altering the assembling processes of a semiconductor storage device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device sealed with resin.

2. Description of the Related Art In recent years, semiconductor memory devices have made remarkable progress, and large storage capacities have been achieved.

Dynamic random access memory (DRAM)
It is written as ), storage capacity has quadrupled in about three years, and higher integration is progressing. In order to achieve high integration, the memory cell area has been reduced and the memory cell capacity C
s tends to decrease. On the other hand, the chip area of semiconductor memory devices is increasing due to the increase in storage capacity, and the bit line capacitance CB tends to increase. As a result, the capacitance ratio O B /C 5 between the bit line and the memory sensor increases, and the potential difference in the bit line bare during data reading becomes smaller. If the sensitivity of the sense amplifier is defined as the minimum potential difference between a pair of focused lines that can be amplified by the differential circuit of the sense amplifier, a sense amplifier with higher sensitivity is essential in order to amplify the minute potential difference between the bare bit lines.

In order to realize a highly sensitive sense amplifier, it is important to reduce the imbalance in the electrical characteristics of the transistor pair forming the differential circuit of the sense amplifier. An imbalance in the electrical characteristics of the transistor pair of the sense amplifier causes a decrease in the sensitivity of the sense amplifier, leading to malfunction of the sense operation.

One factor that causes an imbalance in the electrical characteristics of a pair of transistors in a sense amplifier is mechanical stress applied to the transistors. One of the causes of the above-mentioned mechanical stress' (hereinafter referred to as stress) is due to filler mixed into the sealing resin of the semiconductor memory device. Generally, inorganic powder such as silica or anolemina is mixed into the sealing resin as a filler to bring the expansion coefficient of the resin closer to that of Si. Usually, the particle size of the filler mixed into the resin is from several μm to several tens of μm.
It has sharp edges in shape.

FIG. 4 schematically shows the mechanism by which the filler contained in the sealing resin applies stress to the semiconductor memory device. In FIG. 4, 16 is a chip of a semiconductor memory device;
6 is a filler contained in the sealing resin, 17 is a sealing resin, 1
8 indicates Guipad.

In the resin sealing process of a semiconductor memory device, the edge of the filler may come into contact with the chip surface of the semiconductor memory device. The filler is subjected to stress in the direction of the chip surface of the semiconductor memory device due to shrinkage of the sealing resin when it hardens.

The stress that the filler receives from the resin concentrates on the edge portion of the filler that is in contact with the chip surface, and a large stress is locally applied to the chip surface of the semiconductor memory device.

When stress is applied to a MOS transistor, the threshold voltage and voltage-current characteristics of the MOS transistor vary. The stress applied to the chip surface of a semiconductor memory device by the filler contained in the sealing resin is locally concentrated near the edge of the filler. The stress applied to the transistor pairs forming the circuit is not uniform, and differences occur between the transistor pairs in the amount of fluctuation in threshold voltage and voltage-current characteristics, resulting in an imbalance in the electrical characteristics of the transistor pairs, and the sense amplifier Sensitivity decreases.

A conventional technique for alleviating stress exerted on a semiconductor memory device by a filler will be described below.

FIG. 6 is a schematic cross-sectional view of a conventional semiconductor memory device, in which 16 is a chip of the semiconductor memory device, 18 is a die pad, 17 is a sealing resin, 16 is a filler contained in the sealing resin, and 19 is a semiconductor This shows a buffer coat applied to the surface of a memory device chip.

By applying a puffer coat to the chip surface of a semiconductor memory device, it is possible to prevent the filler in the sealing resin from coming into direct contact with the chip surface. Since the resin used in the passo coat has a lower elastic modulus than that of a typical chip surface protective film, the stress applied to the chip surface of the semiconductor memory device is alleviated by the edges of the filler.

Furthermore, methods have also been taken to reduce the particle size of the filler contained in the sealing resin.

By setting the particle size of the filler to several μm or less, the stress that the filler applies to the chip surface of the semiconductor memory device can be made sufficiently small.

Problems to be Solved by the Invention However, the above-mentioned conventional techniques require an increase in the number of assembly steps or a change in the sealing resin.

We also offer zigzag in-line plastic packaging (Z
In thin packages such as IP packages, it is not possible to increase the thickness of the vanofer coat in order to maintain package reliability, and the filler sticks to the buffer coat and the edges of the filler reach the chip surface, resulting in insufficient effectiveness. There were cases where it was not possible.

The present invention solves the above-mentioned conventional problems, and reduces the unbalance of the sense amplifier caused by the stress caused by the filler in the sealing resin, without increasing the number of steps in the assembly process or changing the sealing resin. An object of the present invention is to provide a semiconductor memory device that realizes a sense amplifier.

Means for Solving the Problem In order to achieve this object, the semiconductor memory device of the present invention includes a layer having a lower elastic modulus than a surface protective film on the upper part of the MOS transistor pair forming the differential circuit of the sense amplifier. It has a structure covered with.

Effect: With this structure, the filler in the sealing resin relieves the stress applied to the sense amplifier section of the semiconductor memory device.
By suppressing the imbalance in the electrical characteristics of the transistor pair of the sense amplifier caused by the stress, the sensitivity of the sense amplifier can be maintained at a high level.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows the layout of a sense amplifier section in one embodiment of the present invention.

In FIG. 1, 1 is a pit line, 2 is a transistor gate of a sense amplifier, 3 is a transistor region of a sense amplifier, 4 is a first wiring layer, and 6 is a sense amplifier drive signal line formed by a second wiring layer. , 6 is a contact portion between the first wiring layer and a conductive layer formed under the wiring layer, and 7 is a contact portion between the first wiring layer and the second wiring layer.

The layout of the sense amplifier section of the semiconductor memory device of this embodiment configured as described above will be described below.

In this embodiment, the second wiring layer shown by 6 in FIG. 1 is formed of a material with a low elastic coefficient, such as aluminum, and is laid out so as to cover the transistor region of the sense amplifier. When stress is applied from the chip surface on the sense amplifier shown in Figure 1 due to the filler contained in the sealing resin,
The stress is alleviated by the second wiring layer with a low elastic coefficient laid out on the sense amplifier, suppressing fluctuations in the electrical characteristics of the transistor caused by the stress, and reducing imbalance in the electrical characteristics of the pair of transistors in the sense amplifier.

As described above, according to this embodiment, by covering the transistor region of the sense amplifier with a wiring layer having a low elastic coefficient such as aluminum, a highly sensitive sense amplifier can be realized without changing the assembly process of the semiconductor memory device. A semiconductor memory device can be provided.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the layout of a sense amplifier section of a semiconductor memory device in another embodiment of the present invention.

In FIG. 2, 1 is a bit line, 2 is a sense amplifier transistor gate, 3 is a transistor region, and 4 is a first
6 is a sense amplifier drive signal line formed in the second wiring layer, 6 is a contact portion between the first wiring layer and a conductive layer formed below the wiring layer, and 7 is a contact portion of the first wiring layer. A contact portion between the wiring layer and the second wiring layer is shown.

The layout of the sense amplifier section of the semiconductor memory device configured as described above will be explained below.

In this embodiment, the first wiring layer shown at 4 in FIG. 2 is formed of a material with a low elastic modulus, such as aluminum. Layout is performed so that the first wiring layer covers the gate of the sense amplifier transistor. When stress is applied from the chip surface on the sense amplifier shown in Figure 2 due to the filler contained in the sealing resin, the stress is alleviated by the first wiring layer with a low elastic modulus laid out on the sense amplifier. This suppresses fluctuations in the electrical characteristics of the transistors caused by this, and reduces the imbalance in the electrical characteristics of the transistor pair of the sense amplifier.

Figure 3 shows the cross-sectional structure at section ▲1B in Figure 2.

In FIG. 3, 4 is the gate of the sense amplifier transistor, 6 is the first wiring layer, 8 is the gate insulating film of the sense amplifier transistor, 9 is the drain diffusion region, 1o is the source diffusion region, and 11 is the gate indicated by 4. a conductive layer to be formed;
5 is an insulating layer between the first wiring layer, 12 is an insulating layer between the first wiring layer 6 and a wiring layer above the wiring layer, and 13 is a surface of the chip of the semiconductor memory device. protective film, 14
indicates a semiconductor substrate.

As shown in FIGS. 2 and 3, the first wiring layer does not cover the entire surface of the gate of the sense amplifier transistor. However, as shown in Figure 3, the interlayer insulating layer and surface protective film have a steep slope above both ends of the gate of the transistor, so the filler in the sealing resin causes local stress on the gate. will not be added.

As is clear from this embodiment, the layer having a low elastic coefficient that covers the transistor of the sense amplifier does not necessarily need to cover the entire gate of the transistor of the sense amplifier.

In addition, in the embodiment of the present invention, the MOS of the sense amplifier
}The explanation was given using an aluminum wiring layer as a layer covering the upper part of the transistor, but this is because aluminum has a low elastic modulus among the materials currently commonly used for the wiring layer or insulating layer of semiconductor integrated devices. This is because the effect of stress relaxation, which is the object of the present invention, is large.

Therefore, by using aluminum, it is possible to fully achieve the object of the present invention without changing the diffusion process.

Effects of the Invention The present invention covers the upper part of the MOS transistor forming the differential circuit of the sense amplifier of the semiconductor memory device with a layer having a low elastic coefficient, thereby reducing the amount of material contained in the sealing resin when sealing the semiconductor memory device with the resin. A highly sensitive sense amplifier is realized by alleviating the local stress generated by the filler and suppressing the imbalance in the electrical characteristics of the transistor pair of the sense amplifier caused by the stress.

Furthermore, by implementing stress-relieving means in the chip body of the semiconductor memory device, the semiconductor memory device can be assembled without changing the sealing resin or buffer coating, improving the workability of the assembly process. This makes it possible to realize a semiconductor memory device that has many excellent features, such as being able to reduce assembly costs.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a layout diagram of a sense amplifier section of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a layout diagram of a sense amplifier section of a semiconductor memory device according to another embodiment of the present invention. 3 are cross-sectional views of the transistor portion of the sense amplifier of the semiconductor memory device according to the embodiment of the present invention shown in FIG.
Fig. 4 schematically shows the mechanism by which the filler contained in the sealing resin of a semiconductor memory device applies stress to the chip surface of the semiconductor memory device, and Fig. 6 schematically shows a conventional semiconductor memory device. FIG. DESCRIPTION OF SYMBOLS 1... Bit line, 2... Gate of sense amplifier transistor, 3... Transistor region, 4... First wiring layer, 6... . . . second wiring layer, 6 . . . contact portion between the first wiring layer and the conductive layer formed under the wiring layer, 7 . . . the first wiring layer and Contact portion of second wiring layer, 8...
...Gate insulating film, 9...Drain diffusion region,
10... Source diffusion region, 11... Insulating layer, 12... Insulating layer, 13... Surface protective film, 14... Semiconductor゜Body board, 16...
- Semiconductor storage device chip, 16... filler, 17... sealing resin, 18... die pad, 19... buffer coat. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 1 t゛-゜Hit line 2゜-Sense 7 pump transistor gate 3-｝Ranjizuta Fukyotei 1st LM line 1 5・- @ 2 wiring eyebrows (Base Z, amplifier, swearing E Ichikini wealth name Og 1st l wiring eyebrows and trout U note 4 interpretation layer Φ bottom I: vagina 6th tag T; guidance J which contact part 7 --- @ I's intelligence layer and the second division layer 9 Konggu upper part / - 1-Bit strategy Z-W Subumunftransukgu F3-} Runjisugu area 41 f's f! Edge layer δ - 11th 2 distribution (zens amplifier, cantering signal enhancement)
1 Back f, E section layer t, and the conspirators, bottom 1: Form eight, r; Condag with the conductive tank} capital 4 --- Sensation Ambly Transistor Gut 5, W section layer 8, 4 Ei 9゜-Drain Boiled'' [Kanju/6--So K stock maki 9 lumps If. /2 --Ikzetsukanko l3 ・111 luster. city city agitation town l4

Claims (2)

[Claims] (1) A semiconductor memory device characterized in that the upper part of a MOS transistor pair forming a differential circuit of a sense amplifier is covered with a layer having a lower elastic coefficient than a surface protective film. (2) The semiconductor memory device according to claim 1, wherein an aluminum wiring layer is used as the layer having a lower elastic modulus than the surface protective film.