KR20160113989A - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
- Publication number
- KR20160113989A KR20160113989A KR1020160034064A KR20160034064A KR20160113989A KR 20160113989 A KR20160113989 A KR 20160113989A KR 1020160034064 A KR1020160034064 A KR 1020160034064A KR 20160034064 A KR20160034064 A KR 20160034064A KR 20160113989 A KR20160113989 A KR 20160113989A
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- KR
- South Korea
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- channel transistor
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- semiconductor device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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- H01L27/11807—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
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- H01L21/8238—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
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- H01L29/66871—
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- H01L29/66878—
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- H01L29/7831—
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- H01L29/785—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/061—Manufacture or treatment of FETs having Schottky gates
- H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
- H10D30/0614—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs using processes wherein the final gate is made after the completion of the source and drain regions, e.g. gate-last processes using dummy gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/061—Manufacture or treatment of FETs having Schottky gates
- H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
- H10D30/0616—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs using processes wherein the final gate is made before the completion of the source and drain regions, e.g. gate-first processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
- H10D84/909—Microarchitecture
- H10D84/922—Microarchitecture relative P to N transistor sizes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
- H10D84/909—Microarchitecture
- H10D84/922—Microarchitecture relative P to N transistor sizes
- H10D84/925—Microarchitecture relative P to N transistor sizes for delay time adaptation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
-
- H01L2027/11822—
-
- H01L2027/11825—
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JPJP-P-2015-059529 | 2015-03-23 | ||
| JP2015059529A JP6396834B2 (ja) | 2015-03-23 | 2015-03-23 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20160113989A true KR20160113989A (ko) | 2016-10-04 |
Family
ID=55451086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020160034064A Withdrawn KR20160113989A (ko) | 2015-03-23 | 2016-03-22 | 반도체 장치 |
Country Status (6)
| Country | Link |
|---|---|
| US (5) | US9768172B2 (enExample) |
| EP (1) | EP3073528A1 (enExample) |
| JP (1) | JP6396834B2 (enExample) |
| KR (1) | KR20160113989A (enExample) |
| CN (2) | CN105990339B (enExample) |
| TW (1) | TW201705371A (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6396834B2 (ja) * | 2015-03-23 | 2018-09-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US10141256B2 (en) * | 2016-04-21 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and layout design thereof |
| US9972571B1 (en) * | 2016-12-15 | 2018-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Logic cell structure and method |
| WO2018150913A1 (ja) * | 2017-02-16 | 2018-08-23 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| US10325845B2 (en) | 2017-06-21 | 2019-06-18 | Qualcomm Incorporated | Layout technique for middle-end-of-line |
| CN109509747B (zh) * | 2017-09-15 | 2021-07-06 | 联华电子股份有限公司 | 具有标准单元的集成电路 |
| WO2019116883A1 (ja) * | 2017-12-12 | 2019-06-20 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| US10985272B2 (en) * | 2018-11-05 | 2021-04-20 | Samsung Electronics Co., Ltd. | Integrated circuit devices including vertical field-effect transistors |
| US11183576B2 (en) * | 2019-02-13 | 2021-11-23 | Micron Technology, Inc. | Gate electrode layout with expanded portions over active and isolation regions |
| US11404415B2 (en) | 2019-07-05 | 2022-08-02 | Globalfoundries U.S. Inc. | Stacked-gate transistors |
| CN113517274B (zh) * | 2020-07-24 | 2025-03-25 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
| US12354952B2 (en) * | 2022-04-14 | 2025-07-08 | Qualcomm Incorporated | Integrated circuits (ICs) employing multi-pattern metallization to optimize metal interconnect spacing for improved performance and related fabrication methods |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006132172A1 (ja) | 2005-06-07 | 2006-12-14 | Nec Corporation | フィン型電界効果型トランジスタ、半導体装置及びその製造方法 |
Family Cites Families (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2621612B2 (ja) | 1990-08-11 | 1997-06-18 | 日本電気株式会社 | 半導体集積回路 |
| JP4565700B2 (ja) * | 1999-05-12 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2001007293A (ja) * | 1999-06-25 | 2001-01-12 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| US6426650B1 (en) * | 1999-12-28 | 2002-07-30 | Koninklijke Philips Electronics, N.V. | Integrated circuit with metal programmable logic having enhanced reliability |
| US7053424B2 (en) * | 2002-10-31 | 2006-05-30 | Yamaha Corporation | Semiconductor integrated circuit device and its manufacture using automatic layout |
| JP4778689B2 (ja) | 2004-06-16 | 2011-09-21 | パナソニック株式会社 | 標準セル、標準セルライブラリおよび半導体集積回路 |
| US7338817B2 (en) * | 2005-03-31 | 2008-03-04 | Intel Corporation | Body bias compensation for aged transistors |
| WO2007034548A1 (ja) * | 2005-09-22 | 2007-03-29 | Fujitsu Limited | 信号伝達回路、その信号伝達回路を含む半導体装置、その半導体回路装置の設計方法、及び、その設計方法を実現するcad装置 |
| US9563733B2 (en) * | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
| US7812373B2 (en) * | 2007-02-12 | 2010-10-12 | Infineon Technologies Ag | MuGFET array layout |
| JP5236300B2 (ja) * | 2008-02-06 | 2013-07-17 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| JP5292005B2 (ja) * | 2008-07-14 | 2013-09-18 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
| JP2011029249A (ja) | 2009-07-22 | 2011-02-10 | Renesas Electronics Corp | 半導体装置 |
| JP4892044B2 (ja) * | 2009-08-06 | 2012-03-07 | 株式会社東芝 | 半導体装置 |
| CN103151346B (zh) * | 2011-12-07 | 2016-11-23 | 阿尔特拉公司 | 静电放电保护电路 |
| US8723268B2 (en) * | 2012-06-13 | 2014-05-13 | Synopsys, Inc. | N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch |
| JP2014075507A (ja) * | 2012-10-05 | 2014-04-24 | Renesas Electronics Corp | 半導体装置 |
| US9123565B2 (en) * | 2012-12-31 | 2015-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Masks formed based on integrated circuit layout design having standard cell that includes extended active region |
| CN105493264B (zh) * | 2013-08-23 | 2018-06-01 | 株式会社索思未来 | 半导体集成电路装置 |
| WO2015029280A1 (ja) * | 2013-08-28 | 2015-03-05 | パナソニック株式会社 | 半導体集積回路装置 |
| CN108922887B (zh) * | 2013-09-04 | 2022-12-09 | 株式会社索思未来 | 半导体装置 |
| US9397101B2 (en) * | 2014-03-06 | 2016-07-19 | Qualcomm Incorporated | Stacked common gate finFET devices for area optimization |
| US9412742B2 (en) * | 2014-06-10 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout design for manufacturing a memory cell |
| US9418728B2 (en) * | 2014-07-24 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual-port static random-access memory cell |
| JP6449082B2 (ja) * | 2014-08-18 | 2019-01-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP6396834B2 (ja) * | 2015-03-23 | 2018-09-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP6495145B2 (ja) * | 2015-09-11 | 2019-04-03 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2017063096A (ja) * | 2015-09-24 | 2017-03-30 | ルネサスエレクトロニクス株式会社 | 半導体装置および認証システム |
| US9620509B1 (en) * | 2015-10-30 | 2017-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Static random access memory device with vertical FET devices |
| TWI726869B (zh) * | 2016-02-24 | 2021-05-11 | 聯華電子股份有限公司 | 靜態隨機存取記憶體的佈局結構及其製作方法 |
| KR102434991B1 (ko) * | 2016-04-26 | 2022-08-22 | 삼성전자주식회사 | 집적 회로 및 집적 회로의 설계 방법 |
| TWI681542B (zh) * | 2016-05-04 | 2020-01-01 | 聯華電子股份有限公司 | 靜態隨機存取記憶體的佈局圖案 |
| TWI675454B (zh) * | 2016-07-04 | 2019-10-21 | 聯華電子股份有限公司 | 靜態隨機存取記憶體的佈局圖案 |
| JP2018164055A (ja) * | 2017-03-27 | 2018-10-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US10733352B2 (en) * | 2017-11-21 | 2020-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit and layout method for standard cell structures |
-
2015
- 2015-03-23 JP JP2015059529A patent/JP6396834B2/ja active Active
-
2016
- 2016-02-21 US US15/049,127 patent/US9768172B2/en active Active
- 2016-03-01 EP EP16158030.3A patent/EP3073528A1/en active Pending
- 2016-03-17 CN CN201610188337.9A patent/CN105990339B/zh active Active
- 2016-03-17 CN CN201620251282.7U patent/CN205645809U/zh not_active Expired - Fee Related
- 2016-03-21 TW TW105108610A patent/TW201705371A/zh unknown
- 2016-03-22 KR KR1020160034064A patent/KR20160113989A/ko not_active Withdrawn
-
2017
- 2017-08-15 US US15/677,546 patent/US9991263B2/en active Active
-
2018
- 2018-05-07 US US15/973,186 patent/US20180254276A1/en not_active Abandoned
-
2019
- 2019-01-07 US US16/241,048 patent/US10541240B2/en active Active
- 2019-12-11 US US16/710,894 patent/US10903214B2/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006132172A1 (ja) | 2005-06-07 | 2006-12-14 | Nec Corporation | フィン型電界効果型トランジスタ、半導体装置及びその製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105990339A (zh) | 2016-10-05 |
| US20190139958A1 (en) | 2019-05-09 |
| US20180254276A1 (en) | 2018-09-06 |
| US10903214B2 (en) | 2021-01-26 |
| CN205645809U (zh) | 2016-10-12 |
| CN105990339B (zh) | 2021-08-17 |
| US9991263B2 (en) | 2018-06-05 |
| US10541240B2 (en) | 2020-01-21 |
| US20170373065A1 (en) | 2017-12-28 |
| US20160284707A1 (en) | 2016-09-29 |
| JP6396834B2 (ja) | 2018-09-26 |
| JP2016181537A (ja) | 2016-10-13 |
| US20200119017A1 (en) | 2020-04-16 |
| US9768172B2 (en) | 2017-09-19 |
| EP3073528A1 (en) | 2016-09-28 |
| TW201705371A (zh) | 2017-02-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20160322 |
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| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination |