JP5236300B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
- Publication number
- JP5236300B2 JP5236300B2 JP2008026545A JP2008026545A JP5236300B2 JP 5236300 B2 JP5236300 B2 JP 5236300B2 JP 2008026545 A JP2008026545 A JP 2008026545A JP 2008026545 A JP2008026545 A JP 2008026545A JP 5236300 B2 JP5236300 B2 JP 5236300B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- transistor
- wiring
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 64
- 238000010586 diagram Methods 0.000 description 28
- 238000009434 installation Methods 0.000 description 21
- 239000002184 metal Substances 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 7
- 230000000630 rising effect Effects 0.000 description 7
- 230000008859 change Effects 0.000 description 5
- 230000007704 transition Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000012938 design process Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
12 VDD配線
13、13a トランジスタ抵抗領域
14 基本バッファ回路
15 初段インバータ
16 出力インバータ
20、20a 機能セルエリア
21、21a Pウェル
22、22a Nウェル
31〜37、39〜48、51〜57、61、62 配線
C00〜C05、C10〜C15、C20〜C22、C23〜C25 コンタクト
IN 入力端
MN1、NM2 NMOSトランジスタ
MP1、NP2 PMOSトランジスタ
MR1〜MR6 NMOSトランジスタ抵抗
MR11〜MR16 PMOSトランジスタ抵抗
OUT 出力端
Claims (8)
- 第1の電圧が供給される第1の電源配線と、
第2の電圧が供給され、前記第1の電源配線と平行に配線された第2の電源配線と、
前記第1の電源配線と前記第2の電源配線の一部を2辺とする略矩形の領域にそれぞれ設けられた複数のスタンダードセルと、少なくとも1つのトランジスタ抵抗領域とを備えた半導体集積回路であって、
前記スタンダードセルが、それぞれ、
前記第1の電源配線に沿って一定の高さに設けられた第1の第1導電型ウェルと、
前記第2の電源配線に沿って前記第2の電源配線と前記第1の第1導電型のウェルとの間に一定の高さに設けられた第1の第2導電型ウェルと、
前記第1の第1導電型ウェルの中に設けられた第2導電型MOSトランジスタと、
前記第1の第2導電型ウェルの中に設けられた第1導電型MOSトランジスタと、
を含み、
前記トランジスタ抵抗領域が、
前記第1の電源配線と前記第2の電源配線との一部を2辺とする略矩形の第2の第1または第2導電型ウェルと、
前記第2の第1または第2導電型ウェルの中に設けられた該導電型ウェルと逆導電型である複数のMOSトランジスタ抵抗と、
を含み、
前記複数のMOSトランジスタ抵抗のうち、任意の数のトランジスタ抵抗を前記第1導電型MOSトランジスタのドレインと前記第2導電型MOSトランジスタのドレインとの間に直列形態、並列形態あるいは直列並列組み合わせた形態で配線可能となるように構成することを特徴とする半導体集積回路装置。 - 前記任意の数のトランジスタ抵抗をコンタクト及び/または配線のマスクオプションによって配線可能とすることを特徴とする請求項1記載の半導体集積回路装置。
- 前記スタンダードセルにおいて、
前記第2導電型MOSトランジスタのソースを前記第1の電源配線に接続し、前記第1導電型MOSトランジスタのソースを前記第2の電源配線に接続し、前記第1導電型MOSトランジスタおよび前記第2導電型MOSトランジスタのゲートを共通に接続して入力端とし、前記第1または第2導電型MOSトランジスタのドレインを出力端とすることを特徴とする請求項1記載の半導体集積回路装置。 - 第1導電型である前記複数のMOSトランジスタ抵抗は、それぞれのゲートが前記第1の電源配線に接続されたトランジスタ抵抗であることを特徴とする請求項1記載の半導体集積回路装置。
- 第2導電型である前記複数のMOSトランジスタ抵抗は、それぞれのゲートが前記第2の電源配線に接続されたトランジスタ抵抗であることを特徴とする請求項1記載の半導体集積回路装置。
- 前記複数のMOSトランジスタ抵抗は、それぞれトランジスタサイズの異なる複数種類のトランジスタ抵抗を含むことを特徴とする請求項1、4、5のいずれか一に記載の半導体集積回路装置。
- 前記スタンダードセルと前記トランジスタ抵抗領域とを隣接して配置し、前記第1および第2の第1導電型ウェルを共通のウェル領域とするか、または前記第1および第2の第2導電型ウェルを共通のウェル領域とすることを特徴とする請求項1記載の半導体集積回路装置。
- 前記マスクオプションに係る配線領域は、配線ルールの最小間隔の整数倍で配置される配線を含み、前記マスクオプションに係る配線間の未配線部にダミー用の配線を配置可能とすることを特徴とする請求項2記載の半導体集積回路装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008026545A JP5236300B2 (ja) | 2008-02-06 | 2008-02-06 | 半導体集積回路装置 |
US12/320,187 US7843214B2 (en) | 2008-02-06 | 2009-01-21 | Semiconductor integrated circuit device having standard cell including resistance element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008026545A JP5236300B2 (ja) | 2008-02-06 | 2008-02-06 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009188189A JP2009188189A (ja) | 2009-08-20 |
JP5236300B2 true JP5236300B2 (ja) | 2013-07-17 |
Family
ID=40931074
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008026545A Expired - Fee Related JP5236300B2 (ja) | 2008-02-06 | 2008-02-06 | 半導体集積回路装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7843214B2 (ja) |
JP (1) | JP5236300B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9928337B2 (en) | 2016-04-26 | 2018-03-27 | Samsung Electronics Co., Ltd. | Integrated circuit and design method for same |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5552775B2 (ja) * | 2009-08-28 | 2014-07-16 | ソニー株式会社 | 半導体集積回路 |
WO2014073361A1 (ja) * | 2012-11-06 | 2014-05-15 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
JP6396834B2 (ja) | 2015-03-23 | 2018-09-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6580847B2 (ja) * | 2015-03-25 | 2019-09-25 | ラピスセミコンダクタ株式会社 | 半導体装置 |
JP7364922B2 (ja) * | 2018-12-26 | 2023-10-19 | 株式会社ソシオネクスト | 半導体集積回路装置 |
US11764220B2 (en) | 2020-04-27 | 2023-09-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device by patterning a serpentine cut pattern |
US11005467B1 (en) * | 2020-05-18 | 2021-05-11 | Realtek Semiconductor Corp. | Low-noise duty cycle correction circuit and method thereof |
JP2022174366A (ja) * | 2021-05-11 | 2022-11-24 | エイブリック株式会社 | サーマルヘッド駆動用集積回路及びサーマルヘッド駆動用集積回路の製造方法。 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05102826A (ja) * | 1991-10-04 | 1993-04-23 | Nec Corp | 半導体集積回路装置 |
JPH05326713A (ja) * | 1992-05-19 | 1993-12-10 | Toshiba Corp | 半導体装置の出力回路 |
JP2000269343A (ja) * | 1999-03-16 | 2000-09-29 | Kawasaki Steel Corp | 半導体集積回路 |
JP2002124630A (ja) * | 2000-10-17 | 2002-04-26 | Seiko Epson Corp | 半導体装置 |
JP2007095787A (ja) * | 2005-09-27 | 2007-04-12 | Nec Electronics Corp | 半導体集積回路 |
US7417480B2 (en) * | 2006-07-14 | 2008-08-26 | International Business Machines Corporation | Duty cycle correction circuit whose operation is largely independent of operating voltage and process |
KR100925364B1 (ko) * | 2007-02-13 | 2009-11-09 | 주식회사 하이닉스반도체 | 듀티 비를 보정하기 위한 클럭 변조 회로, 및 이를포함하는 스펙트럼 확산 클럭 발생 장치 |
-
2008
- 2008-02-06 JP JP2008026545A patent/JP5236300B2/ja not_active Expired - Fee Related
-
2009
- 2009-01-21 US US12/320,187 patent/US7843214B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9928337B2 (en) | 2016-04-26 | 2018-03-27 | Samsung Electronics Co., Ltd. | Integrated circuit and design method for same |
Also Published As
Publication number | Publication date |
---|---|
US20090195282A1 (en) | 2009-08-06 |
US7843214B2 (en) | 2010-11-30 |
JP2009188189A (ja) | 2009-08-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5236300B2 (ja) | 半導体集積回路装置 | |
CN109314110B (zh) | 用于基于鳍片计数的扩散的标准单元架构 | |
US20180183414A1 (en) | Cell of transmission gate free circuit and integrated circuit layout including the same | |
US8525552B2 (en) | Semiconductor integrated circuit device having a plurality of standard cells for leakage current suppression | |
US7469389B2 (en) | Standard cell library, method of designing semiconductor integrated circuit, semiconductor integrated circuit pattern, and semiconductor integrated circuit | |
US20100270600A1 (en) | Semiconductor integrated circuit device and method of designing the same | |
US20080105929A1 (en) | Semiconductor integrated circuit | |
US10748933B2 (en) | Semiconductor device | |
US7589361B2 (en) | Standard cells, LSI with the standard cells and layout design method for the standard cells | |
US7747976B2 (en) | Semiconductor cell with power layout not contacting sides of its rectangular boundary and semiconductor circuit utilizing semiconductor cells | |
US7334210B2 (en) | Semiconductor integrated circuit and method of designing the same | |
JP2009272340A (ja) | 半導体集積回路 | |
JP4743469B2 (ja) | 半導体集積回路装置とクロック分配方法 | |
KR20070067603A (ko) | 게이트 어레이 | |
US6426650B1 (en) | Integrated circuit with metal programmable logic having enhanced reliability | |
CN111934684B (zh) | 一种缓冲器、时钟网格电路和信号驱动方法 | |
JP3996735B2 (ja) | 半導体装置 | |
JP2006261458A (ja) | クロックツリー安定化装置、および半導体装置 | |
US11410987B2 (en) | Chip and method for manufacturing a chip | |
JP4523290B2 (ja) | セルレイアウト、半導体集積回路装置、半導体集積回路の設計方法並びに半導体集積回路の半導体製造方法 | |
JP2016046479A (ja) | 半導体装置及び半導体装置の設計方法とプログラム | |
JP2007027314A (ja) | 半導体集積回路装置 | |
US6924666B2 (en) | Integrated logic circuit and hierarchical design method thereof | |
JP4441541B2 (ja) | 半導体装置 | |
JP2023110556A (ja) | 半導体集積回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100812 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130108 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130212 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130312 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130327 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160405 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |