JP7364922B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- JP7364922B2 JP7364922B2 JP2020563138A JP2020563138A JP7364922B2 JP 7364922 B2 JP7364922 B2 JP 7364922B2 JP 2020563138 A JP2020563138 A JP 2020563138A JP 2020563138 A JP2020563138 A JP 2020563138A JP 7364922 B2 JP7364922 B2 JP 7364922B2
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- 239000004065 semiconductor Substances 0.000 title claims description 125
- 239000002070 nanowire Substances 0.000 description 96
- 239000010410 layer Substances 0.000 description 27
- 239000000758 substrate Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
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Description
図1~図3は第1実施形態に係るセルのレイアウト構造の例を示す図であり、図1(a),(b)は平面図、図2は平面視横方向における断面図、図3(a)~(c)は平面視縦方向における断面図である。具体的には、図1(a)は下部、すなわち基板に近い側に形成された立体構造トランジスタ(ここではP型ナノワイヤFET)を含む部分を示し、図1(b)は上部、すなわち基板から遠い側に形成された立体構造トランジスタ(ここではN型ナノワイヤFET)を含む部分を示す。図2は線X1-X1’の断面、図3(a)は線Y1-Y1’の断面、図3(b)は線Y2-Y2’の断面、図3(c)は線Y3-Y3’の断面である。
図5は第1実施形態に係るセルのレイアウト構造の他の例を示す平面図であり、(a)はP型ナノワイヤFETを含む下部、(b)はN型ナノワイヤFETを含む上部を示す。また図6は図5に示すセルの回路図である。図6に示すように、図5に示すセルは、P型トランジスタP11,P12およびN型トランジスタN11,N12を有し、入力A,B、出力Yの2入力NAND回路を実現している。なお、セルの断面構造は、第1実施形態で示した図2および図3を参照して、理解することができる。
図7は第1実施形態に係るセルのレイアウト構造の他の例を示す平面図であり、(a)はP型ナノワイヤFETを含む下部、(b)はN型ナノワイヤFETを含む上部を示す。また図8は図7に示すセルの回路図である。図8に示すように、図7に示すセルは、P型トランジスタP21,P22およびN型トランジスタN21,N22を有し、入力A,B、出力Yの2入力NOR回路を実現している。なお、セルの断面構造は、第1実施形態で示した図2および図3を参照して、理解することができる。
図9は第2実施形態に係るセルのレイアウト構造の例を示す平面図であり、(a)はP型ナノワイヤFETを含む下部、(b)はN型ナノワイヤFETを含む上部を示す。図9に示すセルは、いわゆるダブルハイトセルであり、第1実施形態で示したセル(シングルハイトセル)の2倍の高さ(Y方向におけるサイズ)を有する。また図10は図9に示すセルの回路図である。図10に示すように、図9に示すセルは、P型トランジスタP41,P42,P43,P44,P45,P46およびN型トランジスタN41,N42,N43,N44,N45,N46を有し、入力A,B,C、出力Yの3入力NAND回路を実現している。なお、セルの断面構造は、第1実施形態で示した図2および図3を参照して、理解することができる。
本実施形態に係るセルは、下部はN型FETを含み、上部はP型FETを含むように構成してもよい。この場合は、セルのY方向における両端に電源電圧VSSを供給する電源配線を設けて、セルのY方向における中央部に電源電圧VDDを供給する電源配線を設けて、上の例と同様のレイアウトとすればよい。
図11および図12は上述の各実施形態で示したセルを用いた回路ブロックのレイアウトの例である。図11はセルの下部を図示しており、図12はセルの上部を図示している。C11,C12,C13,C14,C15,C16,C17,C18は第1実施形態で示したインバータセル、C21,C22,C23は第1実施形態で示した2入力NANDセル、C31,C32,C33は第1実施形態で示した2入力NORセル、C41は第2実施形態で示したダブルハイトの3入力NANDセルである。ダブルハイトの3入力NANDセルC41およびインバータセルC15は、X方向において反転されている。2入力NORセルC32、インバータセルC13および2入力NANDセルC22は、Y方向において反転されている。インバータセルC14は、X方向およびY方向において反転されている。
42,44 ローカル配線
53 コンタクト
142,145 ローカル配線
243,246 ローカル配線
411,412,413 電源配線
441~449 ローカル配線
457 コンタクト
501,502,511,512,513,514 ローカル配線
VDD,VSS 電源電圧
P1,P11,P12,P21,P22,P41~P46 P型トランジスタ
N1,N11,N12,N21,N22,N41~N46 N型トランジスタ
C11~C18,C21~C23,C31~C33,C41 スタンダードセル
Claims (11)
- スタンダードセルを含む半導体集積回路装置であって、
前記スタンダードセルは、
第1方向に延び、第1電源電圧を供給する第1電源配線と、
前記第1方向に延び、前記第1電源電圧と異なる第2電源電圧を供給する第2電源配線と、
平面視で前記第1電源配線と前記第2電源配線との間にある第1導電型の立体構造トランジスタである、第1トランジスタと、
深さ方向において前記第1トランジスタよりも上に形成されており、平面視で前記第1電源配線と前記第2電源配線との間にある第2導電型の立体構造トランジスタである、第2トランジスタと、
前記第1方向と垂直をなす方向である第2方向に延びており、前記第1トランジスタのソースまたはドレインと接続された第1ローカル配線と、
前記第2方向に延びており、前記第1ローカル配線と平面視で重なっており、前記第2トランジスタのソースまたはドレインと接続された第2ローカル配線とを備え、
前記第1および第2ローカル配線は、いずれも、平面視で、前記第1および第2電源配線と重なっている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1および第2ローカル配線は、いずれも、前記第1および第2電源配線と電気的に分離されている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1ローカル配線と前記第2ローカル配線とは、コンタクトを介して接続されている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1および第2ローカル配線は、前記第2方向における両端の位置がそろっている
ことを特徴とする半導体集積回路装置。 - スタンダードセルを含む半導体集積回路装置であって、
前記スタンダードセルは、
第1方向に延び、第1電源電圧を供給する第1電源配線と、
前記第1方向に延び、前記第1電源電圧を供給する第2電源配線と、
前記第1電源配線と前記第2電源配線との間において前記第1方向に延び、前記第1電源電圧と異なる第2電源電圧を供給する第3電源配線と、
平面視で前記第1電源配線と前記第3電源配線との間にある第1導電型の立体構造トランジスタである、第1トランジスタと、
深さ方向において前記第1トランジスタよりも上に形成されており、平面視で前記第1電源配線と前記第3電源配線との間にある第2導電型の立体構造トランジスタである、第2トランジスタと、
前記第1方向と垂直をなす方向である第2方向に延びており、前記第1トランジスタのソースまたはドレインと接続された第1ローカル配線と、
前記第2方向に延びており、前記第1ローカル配線と平面視で重なっており、前記第2トランジスタのソースまたはドレインと接続された第2ローカル配線とを備え、
前記第1および第2ローカル配線のうち少なくともいずれか一方は、平面視で、前記第1、第2および第3電源配線と重なっている
ことを特徴とする半導体集積回路装置。 - 請求項5記載の半導体集積回路装置において、
前記少なくともいずれか一方のローカル配線は、前記第1、第2および第3電源配線と電気的に分離されている
ことを特徴とする半導体集積回路装置。 - 請求項5記載の半導体集積回路装置において、
前記第1および第2ローカル配線の両方が、平面視で、前記第1、第2および第3電源配線と重なっている
ことを特徴とする半導体集積回路装置。 - 請求項7記載の半導体集積回路装置において、
前記第1ローカル配線と前記第2ローカル配線とは、コンタクトを介して接続されている
ことを特徴とする半導体集積回路装置。 - 請求項7記載の半導体集積回路装置において、
前記第1および第2ローカル配線は、前記第2方向における両端の位置がそろっている
ことを特徴とする半導体集積回路装置。 - 請求項5記載の半導体集積回路装置において、
前記スタンダードセルは、
平面視で前記第2電源配線と前記第3電源配線との間にある前記第1導電型の立体構造トランジスタである、第3トランジスタと、
深さ方向において前記第3トランジスタよりも上に形成されており、平面視で前記第2電源配線と前記第3電源配線との間にある前記第2導電型の立体構造トランジスタである、第4トランジスタとを備え、
前記第1ローカル配線は、前記第3トランジスタのソースまたはドレインと接続されており、
前記第2ローカル配線は、前記第4トランジスタのソースまたはドレインと接続されている
ことを特徴とする半導体集積回路装置。 - 第1スタンダードセルと、前記第1スタンダードセルと第1方向において隣接配置された第2スタンダードセルとを含む半導体集積回路装置であって、
前記第1スタンダードセルは、
前記第1方向に延び、第1電源電圧を供給する第1電源配線と、
前記第1方向に延び、前記第1電源電圧と異なる第2電源電圧を供給する第2電源配線と、
平面視で前記第1電源配線と前記第2電源配線との間にある第1導電型の立体構造トランジスタである、第1トランジスタと、
深さ方向において前記第1トランジスタよりも上に形成されており、平面視で前記第1電源配線と前記第2電源配線との間にある第2導電型の立体構造トランジスタである、第2トランジスタとを備え、
前記第2スタンダードセルは、
前記第1方向に延び、前記第1電源電圧を供給する第3電源配線と、
前記第1方向に延び、前記第2電源電圧を供給する第4電源配線と、
平面視で前記第3電源配線と前記第4電源配線との間にある前記第1導電型の立体構造トランジスタである、第3トランジスタと、
深さ方向において前記第3トランジスタよりも上に形成されており、平面視で前記第3電源配線と前記第4電源配線との間にある前記第2導電型の立体構造トランジスタである、第4トランジスタとを備え、
前記第1スタンダードセルと前記第2スタンダードセルとの間の境界であるセル境界を挟んで、前記第1トランジスタと前記第3トランジスタとが対向しているとともに、前記第2トランジスタと前記第4トランジスタとが対向しており、
前記第1スタンダードセルは、
前記第1方向と垂直をなす方向である第2方向に延びており、前記第1トランジスタのソースまたはドレインのうち前記セル境界に近い方に接続された第1ローカル配線と、
前記第2方向に延びており、前記第1ローカル配線と平面視で重なっており、前記第2トランジスタのソースまたはドレインのうち前記セル境界に近い方に接続された第2ローカル配線とを備え、
前記第1および第2ローカル配線は、いずれも、平面視で、前記第1および第2電源配線と重なっている
ことを特徴とする半導体集積回路装置。
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