KR20100091164A - 직렬-연결된 집적회로를 스택하는 방법 및 이 방법으로 제조한 멀티-칩 장치 - Google Patents

직렬-연결된 집적회로를 스택하는 방법 및 이 방법으로 제조한 멀티-칩 장치 Download PDF

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KR20100091164A
KR20100091164A KR1020107009261A KR20107009261A KR20100091164A KR 20100091164 A KR20100091164 A KR 20100091164A KR 1020107009261 A KR1020107009261 A KR 1020107009261A KR 20107009261 A KR20107009261 A KR 20107009261A KR 20100091164 A KR20100091164 A KR 20100091164A
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KR
South Korea
Prior art keywords
chip
chips
signal pads
pads
pad
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Ceased
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KR1020107009261A
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English (en)
Korean (ko)
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홍 범 편
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모사이드 테크놀로지스 인코퍼레이티드
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Priority claimed from US12/168,354 external-priority patent/US8399973B2/en
Application filed by 모사이드 테크놀로지스 인코퍼레이티드 filed Critical 모사이드 테크놀로지스 인코퍼레이티드
Publication of KR20100091164A publication Critical patent/KR20100091164A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

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  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1020107009261A 2007-12-20 2008-12-18 직렬-연결된 집적회로를 스택하는 방법 및 이 방법으로 제조한 멀티-칩 장치 Ceased KR20100091164A (ko)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US1534507P 2007-12-20 2007-12-20
US61/015,345 2007-12-20
US3220308P 2008-02-28 2008-02-28
US61/032,203 2008-02-28
US12/168,354 2008-07-07
US12/168,354 US8399973B2 (en) 2007-12-20 2008-07-07 Data storage and stackable configurations
US12/236,874 US7791175B2 (en) 2007-12-20 2008-09-24 Method for stacking serially-connected integrated circuits and multi-chip device made from same
US12/236,874 2008-09-24

Publications (1)

Publication Number Publication Date
KR20100091164A true KR20100091164A (ko) 2010-08-18

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Application Number Title Priority Date Filing Date
KR1020107009261A Ceased KR20100091164A (ko) 2007-12-20 2008-12-18 직렬-연결된 집적회로를 스택하는 방법 및 이 방법으로 제조한 멀티-칩 장치

Country Status (8)

Country Link
US (3) US7791175B2 (https=)
EP (1) EP2220681B1 (https=)
JP (1) JP5633885B2 (https=)
KR (1) KR20100091164A (https=)
CN (1) CN101842896B (https=)
ES (1) ES2499392T3 (https=)
TW (1) TW200941695A (https=)
WO (1) WO2009079772A1 (https=)

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Publication number Publication date
CN101842896A (zh) 2010-09-22
TW200941695A (en) 2009-10-01
EP2220681B1 (en) 2014-06-18
US7791175B2 (en) 2010-09-07
EP2220681A4 (en) 2011-03-02
US20090020855A1 (en) 2009-01-22
ES2499392T3 (es) 2014-09-29
JP2011507283A (ja) 2011-03-03
JP5633885B2 (ja) 2014-12-03
WO2009079772A1 (en) 2009-07-02
US20110163423A1 (en) 2011-07-07
US8383514B2 (en) 2013-02-26
CN101842896B (zh) 2013-11-06
EP2220681A1 (en) 2010-08-25
US20100297812A1 (en) 2010-11-25
WO2009079772A8 (en) 2010-01-14
US7923370B2 (en) 2011-04-12

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