KR20070121849A - 반도체 장치 및 그 제조 방법 - Google Patents
반도체 장치 및 그 제조 방법 Download PDFInfo
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- KR20070121849A KR20070121849A KR1020077026951A KR20077026951A KR20070121849A KR 20070121849 A KR20070121849 A KR 20070121849A KR 1020077026951 A KR1020077026951 A KR 1020077026951A KR 20077026951 A KR20077026951 A KR 20077026951A KR 20070121849 A KR20070121849 A KR 20070121849A
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Abstract
Description
Claims (8)
- 반도체 기판 위에 형성되고, 제 1 게이트 절연막과, 상기 제 1 게이트 절연막 위에 형성된 제 1 게이트 전극과, 상기 반도체 기판 내에 형성된 제 1 소스/드레인 영역을 갖는 제 1 MIS 트랜지스터와,상기 반도체 기판 위에 형성되고, 상기 제 1 게이트 절연막보다도 두꺼운 제 2 게이트 절연막과, 상기 제 2 게이트 절연막 위에 형성된 제 2 게이트 전극과, 상기 반도체 기판 내에 형성된 제 2 소스/드레인 영역과, 상기 제 2 소스/드레인 영역에 접속하여 상기 반도체 기판 내에 형성된 밸러스트 저항을 갖는 제 2 MIS 트랜지스터와,상기 밸러스트 저항 위에, 상기 제 2 게이트 절연막보다 얇은 절연막을 통하여 형성된 살리사이드 블록 절연막과,상기 제 1 소스/드레인 영역 위 및 상기 제 2 소스/드레인 영역 위에 형성된 실리사이드막을 갖는 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,상기 절연막의 막 두께는 상기 제 1 게이트 절연막의 막 두께 이하인 것을 특징으로 하는 반도체 장치.
- 제 1 항 또는 제 2 항에 있어서,상기 제 1 소스/드레인 영역은 상기 제 1 게이트 전극에 정합(整合)하여 형성된 제 1 불순물층을 가지며,상기 제 2 소스/드레인 영역은 상기 제 2 게이트 전극에 정합하여 형성된 제 2 불순물층을 가지며,상기 밸러스트 저항은 상기 제 1 불순물층과 동시에 형성된 제 3 불순물층과, 상기 제 2 불순물층과 동시에 형성된 제 4 불순물층에 의해 구성되어 있는 것을 특징으로 하는 반도체 장치.
- 제 3 항에 있어서,상기 제 1 불순물층은 상기 제 1 소스/드레인 영역의 LDD 영역 또는 익스텐션 영역이며,상기 제 2 불순물층은 상기 제 2 소스/드레인 영역의 LDD 영역 또는 익스텐션 영역인 것을 특징으로 하는 반도체 장치.
- 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,상기 제 1 게이트 전극의 측벽 부분에 형성된 측벽 절연막을 더 가지며,상기 절연막의 막 두께와, 상기 사이드 월 스페이서 아래에서의 상기 제 1 게이트 절연막의 막 두께가 동일한 것을 특징으로 하는 반도체 장치.
- 반도체 기판의 제 1 영역에 제 1 MIS 트랜지스터가 형성되고, 상기 반도체 기판의 제 2 영역에 밸러스트 저항을 갖는 제 2 MIS 트랜지스터가 형성된 반도체 장치의 제조 방법으로서,상기 반도체 기판을 열산화하여, 상기 제 1 영역 및 상기 제 2 영역에 제 1 절연막을 형성하는 공정과,상기 제 1 영역 및 상기 제 2 영역의 상기 밸러스트 저항 형성 영역의 상기 제 1 절연막을 제거하는 공정과,상기 반도체 기판을 열산화하여, 상기 제 1 영역 및 상기 밸러스트 저항 형성 영역에 제 1 게이트 절연막을 형성하고, 상기 밸러스트 저항 형성 영역을 제외한 상기 제 2 영역에 상기 제 1 절연막을 추가 산화하여 이루어지는 제 2 게이트 절연막을 형성하는 공정과,상기 제 1 게이트 절연막 위에 제 1 게이트 전극을 형성하고, 상기 제 2 게이트 절연막 위에 제 2 게이트 전극을 형성하는 공정과,상기 제 1 영역 및 상기 밸러스트 저항 형성 영역의 상기 반도체 기판에, 상기 제 1 게이트 전극을 마스크로 하여 불순물을 도입해서, 제 1 불순물층을 형성하는 공정과,상기 제 2 영역의 상기 반도체 기판에, 상기 제 2 게이트 전극을 마스크로 하여 불순물을 도입해서, 제 2 불순물층을 형성하는 공정을 가지며,상기 밸러스트 저항 형성 영역에, 상기 제 1 불순물층 및 상기 제 2 불순물층을 갖는 상기 밸러스트 저항을 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제 6 항에 있어서,상기 제 2 불순물층을 형성하는 공정 후에,제 2 절연막을 형성하는 공정과,상기 밸러스트 저항 형성 영역의 상기 제 2 절연막 위에 마스크막을 형성하는 공정과,상기 마스크막을 마스크로 하여 상기 제 2 절연막을 에치백하고, 상기 제 1 게이트 전극 및 상기 제 2 게이트 전극의 측벽 부분에 측벽 절연막을 형성하여, 상기 밸러스트 저항 형성 영역에 살리사이드 블록 절연막을 형성하는 공정과,상기 측벽 절연막 및 상기 살리사이드 블록 절연막에 의해 덮여 있지 않은 상기 반도체 기판 위에 선택적으로 실리사이드막을 형성하는 공정을 갖는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제 7 항에 있어서,상기 측벽 절연막 및 상기 살리사이드 블록 절연막을 형성하는 공정 후에, 상기 제 1 게이트 전극, 상기 제 2 게이트 전극, 상기 측벽 절연막 및 상기 살리사이드 블록 절연막을 마스크로 하여 불순물을 도입해서, 상기 제 1 영역의 상기 반도체 기판 내에 제 3 불순물층을 형성하고, 상기 제 2 영역의 상기 반도체 기판 내에 제 4 불순물층을 형성하는 공정을 더 갖는 것을 특징으로 하는 반도체 장치의 제조 방법.
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