JP6407900B2 - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
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- JP6407900B2 JP6407900B2 JP2016020237A JP2016020237A JP6407900B2 JP 6407900 B2 JP6407900 B2 JP 6407900B2 JP 2016020237 A JP2016020237 A JP 2016020237A JP 2016020237 A JP2016020237 A JP 2016020237A JP 6407900 B2 JP6407900 B2 JP 6407900B2
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- 239000004065 semiconductor Substances 0.000 title claims description 88
- 238000009792 diffusion process Methods 0.000 claims description 74
- 239000012535 impurity Substances 0.000 claims description 17
- 230000004048 modification Effects 0.000 description 27
- 238000012986 modification Methods 0.000 description 27
- 230000000694 effects Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
- H01L27/0738—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
以下に、第1実施形態に係る半導体集積回路について説明する。
まず、図1〜図5を用いて本実施形態に係る半導体集積回路の構成について説明する。図1には半導体集積回路の平面レイアウトを示し、図2〜図4には半導体集積回路の断面構造を示し、図5には半導体集積回路の等価回路の構成を示している。
次に、本実施形態の効果について説明する。本実施形態に係る半導体集積回路1によれば、半導体集積回路1のESD耐性を向上することが出来る。この詳細について以下に説明する。
次に、第2実施形態に係る半導体集積回路について説明する。本実施形態は、上記第1実施形態で説明した構成を、Tie−Lowセルに適用したものである。以下では第1実施形態と異なる点を説明する。
まず、図6〜図8を用いて本実施形態に係る半導体集積回路1の構成について説明する。図6には半導体集積回路1の平面レイアウトを示し、図7には半導体集積回路1の断面構造を示し、図8には半導体集積回路1の等価回路の構成を示している。本実施形態に係る半導体集積回路1は、第1実施形態と各配線の接続関係が異なる。
本実施形態によれば、Tie−Lowセルにおいても第1実施形態と同様の効果が得られる。すなわち本実施形態に係る半導体集積回路1は、Tie−Lowセルの共通ゲート(配線層40)を、PMOSトランジスタ30のソース配線(配線層31)が接続されたp+不純物拡散領域14Aに接続する。つまり、共通ゲートがトランジスタ30の拡散領域14A及びソース配線を介して高電圧電源線51に電気的に接続される。そして、拡散領域14Aを実質的に抵抗素子60として機能させる。
次に、第3実施形態に係る半導体集積回路1について説明する。本実施形態は、上記第1及び第2実施形態で説明した構成を、デカップリングセルに適用したものである。以下では第1及び第2実施形態と異なる点を説明する。
まず、図9〜図13を用いて本実施形態に係る半導体集積回路1の構成について説明する。図9には半導体集積回路1の平面レイアウトを示し、図10〜図12には半導体集積回路1の断面構造を示し、図13には半導体集積回路1の等価回路の構成を示している。本実施形態に係る半導体集積回路1は、ソースを共通とするNMOSトランジスタ20の組と、ソースを共通とするPMOSトランジスタ30の組とを備え、且つ第1実施形態と各配線の接続関係が異なる。
本実施形態によれば、デカップリングセルにおいても第1実施形態と同等の効果が得られる。この詳細について以下に説明する。
次に、第3実施形態に係る半導体集積回路1の変形例1〜3について説明する。本変形例は、上記第3実施形態で説明した構成において、組み合わせるトランジスタの構成を変更した物である。以下では第3実施形態と異なる点を説明する。
まず、図14〜図16を用いて変形例1に係る半導体集積回路1について説明する。図14には半導体集積回路1の平面レイアウトを示し、図15には半導体集積回路1の断面構造を示し、図16には半導体集積回路1の等価回路の構成を示している。
次に、図17を用いて変形例2に係る半導体集積回路1について説明する。図17には半導体集積回路1の等価回路の構成を示している。
次に、図18を用いて変形例3に係る半導体集積回路1について説明する。図18には半導体集積回路1の等価回路の構成を示している。
上記実施形態に係る半導体集積回路1は、第1トランジスタ≪30、図5≫及び第2トランジスタ≪20、図5≫と、抵抗素子≪60、図5≫とを備える。第1トランジスタは、一端が第1電源線≪51、図1≫に接続される。第2トランジスタは、一端及び他端が第1電源線と異なる第2電源線≪50、図1≫に接続され、ゲート≪40、図1≫を第1トランジスタと共有する。抵抗素子は、第2トランジスタのソース又はドレインに対応する不純物拡散領域≪13A、図4≫で形成され、一端が第1及び第2トランジスタのゲートに接続され、他端が第2トランジスタの一端に接続される。
Claims (5)
- 一端が第1電源線に接続された第1トランジスタと、
一端及び他端が前記第1電源線と異なる第2電源線に接続され、ゲートを前記第1トランジスタと共有する第2トランジスタと、
一端が前記ゲートに接続され、他端が前記第2トランジスタの前記一端に接続された抵抗素子と、
を備え、
前記抵抗素子は、前記第2トランジスタのソース又はドレインに対応する不純物拡散領域で形成される、半導体集積回路。 - 前記第1トランジスタの他端は論理回路の入力端子に接続され、
前記第1トランジスタはPMOSトランジスタであり、
前記第2トランジスタはNMOSトランジスタであり、
前記第1及び第2電源線にはそれぞれ第1電圧及び前記第1電圧より低い第2電圧が印加される、請求項1に記載の半導体集積回路。 - 前記第1トランジスタの他端は論理回路の入力端子に接続され、
前記第1トランジスタはNMOSトランジスタであり、
前記第2トランジスタはPMOSトランジスタであり、
前記第1及び第2電源線にはそれぞれ第1電圧及び前記第1電圧より高い第2電圧が印加される、請求項1に記載の半導体集積回路。 - 前記第1トランジスタの他端は前記第1電源線に接続され、
前記第1トランジスタはPMOSトランジスタであり、
前記第2トランジスタはNMOSトランジスタであり、
前記第1及び第2電源線にはそれぞれ第1電圧及び前記第1電圧より低い第2電圧が印加される、請求項1に記載の半導体集積回路。 - 一端が前記第1トランジスタの前記一端と共有され、他端が前記第1電源線に接続された第3トランジスタと、
一端が前記第2トランジスタの前記一端と共有され、他端が前記第2電源線に接続され、ゲートが前記第3トランジスタと共有され且つ前記抵抗素子の前記一端に接続された第4トランジスタと、
をさらに備え、
前記第3トランジスタはPMOSトランジスタであり、
前記第4トランジスタはNMOSトランジスタである、請求項4に記載の半導体集積回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016020237A JP6407900B2 (ja) | 2016-02-04 | 2016-02-04 | 半導体集積回路 |
US15/247,588 US10453840B2 (en) | 2016-02-04 | 2016-08-25 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016020237A JP6407900B2 (ja) | 2016-02-04 | 2016-02-04 | 半導体集積回路 |
Related Child Applications (1)
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JP2018115241A Division JP6510120B2 (ja) | 2018-06-18 | 2018-06-18 | 半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
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JP2017139387A JP2017139387A (ja) | 2017-08-10 |
JP6407900B2 true JP6407900B2 (ja) | 2018-10-17 |
Family
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JP2016020237A Expired - Fee Related JP6407900B2 (ja) | 2016-02-04 | 2016-02-04 | 半導体集積回路 |
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US (1) | US10453840B2 (ja) |
JP (1) | JP6407900B2 (ja) |
Cited By (1)
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US11309333B2 (en) | 2019-12-24 | 2022-04-19 | Kioxia Corporation | Semiconductor integrated circuit |
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JP6617590B2 (ja) * | 2016-02-03 | 2019-12-11 | 富士通株式会社 | 半導体装置 |
KR102101537B1 (ko) * | 2017-07-06 | 2020-04-17 | 매그나칩 반도체 유한회사 | 타이하이 및 타이로우 회로 |
US11562953B2 (en) * | 2018-10-23 | 2023-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell having stacked pick-up region |
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KR20220043738A (ko) | 2020-09-29 | 2022-04-05 | 삼성전자주식회사 | 비대칭 디커플링 셀을 포함하는 집적 회로 및 이를 설계하는 방법 |
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2016
- 2016-02-04 JP JP2016020237A patent/JP6407900B2/ja not_active Expired - Fee Related
- 2016-08-25 US US15/247,588 patent/US10453840B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11309333B2 (en) | 2019-12-24 | 2022-04-19 | Kioxia Corporation | Semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
US20170229457A1 (en) | 2017-08-10 |
JP2017139387A (ja) | 2017-08-10 |
US10453840B2 (en) | 2019-10-22 |
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