JP5947580B2 - デカップルキャパシタセル、セルベースic、セルベースicのレイアウトシステムおよびレイアウト方法 - Google Patents
デカップルキャパシタセル、セルベースic、セルベースicのレイアウトシステムおよびレイアウト方法 Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims description 147
- 238000000034 method Methods 0.000 title claims description 49
- 239000004065 semiconductor Substances 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 22
- 238000013461 design Methods 0.000 claims description 16
- 238000003780 insertion Methods 0.000 claims description 14
- 230000037431 insertion Effects 0.000 claims description 14
- 230000010365 information processing Effects 0.000 claims description 5
- 239000000284 extract Substances 0.000 claims description 2
- 238000012986 modification Methods 0.000 description 7
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- 230000000052 comparative effect Effects 0.000 description 5
- 238000012938 design process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- H—ELECTRICITY
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- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
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- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
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- H01L27/0733—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with capacitors only
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- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H01L28/60—Electrodes
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- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
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Description
(セルベースICのレイアウトシステム)
図1〜図5を参照して、実施の形態に係るセルベースICのレイアウトシステム100について説明する。
ここで、図3〜図7を参照して、第1のデカップルキャパシタ20および第2のデカップルキャパシタ30で構成されるデカップルキャパシタセルについて説明する。
図9には、デカップルキャパシタセルの比較例を示す。
図10から図12を参照して、レイアウト設計中のセルベースIC101における基本セルで占有されていない未使用領域の抽出およびデカップルキャパシタセルの挿入について説明する。
図13のフローチャートを参照して、セルベースICのレイアウトシステム100で実行されるデカップルキャパシタセル挿入処理の処理手順について説明する。
図14から図17を参照して、デカップルキャパシタセル1の変形例について説明する。
上述のセルベースICのレイアウトシステム100によってレイアウト設計されたセルベースIC101について、前出の図1から図3、図10から図12を参照して説明する。
上記のように、実施の形態によって記載したが、この開示の一部をなす論述および図面は例示的なものであり、この発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例および運用技術が明らかとなろう。
20…第1のデカップルキャパシタ
30…第2のデカップルキャパシタ
31a…デカップルキャパシタ部材
32…デカップルキャパシタ部材
33…デカップルキャパシタ部材
34…デカップルキャパシタ部材
40a…電源レール
50…n型半導体層
52…ソース領域
54…ドレイン領域
56…ゲート絶縁膜
58…ゲート電極
60…バックゲート電極
70…半導体基板
80…アクティブ領域
81…コンタクト
83…ポリシリコン・ゲート
85…制限抵抗
100…レイアウトシステム
101…セルベースIC
103…基本セル
103a…一部領域
150…未使用領域
160…1層メタル
170…2層メタル
200…情報処理装置
201…未使用領域抽出手段
202…挿入数算出手段
203…デカップルキャパシタセル挿入手段
300…入力装置
400…表示装置
500…レイアウトデータ出力部
600…フォトマスク作成装置
901…nMOSトランジスタ
902…pMOSトランジスタ
BG…バックゲート配線
DP…ドレイン配線
DSS…接地配線
GP…ゲート配線
VDD…電源配線
VSS…接地配線
Claims (12)
- pMOSトランジスタのみで構成される第1のデカップルキャパシタと、
2層のメタル層で構成される第2のデカップルキャパシタと
を備え、
セルベースICにおいて基本セルで占有されていない未使用領域に配置され、電源配線および接地配線と接続されることを特徴とするデカップルキャパシタセル。 - 半導体基板と、
前記半導体基板に形成され、複数の半導体素子と内部配線とを有し、前記半導体素子間を前記内部配線で接続して所定の機能を有するようにした複数の基本セルと、
前記半導体基板に形成され、前記基本セル間を接続する外部配線を有する配線領域と、
前記半導体素子への電源供給を行う電源配線および接地配線と、
前記半導体基板に形成され、pMOSトランジスタのみで構成される第1のデカップルキャパシタと、
前記半導体基板に形成される2層のメタル層で構成される第2のデカップルキャパシタと
を備え、
前記第1のデカップルキャパシタおよび前記第2のデカップルキャパシタで構成されるデカップルキャパシタセルは、前記基本セルで占有されていない未使用領域に配置され、前記電源配線および前記接地配線と接続されることを特徴とするセルベースIC。 - 前記第2のデカップルキャパシタは、
前記半導体基板に形成される第1層メタルで構成され、面方向に延設されるデカップルキャパシタ部材と、
前記半導体基板に形成される第2層メタルで構成され、前記デカップルキャパシタ部材の一部と対向し、前記電源配線および前記接地配線を形成する電源レールと
から構成されることを特徴とする請求項2に記載のセルベースIC。 - 前記デカップルキャパシタセル毎に、前記電源レールは2本ずつ形成され、前記各電源レールは平行となるように設けられることを特徴とする請求項3に記載のセルベースIC。
- 前記第1のデカップルキャパシタと前記第2のデカップルキャパシタとは、前記電源配線と前記接地配線との間に並列接続されることを特徴とする請求項2〜4のいずれか1項に記載のセルベースIC。
- 前記デカップルキャパシタ部材は、面方向に複数の凹凸を有する櫛歯形状とされることを特徴とする請求項3〜5のいずれか1項に記載のセルベースIC。
- 前記デカップルキャパシタ部材は、短冊形状とされることを特徴とする請求項3〜5のいずれか1項に記載のセルベースIC。
- 前記デカップルキャパシタ部材は、面方向に複数の凹凸を有する櫛歯形状と、短冊形状との組み合わせで構成されることを特徴とする請求項3〜5のいずれか1項に記載のセルベースIC。
- 前記デカップルキャパシタ部材は、面方向に複数の凹凸を有するフィッシュボーン形状とされることを特徴とする請求項3〜5のいずれか1項に記載のセルベースIC。
- 情報処理装置を用いて、セルベースICのレイアウト設計を行うレイアウトシステムであって、
レイアウト設計中のセルベースICにおいて、基本セルで占有されていない未使用領域を抽出する未使用領域抽出手段と、
pMOSトランジスタのみで構成される第1のデカップルキャパシタと、2層のメタル層で構成される第2のデカップルキャパシタとで構成されるデカップルキャパシタセルについて、前記未使用領域に挿入可能な数を算出する挿入数算出手段と、
算出された数に応じて前記デカップルキャパシタセルを挿入するデカップルキャパシタセル挿入手段と
を備えることを特徴とするセルベースICのレイアウトシステム。 - 基本セルで占有されていない未使用領域を抽出するステップと、
pMOSトランジスタのみで構成される第1のデカップルキャパシタと、2層のメタル層で構成される第2のデカップルキャパシタとで構成されるデカップルキャパシタセルについて、前記未使用領域に挿入可能な数を算出するステップと、
算出された数に応じて前記未使用領域に前記デカップルキャパシタセルを挿入するステップと
を有することを特徴とするセルベースICのレイアウト方法。 - 配線ショートの修正を行うか否かを判定するステップをさらに有し、
前記配線ショートの修正を行うと判定された場合には、前記未使用領域に前記デカップルキャパシタセルを挿入した後に、挿入した前記デカップルキャパシタセルのショートを修正し、
前記配線ショートの修正を行わないと判定された場合には、前記未使用領域において、配線とショートしない位置に前記デカップルキャパシタセルを挿入することを特徴とする請求項11に記載のセルベースICのレイアウト方法。
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JP2012066844A JP5947580B2 (ja) | 2012-03-23 | 2012-03-23 | デカップルキャパシタセル、セルベースic、セルベースicのレイアウトシステムおよびレイアウト方法 |
US13/848,923 US8975677B2 (en) | 2012-03-23 | 2013-03-22 | Decoupling capacitor cell, cell-based IC, cell-based IC layout system and method, and portable device |
US14/608,410 US9472546B2 (en) | 2012-03-23 | 2015-01-29 | Cell-based IC layout system and cell-based IC layout method |
US15/262,921 US20160379970A1 (en) | 2012-03-23 | 2016-09-12 | Decoupling capacitor cell, cell-based ic, and portable device |
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JP6599715B2 (ja) * | 2015-09-30 | 2019-10-30 | ラピスセミコンダクタ株式会社 | 耐圧評価用素子及び耐圧評価用素子の製造方法 |
JP6407900B2 (ja) * | 2016-02-04 | 2018-10-17 | 株式会社東芝 | 半導体集積回路 |
WO2017139241A1 (en) | 2016-02-08 | 2017-08-17 | Chaologix, Inc. | Side channel aware automatic place and route |
US10380315B2 (en) | 2016-09-15 | 2019-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit and method of forming an integrated circuit |
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2012
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2013
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US20130248957A1 (en) | 2013-09-26 |
US20160379970A1 (en) | 2016-12-29 |
US8975677B2 (en) | 2015-03-10 |
US20150137202A1 (en) | 2015-05-21 |
US9472546B2 (en) | 2016-10-18 |
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