KR20040012898A - 반도체 장치와 그 제조방법, 회로 기판 및 전자 기기 - Google Patents
반도체 장치와 그 제조방법, 회로 기판 및 전자 기기 Download PDFInfo
- Publication number
- KR20040012898A KR20040012898A KR10-2003-7015902A KR20037015902A KR20040012898A KR 20040012898 A KR20040012898 A KR 20040012898A KR 20037015902 A KR20037015902 A KR 20037015902A KR 20040012898 A KR20040012898 A KR 20040012898A
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- South Korea
- Prior art keywords
- semiconductor substrate
- groove
- insulating layer
- semiconductor device
- etching
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 159
- 238000004519 manufacturing process Methods 0.000 title claims description 51
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 238000005530 etching Methods 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims description 61
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 24
- 238000005520 cutting process Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 10
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 9
- 239000011259 mixed solution Substances 0.000 claims description 7
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 6
- 229910017604 nitric acid Inorganic materials 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000000243 solution Substances 0.000 claims description 3
- 238000000638 solvent extraction Methods 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims 2
- 238000002161 passivation Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
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- 238000001459 lithography Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 3
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- 229910000679 solder Inorganic materials 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
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- 229910052782 aluminium Inorganic materials 0.000 description 1
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- 239000000126 substance Substances 0.000 description 1
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Abstract
Description
Claims (33)
- (a) 집적 회로가 형성된 반도체 기판에 제1면에서 오목부를 형성하는 단계,(b) 상기 오목부의 저면 및 내벽면에 절연층를 설치하는 단계,(c) 상기 절연층의 내측에 도전부를 설치하는 단계,(d) 상기 반도체 기판에 대한 에칭량이 상기 절연층에 대한 에칭량보다 많아지는 성질의 제1에천트에 의해서, 상기 반도체 기판의 상기 제1면과는 반대측의 제2면을 에칭하고, 상기 절연층으로 덮인 상태에서 상기 도전부를 돌출시키는 단계, 및(e) 상기 도전부에 잔류물을 형성하지 않고 적어도 상기 절연층을 에칭하는 성질의 제2에천트에 의해서, 상기 절연층 중의 적어도 상기 오목부의 상기 저면에 형성된 부분을 에칭하여 상기 도전부를 노출시키는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 제1에천트는 SF6또는 CF4또는 Cl2가스인 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제2항에 있어서,상기 (d)단계를 드라이 에칭 장치를 사용하여 실행하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 제1에천트는 플루오르화 수소산 및 질산의 혼합액 또는 플루오르화 수소산, 질산 및 초산의 혼합액인 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 제2에천트는 Ar, CF4의 혼합 가스 또는 O2, CF4의 혼합 가스인 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제5항에 있어서,상기 (e)단계를, 드라이 에칭 장치를 사용하여 실행하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 제2에천트는 플루오르화 수소산액 또는 플루오르화 수소산과 플루오르화 암모늄의 혼합액인 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 절연층을 SiO2또는 SiN으로 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 (e)단계에서, 상기 도전부의 외층부도 에칭하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제9항에 있어서,상기 도전부의 상기 외층부를, 중심부와는 다른 재료로 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제10항에 있어서,상기 도전부의 상기 중심부를 Cu, W, 도프드 폴리실리콘 중의 어느 것으로 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제10항에 있어서,상기 도전부의 상기 외층부 중 적어도 일부를 TiW, TiN 또는 TaN으로 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 (d)단계 전에, 상기 반도체 기판의 상기 제2면을 상기 절연층의 바로 전까지 연마하는 것을 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 (e)단계의 에칭은, 상기 (d)단계의 에칭보다, 상기 반도체 기판에 대한 에칭 속도가 느린 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 반도체 기판은 반도체 웨이퍼이고, 다수의 상기 집적 회로가 형성되어, 각각의 상기 집적 회로에 대응하여 상기 오목부를 형성하며,상기 반도체 기판을 절단하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제15항에 있어서,상기 반도체 기판을 절단하는 단계는,상기 제1면에 상기 반도체 기판의 절단 라인에 따라 홈을 형성하는 단계, 및 상기 홈이 슬릿이 되도록, 상기 제2면으로부터 상기 홈의 바닥부를 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제16항에 있어서,상기 홈을 절삭에 의해서 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제16항에 있어서,상기 홈을 에칭에 의해서 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제16항에 있어서,상기 (a)단계에서, 상기 홈을 상기 오목부와 같은 프로세스로 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제16항에 있어서,상기 (d)단계 전에 상기 반도체 기판의 상기 제2면을 상기 절연층의 바로 전까지 연마하는 단계를 더 포함하고,상기 홈을 상기 오목부보다 깊게 형성하며,상기 반도체 기판의 상기 제2면의 연마에 의해 상기 홈의 바닥부를 제거하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제16항에 있어서,상기 (b)단계에서 상기 절연층을 상기 홈 내에도 설치하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제21항에 있어서,상기 (d)단계에서 상기 홈의 바닥부에 형성된 상기 절연층을 상기 제2면으로부터 돌출시켜,상기 (e)단계에서 상기 제2에천트에 의해서, 상기 홈의 바닥부에 형성된 상기 절연층을 에칭하여 제거하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제16항에 있어서,상기 홈의 바닥부를 제거하는 단계를, 상기 홈 내에 상기 반도체 기판의 재료가 노출한 상태로 실행하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제23항에 있어서,상기 (d)단계에서 상기 제1에천트에 의해서 상기 반도체 기판의 일부로부터 구성되어 이루어지는 상기 홈의 바닥부를 에칭하여 제거하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제16항에 있어서,상기 반도체 기판을 절단하는 단계를, 절단된 다수의 반도체 칩이 탈락하지 않도록, 상기 반도체 기판의 상기 제1면을 유지판에 부착하여 실행하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제16항에 있어서,상기 홈을, 상기 다수의 집적 회로를 갖는 다수의 반도체 칩을 구획하는 영역에만 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항 내지 제26항 중 어느 한 항에 있어서,상기 방법에 의해 제조된 다수의 반도체 장치를 적층하고, 상기 도전부를 통하여 전기적 접속을 도모하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항 내지 제26항 중 어느 한 항에 기재된 방법에 의해서 제조되어 이루어지는 것을 특징으로 하는 반도체 장치.
- 제27항에 기재된 방법에 의해 제조되어 이루어지는 것을 특징으로 하는 반도체 장치.
- 제28항에 기재된 반도체 장치가 실장되어 이루어지는 것을 특징으로 하는 회로 기판.
- 제29항에 기재된 반도체 장치가 실장되어 이루어지는 것을 특징으로 하는 회로 기판.
- 제28항에 기재된 반도체 장치를 갖는 것을 특징으로 하는 전자 기기.
- 제29항에 기재된 반도체 장치를 갖는 것을 특징으로 하는 전자 기기.
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JP2003007277A JP4110390B2 (ja) | 2002-03-19 | 2003-01-15 | 半導体装置の製造方法 |
PCT/JP2003/003302 WO2003079431A1 (en) | 2002-03-19 | 2003-03-19 | Semiconductor device and its manufacturing method, circuit board, and electric apparatus |
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2003
- 2003-01-15 JP JP2003007277A patent/JP4110390B2/ja not_active Expired - Lifetime
- 2003-03-19 CN CNB038007061A patent/CN1279604C/zh not_active Expired - Lifetime
- 2003-03-19 WO PCT/JP2003/003302 patent/WO2003079431A1/ja not_active Application Discontinuation
- 2003-03-19 TW TW092106054A patent/TWI282592B/zh not_active IP Right Cessation
- 2003-03-19 KR KR1020037015902A patent/KR100552987B1/ko active IP Right Grant
- 2003-03-19 EP EP03710425A patent/EP1391924A4/en not_active Withdrawn
- 2003-11-10 US US10/703,573 patent/US7029937B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100707902B1 (ko) * | 2004-09-10 | 2007-04-16 | 가부시끼가이샤 도시바 | 반도체 장치의 제조 방법 |
KR100844997B1 (ko) * | 2006-12-29 | 2008-07-09 | 삼성전자주식회사 | 반도체 패키지, 반도체 스택 패키지, 패키지들을 제조하는방법 |
Also Published As
Publication number | Publication date |
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TWI282592B (en) | 2007-06-11 |
WO2003079431A1 (en) | 2003-09-25 |
CN1533603A (zh) | 2004-09-29 |
KR100552987B1 (ko) | 2006-02-15 |
US20040142574A1 (en) | 2004-07-22 |
EP1391924A1 (en) | 2004-02-25 |
EP1391924A4 (en) | 2005-06-15 |
JP2003347474A (ja) | 2003-12-05 |
CN1279604C (zh) | 2006-10-11 |
TW200305229A (en) | 2003-10-16 |
US7029937B2 (en) | 2006-04-18 |
JP4110390B2 (ja) | 2008-07-02 |
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