KR100782632B1 - 절연막의 에칭 방법 - Google Patents

절연막의 에칭 방법 Download PDF

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Publication number
KR100782632B1
KR100782632B1 KR1020037008446A KR20037008446A KR100782632B1 KR 100782632 B1 KR100782632 B1 KR 100782632B1 KR 1020037008446 A KR1020037008446 A KR 1020037008446A KR 20037008446 A KR20037008446 A KR 20037008446A KR 100782632 B1 KR100782632 B1 KR 100782632B1
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KR
South Korea
Prior art keywords
gas
etching
ratio
insulating film
fluorocarbon
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KR1020037008446A
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English (en)
Korean (ko)
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KR20030066747A (ko
Inventor
아다치겐지
고바야시노리유키
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동경 엘렉트론 주식회사
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Application filed by 동경 엘렉트론 주식회사 filed Critical 동경 엘렉트론 주식회사
Publication of KR20030066747A publication Critical patent/KR20030066747A/ko
Application granted granted Critical
Publication of KR100782632B1 publication Critical patent/KR100782632B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
KR1020037008446A 2000-12-21 2001-12-13 절연막의 에칭 방법 KR100782632B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000389151 2000-12-21
JPJP-P-2000-00389151 2000-12-21
PCT/JP2001/010932 WO2002050885A1 (fr) 2000-12-21 2001-12-13 Procede de gravage pour film isolant

Publications (2)

Publication Number Publication Date
KR20030066747A KR20030066747A (ko) 2003-08-09
KR100782632B1 true KR100782632B1 (ko) 2007-12-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020037008446A KR100782632B1 (ko) 2000-12-21 2001-12-13 절연막의 에칭 방법

Country Status (7)

Country Link
US (1) US20040035826A1 (ja)
JP (1) JP4008352B2 (ja)
KR (1) KR100782632B1 (ja)
CN (1) CN1249788C (ja)
AU (1) AU2002222631A1 (ja)
TW (1) TW521335B (ja)
WO (1) WO2002050885A1 (ja)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4164643B2 (ja) * 2002-07-17 2008-10-15 日本ゼオン株式会社 ドライエッチング方法及びパーフルオロ−２−ペンチンの製造方法
JP4963156B2 (ja) * 2003-10-03 2012-06-27 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4723871B2 (ja) * 2004-06-23 2011-07-13 株式会社日立ハイテクノロジーズ ドライエッチング装置
US7794616B2 (en) * 2004-08-09 2010-09-14 Tokyo Electron Limited Etching gas, etching method and etching gas evaluation method
KR100650835B1 (ko) * 2004-10-29 2006-11-27 에스티마이크로일렉트로닉스 엔.브이. 반도체 소자의 소자분리막 형성방법
US7416676B2 (en) * 2005-02-16 2008-08-26 Tokyo Electron Limited Plasma etching method and apparatus, control program for performing the etching method, and storage medium storing the control program
JP2007242753A (ja) * 2006-03-07 2007-09-20 Tokyo Electron Ltd プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体
US7517804B2 (en) 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
JP5214152B2 (ja) * 2007-02-08 2013-06-19 東京エレクトロン株式会社 プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体
JP4450245B2 (ja) * 2007-06-07 2010-04-14 株式会社デンソー 半導体装置の製造方法
JP4978512B2 (ja) * 2008-02-29 2012-07-18 日本ゼオン株式会社 プラズマエッチング方法
US20110265883A1 (en) * 2010-04-30 2011-11-03 Applied Materials, Inc. Methods and apparatus for reducing flow splitting errors using orifice ratio conductance control
CN103578973B (zh) * 2012-07-29 2017-09-05 中国科学院微电子研究所 氮化硅高深宽比孔的循环刻蚀方法
CN103903978B (zh) * 2012-12-27 2016-12-28 南亚科技股份有限公司 蚀刻方法
CN106297831B (zh) * 2015-05-21 2020-04-21 新科实业有限公司 在衬底形成图案的方法
JP6836959B2 (ja) 2017-05-16 2021-03-03 東京エレクトロン株式会社 プラズマ処理装置、処理システム、及び、多孔質膜をエッチングする方法
US10276439B2 (en) 2017-06-02 2019-04-30 International Business Machines Corporation Rapid oxide etch for manufacturing through dielectric via structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990032708A (ko) * 1997-10-20 1999-05-15 구자홍 간헐 영상 녹화재생장치
KR19990063377A (ko) * 1997-12-24 1999-07-26 가네꼬 히사시 반도체 장치 제조 방법
KR20000004863A (ko) * 1998-06-09 2000-01-25 다니구찌 이찌로오, 기타오카 다카시 집적 회로 장치
KR20000071381A (ko) * 1999-02-25 2000-11-25 이데이 노부유끼 드라이 에칭 방법 및 반도체 장치의 제조 방법

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3038950B2 (ja) * 1991-02-12 2000-05-08 ソニー株式会社 ドライエッチング方法
JP3154128B2 (ja) * 1991-05-24 2001-04-09 ソニー株式会社 ドライエッチング方法
JP3116569B2 (ja) * 1992-06-29 2000-12-11 ソニー株式会社 ドライエッチング方法
TW394989B (en) * 1997-10-29 2000-06-21 Matsushita Electronics Corp Semiconductor device manufacturing and reaction room environment control method for dry etching device
US6159862A (en) * 1997-12-27 2000-12-12 Tokyo Electron Ltd. Semiconductor processing method and system using C5 F8
JPH11330046A (ja) * 1998-05-08 1999-11-30 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
US6297163B1 (en) * 1998-09-30 2001-10-02 Lam Research Corporation Method of plasma etching dielectric materials
US6316349B1 (en) * 1998-11-12 2001-11-13 Hyundai Electronics Industries Co., Ltd. Method for forming contacts of semiconductor devices
JP4230029B2 (ja) * 1998-12-02 2009-02-25 東京エレクトロン株式会社 プラズマ処理装置およびエッチング方法
US6417090B1 (en) * 1999-01-04 2002-07-09 Advanced Micro Devices, Inc. Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer
US6184107B1 (en) * 1999-03-17 2001-02-06 International Business Machines Corp. Capacitor trench-top dielectric for self-aligned device isolation
US6849193B2 (en) * 1999-03-25 2005-02-01 Hoiman Hung Highly selective process for etching oxide over nitride using hexafluorobutadiene
JP4578651B2 (ja) * 1999-09-13 2010-11-10 東京エレクトロン株式会社 プラズマ処理方法およびプラズマ処理装置、プラズマエッチング方法
JP2001135630A (ja) * 1999-11-10 2001-05-18 Matsushita Electronics Industry Corp 半導体装置の製造方法
US6326307B1 (en) * 1999-11-15 2001-12-04 Appllied Materials, Inc. Plasma pretreatment of photoresist in an oxide etch process
JP3400770B2 (ja) * 1999-11-16 2003-04-28 松下電器産業株式会社 エッチング方法、半導体装置及びその製造方法
US6337244B1 (en) * 2000-03-01 2002-01-08 Micron Technology, Inc. Method of forming flash memory
US6451703B1 (en) * 2000-03-10 2002-09-17 Applied Materials, Inc. Magnetically enhanced plasma etch process using a heavy fluorocarbon etching gas
US6337285B1 (en) * 2000-03-21 2002-01-08 Micron Technology, Inc. Self-aligned contact (SAC) etch with dual-chemistry process
JP4839506B2 (ja) * 2000-04-28 2011-12-21 ダイキン工業株式会社 ドライエッチング方法
KR100362834B1 (ko) * 2000-05-02 2002-11-29 삼성전자 주식회사 반도체 장치의 산화막 형성 방법 및 이에 의하여 제조된 반도체 장치
US7030029B2 (en) * 2000-05-12 2006-04-18 Tokyo Electron Limited Method of high selectivity SAC etching
US6362109B1 (en) * 2000-06-02 2002-03-26 Applied Materials, Inc. Oxide/nitride etching having high selectivity to photoresist
KR100363710B1 (ko) * 2000-08-23 2002-12-05 삼성전자 주식회사 셀프-얼라인 콘택 구조를 갖는 반도체 장치 및 그 제조방법
US6797639B2 (en) * 2000-11-01 2004-09-28 Applied Materials Inc. Dielectric etch chamber with expanded process window
WO2002039494A1 (fr) * 2000-11-08 2002-05-16 Daikin Industries, Ltd. Gaz de gravure seche et procede de gravure seche
JP4213871B2 (ja) * 2001-02-01 2009-01-21 株式会社日立製作所 半導体装置の製造方法
TW483111B (en) * 2001-06-08 2002-04-11 Promos Technologies Inc Method for forming contact of memory device
US6674241B2 (en) * 2001-07-24 2004-01-06 Tokyo Electron Limited Plasma processing apparatus and method of controlling chemistry
US6518164B1 (en) * 2001-11-30 2003-02-11 United Microelectronics Corp. Etching process for forming the trench with high aspect ratio

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990032708A (ko) * 1997-10-20 1999-05-15 구자홍 간헐 영상 녹화재생장치
KR19990063377A (ko) * 1997-12-24 1999-07-26 가네꼬 히사시 반도체 장치 제조 방법
KR20000004863A (ko) * 1998-06-09 2000-01-25 다니구찌 이찌로오, 기타오카 다카시 집적 회로 장치
KR20000071381A (ko) * 1999-02-25 2000-11-25 이데이 노부유끼 드라이 에칭 방법 및 반도체 장치의 제조 방법

Also Published As

Publication number Publication date
CN1249788C (zh) 2006-04-05
JP4008352B2 (ja) 2007-11-14
JPWO2002050885A1 (ja) 2004-04-22
KR20030066747A (ko) 2003-08-09
AU2002222631A1 (en) 2002-07-01
CN1483219A (zh) 2004-03-17
WO2002050885A1 (fr) 2002-06-27
US20040035826A1 (en) 2004-02-26
TW521335B (en) 2003-02-21

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