WO2002050885A1 - Procede de gravage pour film isolant - Google Patents

Procede de gravage pour film isolant Download PDF

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Publication number
WO2002050885A1
WO2002050885A1 PCT/JP2001/010932 JP0110932W WO0250885A1 WO 2002050885 A1 WO2002050885 A1 WO 2002050885A1 JP 0110932 W JP0110932 W JP 0110932W WO 0250885 A1 WO0250885 A1 WO 0250885A1
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Prior art keywords
gas
etching
ratio
insulating film
fluorocarbon
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PCT/JP2001/010932
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English (en)
Japanese (ja)
Inventor
Kenji Adachi
Noriyuki Kobayashi
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Tokyo Electron Limited
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Publication date
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Priority to KR1020037008446A priority Critical patent/KR100782632B1/ko
Priority to JP2002551894A priority patent/JP4008352B2/ja
Priority to AU2002222631A priority patent/AU2002222631A1/en
Priority to US10/451,107 priority patent/US20040035826A1/en
Publication of WO2002050885A1 publication Critical patent/WO2002050885A1/fr

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask

Definitions

  • the present invention relates to an insulating film etching method, and is particularly suitable for application to etching of a contact hole having a high aspect ratio.
  • the contact hole has a higher aspect ratio.
  • a C 5 F 8 ZAr / Oz-based etching gas is used. Was used.
  • An object of the present invention is to provide a method of etching an insulating film capable of improving an etching rate and a resist mask selectivity and suppressing a bowing shape.
  • a first fluorocarbon-based gas having C ⁇ 4 and a C / F ratio of 0.625 or more; a second Furuoroka one carbon-based gas F ratio is 0.5 or less, and the a r gas, characterized by using a mixed gas including a less and 0 2 gas.
  • the first fluorocarbon-based gas is used. It is possible to increase the resist mask selectivity by using the system gas, and it is possible to suppress the occurrence of the bowing shape and increase the etching rate by using the second fluorocarbon gas. And the selectivity of the resist mask can be improved.
  • the first fluorocarbon-based gas is a C 5 F 8 gas or a C 4 F 6 gas having a C of 4 or more and a C / F ratio of 0.625 or more. It is characterized by the following.
  • the second fluorocarbon-based gas is any one selected from CF 4 gas, C 2 F 6 gas, C 3 F 8 gas, and C 4 F 8 gas.
  • the etching species ( Mainly, CF X radicals) can be efficiently generated, and the etching rate can be further improved.
  • the flow rate ratio of the first fluorocarbon-based gas to the second fluorocarbon-based gas is 0.5 or more.
  • the mixed gas further includes a hydrofluorocarbon-based gas.
  • the Bon-based gas is preferably CH 2 F 2 gas.
  • the C / F ratio of the entire mixed gas is 0.5 or more.
  • the insulating film is a silicon oxide film.
  • a silicon nitride film is exposed in an upper layer or a lower layer in the etching of the silicon oxide film ( and the etching of the silicon oxide film is performed in a step of forming a self-aligned contact). It is characterized by being performed.
  • the temperature of the substrate on which the insulating film is formed is set to 80 to 120 ° C.
  • the etching rate, the resist mask selectivity, the bowing ratio, the bottom diameter ratio, and the silicon nitride film selectivity can be maintained at favorable values.
  • FIG. 1 is a sectional view showing a schematic configuration of an etching apparatus according to one embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing the structure of an etching sample according to one embodiment of the present invention, wherein FIG. 2 (a) shows a state before etching and FIG. 2 (b) shows a state after etching.
  • FIG. 3 is a diagram showing the etching characteristics when the type and flow ratio of the fluorocarbon according to one embodiment of the present invention are all set to a parameter.
  • FIG. 4 is a diagram showing a calculation result of a C / F ratio of the entire etching gas according to one embodiment of the present invention.
  • FIG. 5 is a diagram showing the relationship between the added amount of CF 4 and the etching characteristics according to one embodiment of the present invention.
  • FIG. 5 (a) shows the etching rate and the resist mask selection ratio
  • FIG. ratio shows a bottom diameter ratio
  • FIG. 6 is a diagram showing the relationship of C 2 F 6 pressurized weight and etching characteristics according to an embodiment of the present invention
  • FIG. 6 (a) the etching rate, the resist mask election indicates ⁇
  • FIG. 6 (b) baud Ing ratio shows a bottom diameter ratio
  • FIG. 7 is a diagram showing the relationship of C 3 F 8 pressurized volume and etching characteristics according to an embodiment of the present invention Yes
  • Fig. 7 (a) shows the etching rate and resist mask selection ratio
  • Fig. 7 (b) shows the Boeing ratio and the bottom diameter ratio
  • Fig. 8 shows the structure of the etching sample according to one embodiment of the present invention FIG.
  • FIG. 9 is a diagram showing the relationship between the added amount of CF 4 and the etching characteristics according to one embodiment of the present invention.
  • FIG. 10 is a diagram showing the temperature dependence of the etching characteristics according to one embodiment of the present invention.
  • FIG. 1 is a cross-sectional view showing a schematic configuration of an etching apparatus according to one embodiment of the present invention.
  • the first fluorocarbon-based gas is C 4 F 6 having a linear molecular structure
  • the second fluorocarbon-based gas is And CF 4
  • an upper electrode 2 and a susceptor 3 are provided in a processing chamber 1.
  • This susceptor 3 also serves as the lower electrode.
  • the upper electrode 2 is provided with a gas ejection hole 2 a for introducing an etching gas into the processing chamber 1.
  • the susceptor 3 is supported on a susceptor 4, and the susceptor 4 is held in the processing chamber 1 via an insulating plate 5.
  • High-frequency power supplies 13 and 11 are connected to the upper electrode 2 and the susceptor 3, respectively, to convert the etching gas introduced into the processing chamber 1 into plasma.
  • the susceptor support 4 is provided with a refrigerant chamber 10, and a refrigerant such as liquid nitrogen circulates in the refrigerant chamber 10 via the refrigerant supply pipe 10a and the refrigerant discharge pipe 10b. Then, the wafer W can be cooled by transferring the cold generated therefrom to the wafer W via the susceptor support 4 and the susceptor 3.
  • a refrigerant such as liquid nitrogen circulates in the refrigerant chamber 10 via the refrigerant supply pipe 10a and the refrigerant discharge pipe 10b. Then, the wafer W can be cooled by transferring the cold generated therefrom to the wafer W via the susceptor support 4 and the susceptor 3.
  • An electrostatic chuck 6 is provided on the susceptor 3.
  • the electrostatic chuck 6 has a configuration in which a conductive layer 7 is sandwiched between polyimide films 8a and 8b.
  • a DC high-voltage power supply 12 is connected to the conductive layer 7, and by applying a DC high voltage to the conductive layer 7, a cron force acts on the wafer W to fix the wafer W on the susceptor 3. Can be.
  • a gas passage 9 for introducing He gas is provided in the susceptor 3 and the electrostatic chuck 6.
  • the gas passage 9 is connected to a He gas supply source 18 via an opening / closing valve 18a and a flow control valve 18b, and can control the pressure of the H ⁇ gas on the back surface of the wafer W.
  • the processing chamber 1 is connected to a gas supply pipe 1 a and an exhaust pipe 1 b.
  • the exhaust pipe 1b is connected to a vacuum pump, and the pressure in the processing chamber 1 can be adjusted by evacuating the processing chamber 1 with the vacuum pump.
  • the wafer W on which the insulating film is formed is placed on the susceptor 3 and fixed by the electrostatic chuck 6.
  • the process chamber 1 is evacuated, while adjusting the pressure in the processing chamber 1, open the closing valves 14 a ⁇ 1 7 a, C4 F 6 gas, CF 4 gas, Ar gas Oyo Pi 0 2 Gas is introduced into the processing chamber 1.
  • C 4 F 6 gas, CF 4 gas flow rate ratio of Ar gas and O 2 gas may be adjusted by the flow amount adjusting valve 14 b ⁇ 17 b.
  • the flow ratio between C 4 F 6 gas and CF 4 gas ( ⁇ 4 F 6 gas flow rate ZCF4 gas flow rate) is preferably 0.5 or more in order to secure the resist mask selection ratio.
  • the etching gas is turned into plasma. Etching of the insulating film is performed.
  • the opening / closing valve 18a is opened, and He gas is supplied to the back side of the wafer W through the gas passage 9.
  • the cooling temperature of the wafer W can be controlled by adjusting the He gas pressure using the flow control valve 18b.
  • the etching condition is that the RF power of the upper electrode 2 and the susceptor 3 is 140- 2 About 100 W, pressure in processing chamber 1 is about 1.33 to 9.31 Pa (10 to 70 mTorr), temperature of susceptor 3 is about 20 to 20 ° C, wafer It is preferable that the temperature of W is about 80 to 120 ° C.
  • the C 4 F 6 gas which has a large number of C (carbon atoms) in the molecule, supplies a large amount of etching species such as CF-based radicals (CF *, CF 2 *, CF 3 *), It is possible to increase the resist selectivity while increasing the etching rate by accelerating the first deposition, but it is easy to generate a bowing shape.
  • etching species such as CF-based radicals (CF *, CF 2 *, CF 3 *)
  • C 4 F 6 gas is likely to cause bowing is that the carbon-based polymer is deposited in large quantities near the entrance of the contact hole, and consequently, deposition is less likely to occur below the deposit. This is because the etching of the side wall of the contact hole progresses in the portion.
  • the resist selectivity is improved because the oxygen contained in the oxide film is sputtered out on the etching surface of the oxide film and contributes to the decomposition of the carbon-based polymer.
  • the carbon-based polymer is not easily removed from the resist surface by ion impact or the like.
  • the CF 4 gas promotes etching while suppressing the deposition of the carbon-based polymer, so that the etching rate can be improved (especially by mixing CF 4 gas with C 4 F 6 gas).
  • the insulating film is, for example, an SiO 2 film and a PSG film. , BSG membrane, A BPSG film, an AsSG film, an AsPSG film, an AsBSG film, or the like may be used.
  • C 4 F 6 / CF 4 / Ar / 0 2 based gas instead of C 4 F 6 gas having a molecular structure of linear, cyclic molecule C 4 F 6 or C 5 F 8 gas having a structure may be used. Further, C 2 F 6 gas, C 3 F 8 gas, or C 4 F 8 gas may be used instead of CF 4 gas.
  • the method of mixing two different types of fluorocarbon gas with the Ar / 02 type gas has been described.
  • three or more different types of fluorocarbon gas may be used.
  • a hydrofluorocarbon-based gas having hydrogen in a molecular structure such as CH 2 F 2 gas and CH 3 F gas may be further added.
  • CH 2 F 2 gas, etc. it is possible to increase the CZF ratio of the etching gas and further improve the resist selectivity by capturing fluorine with hydrogen contained in the CH 2 F 2 gas .
  • the method of performing etching using an RIE device of a type that applies a high-frequency voltage to both the upper electrode and the lower electrode has been described.
  • the magnetron: RIE device The present invention may be applied to plasma etching equipment, HEP (helicon wave excited plasma) etching equipment, ICP (inductively coupled plasma) etching equipment, TCP (transfer coupled plasma) etching equipment, etc. Will be described with reference to the experimental data.
  • FIG. 2A is a cross-sectional view showing a configuration of an etching sample according to one embodiment of the present invention.
  • a silicon oxide film 22 thermal oxide film
  • a photoresist film 23 having an opening 24 formed on a silicon oxide film 22. It is laminated.
  • the thickness Th of the silicon oxide film 22 is 2 ⁇ m
  • the thickness Tr of the photoresist film 23 is 6 00 nm
  • the diameter ⁇ of the opening 24 was 0.15 m.
  • FIG. 2B is a cross-sectional view showing the bowing shape after the etching.
  • etching ET of the sample of FIG. 2A when etching ET of the sample of FIG. 2A is performed, a contact hole having a bowing shape is formed in the silicon oxide film 22.
  • the bowing ratio which represents the degree of bowing, is defined by the bowing diameter Gc and the top diameter Tc. This boin ratio is most preferably 1, and the preferred range is 0.95 to 1.05 (within ⁇ 5%).
  • the bore diameter Gc is the diameter of the most swelled portion in the middle of the contact hole 25, and the top diameter Tc is the diameter of the uppermost part of the contact hole 25.
  • the bottom diameter Bc is the diameter of the bottom of the contact hole 25.
  • the bottom diameter ratio defined by the bottom diameter Bc / top diameter Tc is most preferably 1. However, in the case of a small hole with a small diameter, the bottom diameter ratio is small. Generally, when the top diameter is about 0.15 m and the hole depth is 2 to 3 m, overetching is performed by 30%, and the bottom diameter ratio is about 70%.
  • the resist mask selection ratio in the present embodiment is a value obtained by dividing the etching rate of the silicon oxide film 22 by the etching rate of the flat resist film 23.
  • the resist mask selection ratio is preferably as large as possible, and is preferably 5.0 or more.
  • the etching according to the conventional example was performed.
  • the C 5 F 8 / A r / 0 2 gas mixture as etching conditions in the conventional example had use in flow rate 1 5/380/1 9 sc cm.
  • the RF power of the upper electrode 2 is set to 2 1550 W power, 2.00 Pa (15 mTorr) pressure, 2000 Pa (15 Torr) He pressure on the back side of wafer W, 3330 Pa (25 Torr) edge ), Top temperature 60.
  • the wall temperature was set at 50 ° C and the bottom temperature was set at 20 ° C.
  • the etching time was set to 30% under-etching when determining the etching selectivity and resist selectivity, and was set to 4 minutes and 48 seconds corresponding to 30% over-etching when evaluating the cross-sectional shape.
  • the distance between the electrodes is 25 mm.
  • the etching rate is 560, 558, and 504 nm / min
  • the resist mask selection ratio on the facet surface is 4.9, 5.4, 5.0
  • boring ratio is 1.02, 1.06, 1.03
  • bottom diameter Be is 107, 108, 95 nm
  • bottom diameter ratio is 71, 3, 72. 0, 63.3%
  • a cross-sectional shape having a bowing shape was obtained.
  • the etching conditions in this example were as follows: the first fluorocarbon-based gas was C 4 F 6, and the second fluorocarbon-based gas was CF 4 .C 4 F 6 ZCF4 / A: rZ02 A mixed gas was used with a flow ratio of 25/10/500/26 sccm.
  • the RF power of the upper electrode 2 was 1800 W
  • the RF power of the lower electrode 3 was 1800 W
  • the pressure was 2.66 Pa (20 mTorr)
  • the He pressure on the back surface of the wafer W was 66 5 P a
  • the etching time was set to 30% under-etching when calculating the etching rate and the resist selectivity, and 4 minutes and 24 seconds corresponding to 30% over-etching when evaluating the cross-sectional shape.
  • the wafer W 588, 606, 622 nm / min Greater, 5.7, 5.3, 5.5 for resist facet selectivity, facet ratio 1.00, 1. 00, 1.00, bottom diameter B e is 99, 93, 109 nm, potom diameter ratio is 66.0%, 62.0%, 72.7%, boring shape A cross-sectional shape without any was obtained.
  • C 4 F 6 / CF 4 / A r / 0 instead of 2-based mixed gas, C 4 a second full Ruorokabon based gas was C 2 F 6 F 6 / C 2 F 6 / A r / Etching using an O 2 -based mixed gas was performed.
  • the etching time of the 30% over-etching when evaluating the cross-sectional shape is 4 minutes and 32 seconds, and the other etching conditions are the same as those in the above-described embodiment.
  • the etching rate at the center, middle, and edge of the wafer W is 608, 636, and 686 nm / min, and the resist mask selectivity on the facet is 6.2, 5. 9, 6.0, B Ingress ratio is 0.98, 0.99, 1.00, Bottom diameter B e is 105, 99, 99 nm, Bottom diameter ratio is 70. 0%, 66.0% and 66.0%.
  • etching is performed using a C 4 F 6 / C 2 F 6 / A r / O 2 mixed gas instead of the C 4 F 6 / CF 4 / A r / O 2 mixed gas.
  • C 4 F 6 / C 2 F 6 / A r / O 2 mixed gas instead of the C 4 F 6 / CF 4 / A r / O 2 mixed gas.
  • C 4 instead of the F 6 ZCF 4 / Ar / 0 2 gas mixture, C 5 F 8 / CF 4 / A r / 0 2 system the first full Ruoroka one carbon-containing gas was set to C 5 F 8 Etching using a mixed gas was performed.
  • the sample is a silicon substrate with a 3 m thick BPSG film formed on it. The diameter of the hole formed by etching is 0.25 m.
  • Etching conditions were as follows: flow rate ratio 25/15/500/25 sccms RF power of upper electrode 2 1750 W, RF power of lower electrode 3 1800 W, pressure 2.66 Pa (20 mTorr), wafer W He pressure on the back side is 665 Pa (5 Torr) at night, 3330 Pa (25 Torr) at edge, top temperature 20 ° C, total temperature 60 ° C, bottom temperature 50 ° C, and etching time. Is the time equivalent to 30% over etching.
  • the average etching rate at the center, middle, and edge of the wafer W was 680.5 nm / min.
  • the resist mask residual film amount on the facet surface was 184, 158, 86 nm (initial film thickness of about 800 nm), and the Boeing ratio was The 1.00, 1.00, 1.00 and bottom diameter ratios were 0.59, 0.59 and 0.59 respectively.
  • etching was performed using a C 5 F 8 / Ar / O 2 -based mixed gas under the same conditions as above except for CF 4 from the above gas system.
  • the average etching rate was 56.1 nm / min, and the remaining amount of the resist mask on the facet surface at the center, middle, and edge of the wafer W was 91, 11, 12, 33 nm (initial film thickness of about 800 nm), Boeing ratios are 1.15, 1.10, 105, and bottom diameter ratios are 0.77, 0.67, 0.62 respectively Was.
  • FIG. 3 is a diagram showing the etching characteristics when the type and flow ratio of the fluorocarbon according to one embodiment of the present invention are all set to a parameter.
  • the processing conditions are the same as in the previous embodiment, and the over-etching is 30%.
  • the over-etching is 30%.
  • the first fluorocarbon-based gas having a large C / F ratio is represented by C 4 F 6
  • the second fluorocarbon-based gas having a small C / F ratio is represented by C x Fy
  • the curves Al and A 2 Is C x F ,, CF 4
  • the total gas flow rate is the same as (3 5 sccm)
  • C 4 F 6 gas flow rate of relative C x F y gas C 4 F 6 gas flow rate / C x F y gas flow amount
  • the resist mask selectivity improves and the etching rate increases. This is thought to be because the increase in the etching species due to the increase in the CZF ratio of the gas as a whole and the deposition of the carbon-based polymer act on the improvement of the etching rate and the resist mask selectivity.
  • C x F y C4 F 6 gas flow rate of relative gas (C 4 F 6 gas flow rate / C x F y gas flow rate) is preferably at 0.5 or more, one or more further favorable preferable.
  • the flow rate of the C 4 F 6 gas is preferably 20 sccm or more.
  • FIG. 4 is a diagram showing a calculation result of a C / F ratio of the entire etching gas according to one embodiment of the present invention.
  • FIG. 4 it can be seen that when the flow ratio of the C 4 F 6 gas to the C x F y gas is 1 or more, the CZF ratio of the entire etching gas becomes 0.5 or more.
  • FIG. 3 the case where the C / F ratio is 0.5 or more is indicated by a circle.
  • two types of fluorocarbon-based gases are mixed to improve the resist mask selectivity.
  • the C / F ratio of the entire etching gas is set to 0.5 or more.
  • C x F v C the number of the (X) is preferably larger.
  • FIGS. 5 to 7 show the etching rate, the selectivity of the resist mask in the flat part, the Boeing ratio, and the bottom when the flow rate (addition amount) of the second fluorocarbon gas having a small C / F ratio was changed.
  • the figure shows the results of examining the change in diameter ratio. 5 For CF 4, 6 in the case of C 2 F 6, 7 is for the C 3 F 8.
  • FIGS. 5 (a), 6 (a) and 7 (a) show the change in the etching rate and the selectivity of the resist mask in the flat part
  • FIGS. 5 (b) and 6 (a) show changes in the bore ratio and the bottom diameter ratio.
  • Etching conditions were as follows: flow rate ratio of C 4 F 6 / C x F y / A r / 0 2 35/0 to 35/70 00 no 36 sccm, RF power of upper electrode 2 220 W
  • the RF power of the lower electrode 3 is 180 W
  • the pressure is 2.66 Pa (20 mTorr)
  • the He pressure on the backside of the wafer W is 66.5 Pa (5 Torr).
  • the top temperature is 60.
  • the wall temperature is 50 ° C
  • the bottom temperature is 10 ° C.
  • the etching time was set to a condition of 30% under-etching when obtaining the etching rate and the resist selectivity, and was set to a time corresponding to 30% over-etching when evaluating the sectional shape.
  • the etching rate is improved, the bowing ratio is improved, and the bottom diameter ratio is also improved.
  • the silicon oxide film 32 and the like are etched through the resist mask 31 to form a contact hole 34 reaching the silicon substrate 33, and the silicon nitride film formed around the gate electrode 35 formed in the lower layer is formed.
  • the film (SiN film) 36 may be exposed.
  • Figure 9 shows the changes in the etching rate, resist mask selectivity (facet portion), and silicon nitride film selectivity (SiN selectivity) of the silicon oxide film (BP SG film) due to the difference in the amount of CF 4 added. This shows the result of the experiment.
  • Etching conditions C 4 F 6 / CF 4 / Ar / 0 2 ratio of flow 1 6/0 ⁇ 10Z800 / 1 6 sc cm, RF power of the upper electrode 2 1530 W, RF power 1 of the lower electrode 3 350 W, Pressure 3.99 Pa (30 mTorr), He pressure on the back side of the wafer W is 665 Pa (5 Torr) at the center, 1330 Pa (10 Torr) at the page, top temperature 40 ° C.
  • the wall temperature is 60 ° C and the bottom temperature is 50 ° C.
  • the etching time is 90 seconds for measuring the etching rate and the resist mask selectivity, and 100% for the silicon nitride film selectivity.
  • the thickness of the silicon oxide film is 1400 nm and the diameter of the contact hole is 400 nm.
  • the addition of CF 4 improves the etching rate and the SiN selectivity.
  • etching conditions are as follows: RF power of upper electrode 2 is 1800 W, power of lower electrode 3 is 2100 W, pressure is 2.66 Pa (20 mTorr) to 3.33 Pa (25 mTorr) The He pressure on the back side of the wafer W was 2000 Pa (15 Torr) at the center, 4660 Pa (35 Torr) at the edge, and the top temperature was 60. Wall temperature 50. Bottom temperature—set at 20-20 ° C (wafer temperature 80-120 ° C). The etching time was 30% underetching when the etching rate of the silicon oxide film and the resist mask selectivity were determined, and the other time was equivalent to 20% overetching.
  • the etching rate, the resist mask selectivity, the bowing ratio, the bottom diameter ratio, and the silicon nitride film selectivity each have a temperature dependence.
  • the silicon nitride film selectivity, the bowing ratio and the bottom diameter ratio are preferably higher at the wafer temperature. In other words, they are in a trade-off relationship.
  • the wafer temperature exceeds 140 ° C (bottom temperature of 40 ° C)
  • the resist is softened and deteriorated, and the shape as a mask cannot be maintained. Therefore, the wafer temperature is preferably set to 80 to 120 ° C.
  • the present invention by performing etching by mixing two or more types of fluorocarbon-based gases, it is possible to suppress the occurrence of bowing, and at the same time, the etching rate and the resist mask selectivity. Can be improved. Further, when the silicon nitride film is exposed, the selectivity of the silicon nitride film can be improved.
  • the method for etching an insulating film according to the present invention can be used in a semiconductor manufacturing industry for manufacturing semiconductor devices. Therefore, it has industrial applicability.

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Abstract

L'invention concerne un gaz mixte contenant au moins un premier gaz fluorocarbonique, dont C ≥ 4 et un rapport C/F d'au moins 0,625, un second gaz fluorocarbonique dont F ≥ 4 et un rapport C/F de plus de 0,5, de l'argon. Un gaz O2 est utilisé comme gaz de gravure pour graver un film isolant composé d'une pellicule d'oxyde de silicium, etc. C'est pourquoi, même si une fenêtre de contact à grand allongement est formée, on peut améliorer une vitesse de gravure et un rapport de sélection de masque de réserve et éviter que la fenêtre de contact ne soit formée de manière cintrée.
PCT/JP2001/010932 2000-12-21 2001-12-13 Procede de gravage pour film isolant WO2002050885A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020037008446A KR100782632B1 (ko) 2000-12-21 2001-12-13 절연막의 에칭 방법
JP2002551894A JP4008352B2 (ja) 2000-12-21 2001-12-13 絶縁膜のエッチング方法
AU2002222631A AU2002222631A1 (en) 2000-12-21 2001-12-13 Etching method for insulating film
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005129920A (ja) * 2003-10-03 2005-05-19 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2006128587A (ja) * 2004-10-29 2006-05-18 Hynix Semiconductor Inc 半導体素子の素子分離膜形成方法
JP2007242753A (ja) * 2006-03-07 2007-09-20 Tokyo Electron Ltd プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体
CN100359644C (zh) * 2002-07-17 2008-01-02 日本瑞翁株式会社 干式蚀刻方法、干式蚀刻气体及全氟-2-戊炔的制备方法
JP2008193015A (ja) * 2007-02-08 2008-08-21 Tokyo Electron Ltd プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体
JP2009206444A (ja) * 2008-02-29 2009-09-10 Nippon Zeon Co Ltd プラズマエッチング方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4723871B2 (ja) * 2004-06-23 2011-07-13 株式会社日立ハイテクノロジーズ ドライエッチング装置
US7794616B2 (en) * 2004-08-09 2010-09-14 Tokyo Electron Limited Etching gas, etching method and etching gas evaluation method
US7416676B2 (en) * 2005-02-16 2008-08-26 Tokyo Electron Limited Plasma etching method and apparatus, control program for performing the etching method, and storage medium storing the control program
US7517804B2 (en) * 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
JP4450245B2 (ja) * 2007-06-07 2010-04-14 株式会社デンソー 半導体装置の製造方法
US20110265883A1 (en) * 2010-04-30 2011-11-03 Applied Materials, Inc. Methods and apparatus for reducing flow splitting errors using orifice ratio conductance control
CN103578973B (zh) * 2012-07-29 2017-09-05 中国科学院微电子研究所 氮化硅高深宽比孔的循环刻蚀方法
CN103903978B (zh) * 2012-12-27 2016-12-28 南亚科技股份有限公司 蚀刻方法
CN106297831B (zh) * 2015-05-21 2020-04-21 新科实业有限公司 在衬底形成图案的方法
JP6836959B2 (ja) * 2017-05-16 2021-03-03 東京エレクトロン株式会社 プラズマ処理装置、処理システム、及び、多孔質膜をエッチングする方法
US10276439B2 (en) 2017-06-02 2019-04-30 International Business Machines Corporation Rapid oxide etch for manufacturing through dielectric via structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04346428A (ja) * 1991-05-24 1992-12-02 Sony Corp ドライエッチング方法
US5338399A (en) * 1991-02-12 1994-08-16 Sony Corporation Dry etching method
JP2000173993A (ja) * 1998-12-02 2000-06-23 Tokyo Electron Ltd プラズマ処理装置およびエッチング方法
JP2002016050A (ja) * 2000-04-28 2002-01-18 Daikin Ind Ltd ドライエッチングガスおよびドライエッチング方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3116569B2 (ja) * 1992-06-29 2000-12-11 ソニー株式会社 ドライエッチング方法
KR100246029B1 (ko) * 1997-10-20 2000-03-02 구자홍 간헐 영상 녹화재생장치
TW394989B (en) * 1997-10-29 2000-06-21 Matsushita Electronics Corp Semiconductor device manufacturing and reaction room environment control method for dry etching device
JP3003657B2 (ja) * 1997-12-24 2000-01-31 日本電気株式会社 半導体装置の製造方法
US6159862A (en) * 1997-12-27 2000-12-12 Tokyo Electron Ltd. Semiconductor processing method and system using C5 F8
JPH11330046A (ja) * 1998-05-08 1999-11-30 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
TW511335B (en) * 1998-06-09 2002-11-21 Mitsubishi Electric Corp Integrated circuit
US6297163B1 (en) * 1998-09-30 2001-10-02 Lam Research Corporation Method of plasma etching dielectric materials
JP4776747B2 (ja) * 1998-11-12 2011-09-21 株式会社ハイニックスセミコンダクター 半導体素子のコンタクト形成方法
US6417090B1 (en) * 1999-01-04 2002-07-09 Advanced Micro Devices, Inc. Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer
JP2000252259A (ja) * 1999-02-25 2000-09-14 Sony Corp ドライエッチング方法及び半導体装置の製造方法
US6184107B1 (en) * 1999-03-17 2001-02-06 International Business Machines Corp. Capacitor trench-top dielectric for self-aligned device isolation
US6849193B2 (en) * 1999-03-25 2005-02-01 Hoiman Hung Highly selective process for etching oxide over nitride using hexafluorobutadiene
JP4578651B2 (ja) * 1999-09-13 2010-11-10 東京エレクトロン株式会社 プラズマ処理方法およびプラズマ処理装置、プラズマエッチング方法
JP2001135630A (ja) * 1999-11-10 2001-05-18 Matsushita Electronics Industry Corp 半導体装置の製造方法
US6326307B1 (en) * 1999-11-15 2001-12-04 Appllied Materials, Inc. Plasma pretreatment of photoresist in an oxide etch process
JP3400770B2 (ja) * 1999-11-16 2003-04-28 松下電器産業株式会社 エッチング方法、半導体装置及びその製造方法
US6337244B1 (en) * 2000-03-01 2002-01-08 Micron Technology, Inc. Method of forming flash memory
US6451703B1 (en) * 2000-03-10 2002-09-17 Applied Materials, Inc. Magnetically enhanced plasma etch process using a heavy fluorocarbon etching gas
US6337285B1 (en) * 2000-03-21 2002-01-08 Micron Technology, Inc. Self-aligned contact (SAC) etch with dual-chemistry process
KR100362834B1 (ko) * 2000-05-02 2002-11-29 삼성전자 주식회사 반도체 장치의 산화막 형성 방법 및 이에 의하여 제조된 반도체 장치
EP1281193A2 (fr) * 2000-05-12 2003-02-05 Tokyo Electron Limited Procede de gravure sac a selectivite elevee
US6362109B1 (en) * 2000-06-02 2002-03-26 Applied Materials, Inc. Oxide/nitride etching having high selectivity to photoresist
KR100363710B1 (ko) * 2000-08-23 2002-12-05 삼성전자 주식회사 셀프-얼라인 콘택 구조를 갖는 반도체 장치 및 그 제조방법
US6716302B2 (en) * 2000-11-01 2004-04-06 Applied Materials Inc. Dielectric etch chamber with expanded process window
US20040035825A1 (en) * 2000-11-08 2004-02-26 Shingo Nakamura Dry etching gas and method for dry etching
JP4213871B2 (ja) * 2001-02-01 2009-01-21 株式会社日立製作所 半導体装置の製造方法
TW483111B (en) * 2001-06-08 2002-04-11 Promos Technologies Inc Method for forming contact of memory device
US6674241B2 (en) * 2001-07-24 2004-01-06 Tokyo Electron Limited Plasma processing apparatus and method of controlling chemistry
US6518164B1 (en) * 2001-11-30 2003-02-11 United Microelectronics Corp. Etching process for forming the trench with high aspect ratio

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5338399A (en) * 1991-02-12 1994-08-16 Sony Corporation Dry etching method
JPH04346428A (ja) * 1991-05-24 1992-12-02 Sony Corp ドライエッチング方法
JP2000173993A (ja) * 1998-12-02 2000-06-23 Tokyo Electron Ltd プラズマ処理装置およびエッチング方法
JP2002016050A (ja) * 2000-04-28 2002-01-18 Daikin Ind Ltd ドライエッチングガスおよびドライエッチング方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100359644C (zh) * 2002-07-17 2008-01-02 日本瑞翁株式会社 干式蚀刻方法、干式蚀刻气体及全氟-2-戊炔的制备方法
JP2005129920A (ja) * 2003-10-03 2005-05-19 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2006128587A (ja) * 2004-10-29 2006-05-18 Hynix Semiconductor Inc 半導体素子の素子分離膜形成方法
JP2007242753A (ja) * 2006-03-07 2007-09-20 Tokyo Electron Ltd プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体
JP2008193015A (ja) * 2007-02-08 2008-08-21 Tokyo Electron Ltd プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体
JP2009206444A (ja) * 2008-02-29 2009-09-10 Nippon Zeon Co Ltd プラズマエッチング方法

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CN1483219A (zh) 2004-03-17
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JPWO2002050885A1 (ja) 2004-04-22
CN1249788C (zh) 2006-04-05
KR100782632B1 (ko) 2007-12-06
TW521335B (en) 2003-02-21
JP4008352B2 (ja) 2007-11-14

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