JP2006128587A - 半導体素子の素子分離膜形成方法 - Google Patents
半導体素子の素子分離膜形成方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 85
- 238000002955 isolation Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
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- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 7
- 239000000126 substance Substances 0.000 description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 5
- 229910052731 fluorine Inorganic materials 0.000 description 5
- 239000011737 fluorine Substances 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000001311 chemical methods and process Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
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- H01L21/31608—Deposition of SiO2
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Abstract
【解決手段】 半導体基板にトレンチを形成する段階と、前記形成されたトレンチに第1HDP酸化膜を形成する段階と、前記第1HDP酸化膜が形成された結果物の全面にC2F6ガス及びO2ガスの混合ガスを用いてエッチバック工程を行い、バーティカルな側壁を有する前記第1HDP酸化膜を形成する段階と、前記エッチバック工程の完了した結果物の全面に第2HDP酸化膜を形成する段階とを含む構成としたことを特徴とする。
【選択図】 図2
Description
22…パッド窒化膜
24…パッド酸化膜
26…側壁酸化膜
28a…第1HDP酸化膜
28b…第2HDP酸化膜
Claims (7)
- 半導体基板にトレンチを形成する段階と、
前記形成されたトレンチに第1HDP酸化膜を形成する段階と、
前記第1HDP酸化膜が形成された結果物の全面にC2F6ガス及びO2ガスの混合ガスを用いてエッチバック工程を行い、バーティカルな側壁を有する前記第1HDP酸化膜を形成する段階と、
前記エッチバック工程の完了した結果物の全面に第2HDP酸化膜を形成する段階と、 を含むことを特徴とする半導体素子の素子分離膜形成方法。 - C2F6ガス及びO2ガスの混合ガスを用いて行われる前記エッチバック工程は、50sccm以上、且つ200sccm以下のC2F6ガス、200sccm以上、且つ500sccm以下のO2ガス、500W以上、且つ1000W以下のHFパワー、3000W以上、且つ4000W以下のLFパワーを有する工程条件で行われることを特徴とする請求項1記載の半導体素子の素子分離膜形成方法。
- 前記トレンチの形成後、前記トレンチの側壁に酸化工程によって側壁酸化膜を形成する段階をさらに含むことを特徴とする請求項1記載の半導体素子の素子分離膜形成方法。
- 前記第1HDP酸化膜は、10sccm以上、且つ100sccm以下程度のSiH4ガス、10sccm以上、且つ100sccm以下程度のO2ガス、100sccm以上、且つ1000sccm以下程度のHeガス、50sccm以上、且つ1000sccm以下程度のH2ガス、1000W以上、且つ10000W以下程度のLFパワー及び500W以上、且つ5000W以下程度のHFパワーを有する工程条件で形成されることを特徴とする請求項1記載の半導体素子の素子分離膜形成方法。
- 前記第2HDP酸化膜は、前記第1HDP酸化膜の工程条件と同一の工程条件で形成されることを特徴とする請求項1または請求項4記載の半導体素子の素子分離膜形成方法。
- 前記第2HDP酸化膜の形成後、前記半導体基板が露出するまで平坦化工程を行って前記トレンチの内部にのみ前記第1HDP酸化膜及び第2HDP酸化膜が埋め込まれるようにして、素子分離膜の形成を完了する段階をさらに含むことを特徴とする請求項1記載の半導体素子の素子分離膜形成方法。
- 半導体基板にトレンチを形成する段階と、
前記トレンチの側壁に側壁酸化膜を形成する段階と、
前記側壁酸化膜が備えられたトレンチに第1HDP酸化膜を形成する段階と、
前記第1HDP酸化膜が形成された結果物の全面にC2F6ガス及びO2ガスの混合ガスを用いてエッチバック工程を行い、バーティカルな側壁を有する第1HDP酸化膜を形成する段階と、
前記エッチバック工程の完了した結果物の全面に第2HDP酸化膜を形成する段階と、
前記形成された結果物に前記半導体基板が露出するまで平坦化工程を行って前記トレンチの内部にのみ前記第1HDP酸化膜及び第2HDP酸化膜が埋め込まれるようにして、素子分離膜の形成を完了する段階と、
を含むことを特徴とする半導体素子の素子分離膜形成方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2004-087145 | 2004-10-29 | ||
KR1020040087145A KR100650835B1 (ko) | 2004-10-29 | 2004-10-29 | 반도체 소자의 소자분리막 형성방법 |
Publications (2)
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JP2006128587A true JP2006128587A (ja) | 2006-05-18 |
JP5030126B2 JP5030126B2 (ja) | 2012-09-19 |
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JP2004370438A Expired - Fee Related JP5030126B2 (ja) | 2004-10-29 | 2004-12-22 | 半導体素子の素子分離膜形成方法 |
Country Status (6)
Country | Link |
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US (1) | US7183173B2 (ja) |
JP (1) | JP5030126B2 (ja) |
KR (1) | KR100650835B1 (ja) |
CN (1) | CN100372096C (ja) |
DE (1) | DE102004060667B4 (ja) |
TW (1) | TWI244698B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009111351A (ja) * | 2007-09-07 | 2009-05-21 | Applied Materials Inc | Hdp−cvd堆積/エッチング/堆積プロセスの不純物コントロール |
JP2009164384A (ja) * | 2008-01-08 | 2009-07-23 | Renesas Technology Corp | 半導体装置の製造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100912988B1 (ko) * | 2006-09-29 | 2009-08-20 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR100919803B1 (ko) * | 2006-12-28 | 2009-10-01 | 주식회사 하이닉스반도체 | 반도체소자의 트렌치 소자분리막 형성방법 |
CN101289284B (zh) * | 2007-04-20 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | 有效控制含氟硅玻璃层间介质层形成中产生的气泡的方法 |
KR100899393B1 (ko) * | 2007-09-07 | 2009-05-27 | 주식회사 하이닉스반도체 | 반도체 소자의 소자분리막 형성방법 |
KR101002493B1 (ko) * | 2007-12-28 | 2010-12-17 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 소자 분리막 형성 방법 |
KR101145386B1 (ko) * | 2010-11-16 | 2012-05-15 | 에스케이하이닉스 주식회사 | 반도체 장치의 매립게이트 제조방법 |
CN104425350B (zh) * | 2013-09-10 | 2017-09-01 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法 |
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2004
- 2004-10-29 KR KR1020040087145A patent/KR100650835B1/ko not_active IP Right Cessation
- 2004-12-13 TW TW093138520A patent/TWI244698B/zh not_active IP Right Cessation
- 2004-12-15 DE DE102004060667A patent/DE102004060667B4/de not_active Expired - Fee Related
- 2004-12-22 JP JP2004370438A patent/JP5030126B2/ja not_active Expired - Fee Related
- 2004-12-22 US US11/020,330 patent/US7183173B2/en not_active Expired - Fee Related
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2005
- 2005-04-05 CN CNB2005100628825A patent/CN100372096C/zh not_active Expired - Fee Related
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JPS62152128U (ja) * | 1986-03-17 | 1987-09-26 | ||
JPH04170026A (ja) * | 1990-11-02 | 1992-06-17 | Sony Corp | ドライエッチング方法 |
JPH04309221A (ja) * | 1991-04-08 | 1992-10-30 | Nec Corp | 半導体装置の製造方法 |
JPH07221110A (ja) * | 1994-01-31 | 1995-08-18 | Toshiba Corp | 半導体装置の配線構造とその製造方法 |
JPH09134895A (ja) * | 1995-11-10 | 1997-05-20 | Nec Corp | 半導体装置の製造方法 |
JP2001332510A (ja) * | 2000-05-25 | 2001-11-30 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2002025941A (ja) * | 2000-07-11 | 2002-01-25 | Fujitsu Ltd | 半導体装置の製造方法 |
WO2002050885A1 (fr) * | 2000-12-21 | 2002-06-27 | Tokyo Electron Limited | Procede de gravage pour film isolant |
JP2003031649A (ja) * | 2001-07-13 | 2003-01-31 | Toshiba Corp | 半導体装置の製造方法 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009111351A (ja) * | 2007-09-07 | 2009-05-21 | Applied Materials Inc | Hdp−cvd堆積/エッチング/堆積プロセスの不純物コントロール |
JP2009164384A (ja) * | 2008-01-08 | 2009-07-23 | Renesas Technology Corp | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
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JP5030126B2 (ja) | 2012-09-19 |
KR20060038022A (ko) | 2006-05-03 |
CN100372096C (zh) | 2008-02-27 |
DE102004060667B4 (de) | 2010-11-25 |
US20060094201A1 (en) | 2006-05-04 |
TWI244698B (en) | 2005-12-01 |
TW200614371A (en) | 2006-05-01 |
CN1767166A (zh) | 2006-05-03 |
KR100650835B1 (ko) | 2006-11-27 |
US7183173B2 (en) | 2007-02-27 |
DE102004060667A1 (de) | 2006-05-04 |
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