JP2006041503A - フラッシュメモリ素子の製造方法 - Google Patents
フラッシュメモリ素子の製造方法 Download PDFInfo
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- JP2006041503A JP2006041503A JP2005186726A JP2005186726A JP2006041503A JP 2006041503 A JP2006041503 A JP 2006041503A JP 2005186726 A JP2005186726 A JP 2005186726A JP 2005186726 A JP2005186726 A JP 2005186726A JP 2006041503 A JP2006041503 A JP 2006041503A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 74
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 53
- 229920005591 polysilicon Polymers 0.000 claims abstract description 53
- 150000004767 nitrides Chemical class 0.000 claims abstract description 24
- 238000002955 isolation Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 30
- 238000004140 cleaning Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000000137 annealing Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000009279 wet oxidation reaction Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 3
- 229910017855 NH 4 F Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
【解決手段】セル領域にはパッド酸化膜が形成され、低電圧領域には低電圧ゲート酸化膜が形成され、高電圧領域には高電圧ゲート酸化膜が形成された半導体基板を提供する段階と、前記低電圧領域及び前記高電圧領域に第1ポリシリコン膜を形成する段階と、前記第1ポリシリコン膜を含む全体構造の上部にパッド窒化膜を蒸着する段階と、前記セル領域に形成された前記パッド窒化膜、前記パッド酸化膜及び前記半導体基板の一部をパターニングして第1トレンチを形成する段階と、前記低電圧領域と前記高電圧領域に形成された前記パッド窒化膜、前記第1ポリシリコン膜、前記低電圧ゲート酸化膜、前記高電圧ゲート酸化膜及び前記半導体基板の一部をパターニングして第2及び第3トレンチを形成する段階とを含む。
【選択図】図4
Description
11a パッド酸化膜
11b 低電圧ゲート酸化膜
11c 高電圧ゲート酸化膜
12 第1ポリシリコン膜
13 パッド窒化膜
14 素子分離膜
15 トンネル絶縁膜
16 第2ポリシリコン膜
16a フローティングゲート
17 誘電体膜
18 第3ポリシリコン膜
18a コントロールゲート
19 第4ポリシリコン膜
Claims (6)
- (a)セル領域にはパッド酸化膜が形成され、低電圧領域には低電圧ゲート酸化膜が形成され、高電圧領域には高電圧ゲート酸化膜が形成された半導体基板を提供する段階と、
(b)前記低電圧領域及び前記高電圧領域に第1ポリシリコン膜を形成する段階と、
(c)前記第1ポリシリコン膜を含む全体構造の上部にパッド窒化膜を蒸着する段階と、
(d)前記セル領域に形成された前記パッド窒化膜、前記パッド酸化膜及び前記半導体基板の一部をパターニングして第1トレンチを形成する段階と、
(e)前記低電圧領域と前記高電圧領域に形成された前記パッド窒化膜、前記第1ポリシリコン膜、前記低電圧ゲート酸化膜、前記高電圧ゲート酸化膜及び前記半導体基板の一部をパターニングして第2及び第3トレンチを形成する段階と、
(f)前記第1〜第3トレンチが埋め立てられるように素子分離膜を形成する段階と、
(g)前記パッド窒化膜を除去する段階と、
(h)前記素子分離膜の形成された全体構造の上部にトンネル絶縁膜を形成する段階と、
(i)前記トンネル絶縁膜上に第2ポリシリコン膜を蒸着した後、パターニングしてフローティングゲートを形成する段階とを含むことを特徴とするフラッシュメモリ素子の製造方法。 - 前記第1ポリシリコン膜は300Å〜500Åの厚さに形成されることを特徴とする請求項1記載のフラッシュメモリ素子の製造方法。
- 前記トンネル絶縁膜を形成する前に前処理洗浄工程を行い、前記セル領域に残留する前記パッド酸化膜を除去する段階をさらに含むことを特徴とする請求項1記載のフラッシュメモリ素子の製造方法。
- 前記(i)段階で行われる前記第2ポリシリコン膜パターニングの際に、前記低電圧領域及び前記高電圧領域に蒸着された前記誘電体膜がエッチング停止層として機能することを特徴とする請求項1記載のフラッシュメモリ素子の製造方法。
- 前記(b)段階は、
(b−1)前記パッド酸化膜、前記低電圧ゲート酸化膜及び前記高電圧ゲート酸化膜を含む全体構造の上部に前記第1ポリシリコン膜を蒸着する段階と、
(b−2)前記セル領域に形成された前記第1ポリシリコン膜を除去して前記低電圧領域及び前記高電圧領域に前記第1ポリシリコン膜を残留させる段階とを含むことを特徴とする請求項1記載のフラッシュメモリ素子の製造方法。 - 前記(i)段階後、
(j)前記フローティングゲートを含む全体構造の上部に誘電体膜を形成する段階と、
(k)前記誘電体膜上に第3ポリシリコン膜を蒸着した後、パターニングして前記フローティングゲートを覆うコントロールゲートを形成する段階をさらに含むことを特徴とする請求項1記載のフラッシュメモリ素子の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040057617A KR100562153B1 (ko) | 2004-07-23 | 2004-07-23 | 플래시 메모리 소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006041503A true JP2006041503A (ja) | 2006-02-09 |
JP4633554B2 JP4633554B2 (ja) | 2011-02-16 |
Family
ID=35657766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005186726A Expired - Fee Related JP4633554B2 (ja) | 2004-07-23 | 2005-06-27 | フラッシュメモリ素子の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7052960B2 (ja) |
JP (1) | JP4633554B2 (ja) |
KR (1) | KR100562153B1 (ja) |
CN (1) | CN100365802C (ja) |
DE (1) | DE102005021190B4 (ja) |
TW (1) | TWI264778B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101563776B1 (ko) | 2013-01-25 | 2015-10-29 | 매그나칩 반도체 유한회사 | 반도체 장치 |
KR20180025134A (ko) * | 2016-08-30 | 2018-03-08 | 윈본드 일렉트로닉스 코포레이션 | 메모리 디바이스의 제조 방법 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100755411B1 (ko) * | 2006-09-28 | 2007-09-04 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
KR100757335B1 (ko) * | 2006-10-18 | 2007-09-11 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 이를 제조하는 방법 |
KR100891423B1 (ko) * | 2006-12-27 | 2009-04-02 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조방법 |
US7439134B1 (en) * | 2007-04-20 | 2008-10-21 | Freescale Semiconductor, Inc. | Method for process integration of non-volatile memory cell transistors with transistors of another type |
JP4886801B2 (ja) * | 2009-03-02 | 2012-02-29 | 株式会社東芝 | 半導体装置の製造方法 |
KR20110117326A (ko) * | 2010-04-21 | 2011-10-27 | 매그나칩 반도체 유한회사 | 반도체 장치 및 그 제조방법 |
US8652907B2 (en) * | 2011-03-24 | 2014-02-18 | Spansion Llc | Integrating transistors with different poly-silicon heights on the same die |
CN104103681A (zh) * | 2014-07-02 | 2014-10-15 | 武汉新芯集成电路制造有限公司 | 浮栅结构及其制造方法 |
TWI685061B (zh) | 2016-05-04 | 2020-02-11 | 聯華電子股份有限公司 | 半導體元件及其製作方法 |
US10553583B2 (en) | 2017-08-28 | 2020-02-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Boundary region for high-k-metal-gate(HKMG) integration technology |
US10522557B2 (en) | 2017-10-30 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Surface topography by forming spacer-like components |
CN117790290A (zh) * | 2024-02-23 | 2024-03-29 | 合肥晶合集成电路股份有限公司 | 半导体结构及其制作方法 |
Citations (3)
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JPH11261040A (ja) * | 1998-01-08 | 1999-09-24 | Internatl Business Mach Corp <Ibm> | フロ―ティング・ゲ―ト領域形成方法 |
JP2003046062A (ja) * | 2001-07-30 | 2003-02-14 | Toshiba Corp | 半導体メモリ装置の製造方法 |
JP2004104092A (ja) * | 2002-07-12 | 2004-04-02 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
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JP2000183053A (ja) * | 1998-12-14 | 2000-06-30 | Sony Corp | 半導体装置の製造方法 |
US6281050B1 (en) * | 1999-03-15 | 2001-08-28 | Kabushiki Kaisha Toshiba | Manufacturing method of a semiconductor device and a nonvolatile semiconductor storage device |
US6130168A (en) * | 1999-07-08 | 2000-10-10 | Taiwan Semiconductor Manufacturing Company | Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process |
JP2002064157A (ja) * | 2000-06-09 | 2002-02-28 | Toshiba Corp | 半導体メモリ集積回路及びその製造方法 |
KR100406177B1 (ko) * | 2001-11-23 | 2003-11-17 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 제조 방법 |
KR100426483B1 (ko) * | 2001-12-22 | 2004-04-14 | 주식회사 하이닉스반도체 | 플래쉬 메모리 셀의 제조 방법 |
JP2004095886A (ja) * | 2002-08-30 | 2004-03-25 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2006504261A (ja) * | 2002-10-22 | 2006-02-02 | テラ セミコンダクター、インク. | フラッシュeeprom単位セル及びこれを含むメモリーアレイ構造体 |
KR100612416B1 (ko) * | 2004-05-20 | 2006-08-16 | 삼성전자주식회사 | 다중 게이트 절연막을 가지는 반도체 소자 및 그 제조 방법 |
-
2004
- 2004-07-23 KR KR1020040057617A patent/KR100562153B1/ko not_active IP Right Cessation
-
2005
- 2005-05-03 DE DE102005021190A patent/DE102005021190B4/de not_active Expired - Fee Related
- 2005-05-09 TW TW094114909A patent/TWI264778B/zh not_active IP Right Cessation
- 2005-05-11 US US11/126,333 patent/US7052960B2/en not_active Expired - Fee Related
- 2005-06-22 CN CNB2005100786424A patent/CN100365802C/zh not_active Expired - Fee Related
- 2005-06-27 JP JP2005186726A patent/JP4633554B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH11261040A (ja) * | 1998-01-08 | 1999-09-24 | Internatl Business Mach Corp <Ibm> | フロ―ティング・ゲ―ト領域形成方法 |
JP2003046062A (ja) * | 2001-07-30 | 2003-02-14 | Toshiba Corp | 半導体メモリ装置の製造方法 |
JP2004104092A (ja) * | 2002-07-12 | 2004-04-02 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101563776B1 (ko) | 2013-01-25 | 2015-10-29 | 매그나칩 반도체 유한회사 | 반도체 장치 |
KR20180025134A (ko) * | 2016-08-30 | 2018-03-08 | 윈본드 일렉트로닉스 코포레이션 | 메모리 디바이스의 제조 방법 |
KR101989921B1 (ko) | 2016-08-30 | 2019-06-17 | 윈본드 일렉트로닉스 코포레이션 | 메모리 디바이스의 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
TWI264778B (en) | 2006-10-21 |
US20060019446A1 (en) | 2006-01-26 |
US7052960B2 (en) | 2006-05-30 |
DE102005021190A1 (de) | 2006-03-16 |
CN1725470A (zh) | 2006-01-25 |
CN100365802C (zh) | 2008-01-30 |
JP4633554B2 (ja) | 2011-02-16 |
DE102005021190B4 (de) | 2010-01-28 |
KR20060007982A (ko) | 2006-01-26 |
KR100562153B1 (ko) | 2006-03-17 |
TW200608493A (en) | 2006-03-01 |
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