TWI685061B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI685061B
TWI685061B TW105113789A TW105113789A TWI685061B TW I685061 B TWI685061 B TW I685061B TW 105113789 A TW105113789 A TW 105113789A TW 105113789 A TW105113789 A TW 105113789A TW I685061 B TWI685061 B TW I685061B
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substrate
region
item
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shallow trench
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張凱焜
蕭世楹
熊昌鉑
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聯華電子股份有限公司
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Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底，且該基底具有一第一區域以及一第二區域。然後形成一淺溝隔離於基底內並分隔第一區域及第二區域，形成一圖案化硬遮罩於第一區域及部分淺溝隔離上，再通入一氣體繞過圖案化硬遮罩並藉此改變第一區域之基底之一邊緣。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種改變基底邊緣輪廓的方法。
在半導體製程中，為了使晶片上各個電子元件之間擁有良好的隔離，以避免元件相互干擾而產生短路現象，一般皆採用區域氧化法(localized oxidation isolation,LOCOS)或是淺溝隔離方法來進行隔離與保護。然由於LOCOS製程中產生的場氧化層(field oxide)所佔據晶片的面積太大，且生成過程會伴隨鳥嘴(bird's beak)現象的發生，因此目前線寬在0.25微米(μm)以下的半導體製程幾乎都採用淺溝隔離方法。
淺溝隔離方法是在晶片表面的各元件間製作一淺溝並填入絕緣物質以產生電性隔離的效果。現今的淺溝隔離製程，在填入絕緣物質於淺溝 中之前，會先在淺溝的側壁形成一氧化物，以進一步將絕緣物質與凹槽表面隔離。然而，當尺寸日漸微縮，反相窄通道效應(inverse narrow width effect,INWE)更趨顯著之外又容易造成漏電流現象增加，嚴重影響半導體裝置的效能。因此，本產業亟需一種可改善上述問題的方法，以解決尺寸日漸微縮下所遭遇的瓶頸。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，且該基底具有一第一區域以及一第二區域。然後形成一淺溝隔離於基底內並分隔第一區域及第二區域，形成一圖案化硬遮罩於第一區域及部分淺溝隔離上，再通入一氣體繞過圖案化硬遮罩並藉此改變第一區域之基底之一邊緣。
本發明另一實施例揭露一種半導體元件，其包含：一基底；一閘極結構設於基底上，以及一淺溝隔離設於基底內並圍繞閘極結構，其中接觸淺溝隔離之基底之一邊緣包含一弧形輪廓。
12‧‧‧基底
14‧‧‧第一區域
16‧‧‧第二區域
18‧‧‧淺溝隔離
20‧‧‧襯墊層
22‧‧‧圖案化硬遮罩
24‧‧‧開口
26‧‧‧閘極介電層
28‧‧‧弧形輪廓
30‧‧‧井區
32‧‧‧閘極介電層
34‧‧‧閘極結構
36‧‧‧摻雜區
38‧‧‧長度
40‧‧‧寬度
42‧‧‧區域
44‧‧‧第一邊
46‧‧‧第二邊
d‧‧‧距離
第1圖至第5圖為本發明較佳實施例製作一半導體元件的方法示意圖。
第6圖為本發明一實施例之半導體元件結構示意圖。
第7圖為本發明一實施例之半導體元件結構示意圖。
第8圖為本發明一實施例之半導體元件結構示意圖。
請參照第1圖至第5圖，第1圖至第5圖為本發明較佳實施例製作一半導體元件的方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板。基底12上定義有一第一區域14與一第二區域16，然後形成一由二氧化矽所構成的淺溝隔離(shallow trench isolation,STI)18於基底12中並分隔第一區14域與第二區域16。在本實施例中，第一區域14較佳於後續製程中用來製作一中電壓半導體元件因此又可簡稱為中電壓區，第二區域16則較佳用來製作高壓半導體元件因此又可簡稱為高壓區。
然後依序形成一襯墊層20以及一圖案化硬遮罩22於第一區域14的基底12與淺溝隔離18上，其中襯墊層20較佳僅設於第一區域14的基底12表面，圖案化硬遮罩22則同時設於基底12與淺溝隔離18表面，且圖案化硬遮罩22具有開口24暴露出部分淺溝隔離18。在本實施例中，襯墊層20較佳由二氧化矽所構成，圖案化硬遮罩22較佳由氮化矽所構成，但不侷限於此，又可依據製程需求選擇任何不同的介電材料作為襯墊層20與圖案化硬遮罩22，此實施例也屬本發明所涵蓋的範圍。
然後如第1圖至第2圖所示，同時對第一區域14與第二區域16通入一氣體或進行一處理例如氧化製程，以於第二區域16的基底12表 面形成一閘極介電層26並同時改變第一區域14中與淺溝隔離18所接觸之基底12的邊緣。更具體而言，所通入的氣體較佳為一含氧氣體或氧氣，且由於第二區域16上並無圖案化硬遮罩22的遮蔽，因此所通入的含氧氣體較佳於第二區域16的基底12表面直接反應而形成一閘極介電層26，其中所形成的閘極介電層26厚度較佳介於300埃至1500埃，例如可用來當作高壓半導體元件的閘極介電層。
第一區域14的基底12上由於圖案化硬遮罩22的設置，因此所通入的含氧氣體較佳繞過圖案化硬遮罩22，例如沿著第1圖中的箭頭方向從圖案化硬遮罩22的開口24進入並經過被開口24暴露出的淺溝隔離18，藉此改變接觸淺溝隔離18的基底12邊緣輪廓或淺溝隔離18自己本身的邊緣輪廓。依據本發明之較佳實施例，原本在通入含氧氣體之前接觸淺溝隔離18或基底12的邊緣較佳呈現具有鈍角的輪廓，但在通入含氧氣體之後，原本為鈍角的基底12邊緣或淺溝隔離18邊緣較佳改變為一弧形輪廓28。從另一角度來看，在基底12邊緣形成弧形輪廓28的同時，淺溝隔離18的兩邊亦同時形成突出部，而形成左右對稱的態樣。
如第3圖所示，接著去除第一區域14上的圖案化硬遮罩22，並進行一離子佈植，以形成一井區30於第一區域14的基底12內。
然後如第4圖所示，先去除第一區域14上的襯墊層20，再進行一氧化製程，以於裸露出的第一區域14基底12表面形成一閘極介電層32，其中閘極介電層32的厚度較佳介於60埃至200埃，例如可用來當作中壓半導體元件的閘極介電層。接著可選擇性於另一低壓元件區(圖 未示)形成另一閘極介電層(圖未示)，並形成一閘極結構34於第一區域14與第二區域16的閘極介電層26、32上，其中閘極結構34較佳由多晶矽所構成，但不侷限於此。
請接著參照第5圖所示，第5圖為接續第4圖第一區14域中形成閘極結構34後之上視圖。如第5圖所示，之後可依據製程需求於閘極結構34兩側利用離子佈植製程形成摻雜區36做為源極/汲極區域，其中源極/汲極區域可依據所製作的元件態樣具有不同導電型式。
請同時參照第4圖與第5圖，第4圖與第5圖另揭露本發明較佳實施例之一種半導體元件結構。如第4圖與第5圖所示，本發明之半導體元件主要包含一基底12，一閘極結構34設於基底12上，一摻雜區36設於閘極結構34兩側，以及一淺溝隔離18設於基底12內並圍繞摻雜區36與閘極結構34，其中接觸淺溝隔離18的基底12邊緣包含一弧形輪廓28。從另一角度來看，設於閘極結構34下方的淺溝隔離18亦具有一突出部，且突出部為左右對稱。
更具體而言，從第5圖的上視圖來看，本實施例的閘極結構34包含一長度38以及一寬度40，且弧形輪廓28較佳設於靠近寬度40的閘極結構34下方且與寬度40平行，即圖中由斜線所標示出之區域42。亦即，第1圖至第2圖所示圖案化硬遮罩22的開口24僅暴露出位於閘極結構34寬度40邊緣之部分的淺溝隔離18。
另外摻雜區36包含一第一邊44平行於閘極結構34之寬度40 以及一第二邊46平行於閘極結構34之長度38，淺溝隔離18較佳環繞摻雜區36之第一邊44與第二邊46，而本實施例中弧形輪廓28的所在區域42則僅設於閘極結構34下方與摻雜區36第一邊44之間，或更細部來看位於閘極結構34下方與切齊摻雜區36第一邊44的閘極結構寬度40之間，但不延伸至摻雜區36正下方與摻雜區36第一邊44之間。
請參照第6圖，第6圖為第5圖之上視圖對應第2圖中圖案化硬遮罩的開口之示意圖。如第6圖所示，若與第2圖中圖案化硬遮罩22的開口24進行比對，開口24邊緣較佳不切齊摻雜區36的第一邊44，且開口24邊緣至摻雜區36邊緣或第一邊44的距離d較佳介於0.005微米至0.5微米，或最佳為0.02微米。
請參照第7圖，第7圖為本發明另一實施例之半導體元件結構示意圖。如第7圖所示，本實施例同樣包含一閘極結構34設於基底12上，一摻雜區36設於閘極結構34兩側，以及一淺溝隔離18設於基底12內並圍繞摻雜區36與閘極結構34，其中接觸淺溝隔離18的基底12邊緣(平行於閘極結構34寬度40方向)包含一弧形輪廓28。亦即，第1圖至第2圖所示圖案化硬遮罩22的有開口24係暴露出位於整個閘極結構34寬度40邊緣之部分的淺溝隔離18。
相較於第5圖中弧形輪廓28僅設置於閘極結構34下方與切齊摻雜區36第一邊44的閘極結構寬度40之間，本實施例中弧形輪廓28所設置的區域42除了設於閘極結構34下方與切齊摻雜區36第一邊44的閘極結構寬度40之間外，又延伸至摻雜區36下方與摻雜區36第一邊44之 間。
請參照第8圖，第8圖為本發明另一實施例之半導體元件結構示意圖。如第8圖所示，本實施例同樣包含一閘極結構34設於基底12上，一摻雜區36設於閘極結構34兩側，以及一淺溝隔離18設於基底12內並圍繞摻雜區36與閘極結構34，其中所有接觸淺溝隔離18的基底12邊緣包含一弧形輪廓28。亦即，第1圖至第2圖所示圖案化硬遮罩22的有開口24係暴露出第一區域14內所有接觸淺溝隔離18的基底12邊緣的淺溝隔離18。
相較於第5圖與第7圖的實施例，本實施例中弧形輪廓28所設置的區域42除了設於閘極結構34下方與切齊摻雜區36第一邊44的閘極結構寬度40之間外，又延伸至摻雜區36下方與摻雜區36第一邊44之間以及摻雜區36下方與第二邊46之間。換句話說，基底12的弧形結構28環繞了整個摻雜區36。
綜上所述，本發明主要先於一中壓元件區的基底上形成一圖案化遮罩覆蓋基底與部分淺溝隔離，然後在製作高壓元件區的閘極介電層時利用所通入的含氧氣體來改變中壓元件區基底中淺溝隔離的邊緣輪廓或接觸淺溝隔離的基底邊緣輪廓。由於高壓元件區並無上述圖案化遮罩的遮蔽，因此高壓元件的基底表面會直接形成一閘極介電層。中壓元件區由於圖案化遮罩的設置，因此所通入的含氧氣體較佳由圖案化遮罩的開口中進入並穿過淺溝隔離，使原本為鈍角的基底邊緣或淺溝隔離邊緣改變為一弧形輪廓，而此弧形輪廓即可用來改善現 行在尺寸日漸微縮下因淺溝隔離的設計而導致漏電流並連帶影響元件效能的問題。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧第一區域
16‧‧‧第二區域
18‧‧‧淺溝隔離
20‧‧‧襯墊層
22‧‧‧圖案化硬遮罩
24‧‧‧開口

Claims (16)

  1. 一種製作半導體元件的方法，包含：提供一基底，該基底具有一第一區域以及一第二區域；形成一淺溝隔離於該基底內並分隔該第一區域及該第二區域；形成一圖案化硬遮罩於該第一區域及部分該淺溝隔離上，其中該圖案化硬遮罩包含一開口暴露出部分該淺溝隔離；以及通入一氣體經由所暴露出之該淺溝隔離來藉此改變該第一區域之該基底之一邊緣。
  2. 如申請專利範圍第1項所述之方法，另包含：利用該氣體形成一第一閘極介電層於該第二區域之該基底上，並同時繞過該圖案化硬遮罩利用該氣體改變該第一區域之該基底之該邊緣。
  3. 如申請專利範圍第2項所述之方法，另包含：於形成該第一閘極介電層後去除該圖案化硬遮罩；以及形成一井區於該第一區域之該基底內。
  4. 如申請專利範圍第3項所述之方法，另包含：形成一襯墊層以及該圖案化硬遮罩於該第一區域之該基底上及部分該淺溝隔離上；形成該第一閘極介電層；去除該圖案化硬遮罩； 形成該井區；以及去除該襯墊層。
  5. 如申請專利範圍第4項所述之方法，另包含於去除該襯墊層之後形成一第二閘極介電層於該第一區域之該基底上。
  6. 如申請專利範圍第5項所述之方法，其中該第一閘極介電層之厚度大於該第二閘極介電層之厚度。
  7. 如申請專利範圍第5項所述之方法，另包含：形成一閘極結構於該第二閘極介電層上；以及形成一摻雜區於該第二閘極介電層兩側。
  8. 如申請專利範圍第5項所述之方法，其中該開口邊緣至該摻雜區邊緣之距離介於0.005微米至0.5微米。
  9. 如申請專利範圍第1項所述之方法，其中該氣體包含氧氣。
  10. 如申請專利範圍第1項所述之方法，另包含改變該第一區域之該基底之該邊緣並使該邊緣具有一弧形輪廓。
  11. 一種半導體元件，包含：一基底；一閘極結構設於該基底上；以及 一淺溝隔離設於該基底內並圍繞該閘極結構，其中接觸該淺溝隔離之該基底之一邊緣包含一弧形輪廓。
  12. 如申請專利範圍第11項所述之半導體元件，另包含一摻雜區設於該閘極結構兩側，其中該摻雜區包含一第一邊平行於該閘極結構之一寬度以及一第二邊平行於該閘極結構之一長度。
  13. 如申請專利範圍第12項所述之半導體元件，其中該弧形輪廓係介於該閘極結構下方及該摻雜區之該第一邊之間。
  14. 如申請專利範圍第12項所述之半導體元件，其中該淺溝隔離環繞該摻雜區之該第一邊及該第二邊。
  15. 如申請專利範圍第12項所述之半導體元件，其中該弧形輪廓係位於該閘極結構下方及部分該摻雜區下方。
  16. 如申請專利範圍第12項所述之半導體元件，其中該弧形輪廓係位於該閘極結構下方並環繞該摻雜區。
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