KR100603694B1 - 반도체 소자의 제조방법 - Google Patents
반도체 소자의 제조방법 Download PDFInfo
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- KR100603694B1 KR100603694B1 KR1020050034713A KR20050034713A KR100603694B1 KR 100603694 B1 KR100603694 B1 KR 100603694B1 KR 1020050034713 A KR1020050034713 A KR 1020050034713A KR 20050034713 A KR20050034713 A KR 20050034713A KR 100603694 B1 KR100603694 B1 KR 100603694B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims description 60
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 45
- 229920005591 polysilicon Polymers 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 34
- 239000010410 layer Substances 0.000 description 24
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (8)
- 로직 소자용 트랜지스터가 형성될 제1 영역, EEPROM 셀이 형성될 제2 영역 및 플래시 메모리 셀이 형성될 제3 영역으로 정의되는 반도체 기판을 제공하는 단계;상기 제1 내지 제3 영역의 상기 반도체 기판 상에 터널 산화막, 제1 폴리 실리콘막 및 제1 유전체막을 증착하는 단계;상기 제1 유전체막, 상기 제1 폴리 실리콘막 및 상기 터널 산화막을 식각하여 상기 제1 영역의 상기 기판을 노출시키는 동시에 상기 제2 영역에 제1 플로팅 게이트를 형성하는 단계;상기 제1 플로팅 게이트의 양측벽과 상기 제3 영역에 증착된 상기 제1 폴리 실리콘막 상에 제2 유전체막을 형성하는 단계;상기 제1 영역과, 상기 제1 플로팅 게이트의 양측으로 노출된 상기 기판 상에 게이트 산화막을 형성하는 단계;상기 제2 유전체막을 포함하는 전체 구조 상부에 제2 폴리 실리콘막을 증착하는 단계;상기 제2 폴리 실리콘막 및 상기 게이트 산화막을 식각하여 상기 제1 영역에 게이트 전극을 형성하고, 상기 제2 영역의 상기 제2 유전체막의 양측벽에 제1 컨트롤 게이트를 형성하는 단계;상기 제3 영역의 상기 제2 폴리 실리콘막, 상기 제2 유전체막, 상기 제1 폴 리 실리콘막 및 상기 터널 산화막을 식각하여 제2 플로팅 게이트와 상기 제2 컨트롤 게이트를 형성하는 단계; 및상기 게이트 전극, 상기 제1 컨트롤 게이트 및 상기 제2 컨트롤 게이트로 노출된 상기 기판에 각각 소오스/드레인 영역을 형성하는 단계를 포함하는 반도체 소자의 제조방법.
- 제 1 항에 있어서,상기 제1 유전체막 증착 후, 상기 제1 유전체막 상에 하드 마스크를 더 증착하는 단계를 더 포함하는 반도체 소자의 제조방법.
- 제 2 항에 있어서, 상기 제1 플로팅 게이트를 형성하는 단계는,마스크를 이용하여 상기 하드 마스크와 상기 제1 유전체막을 식각하는 단계;상기 마스크를 제거하는 단계; 및식각된 상기 하드 마스크를 식각 마스크로 이용한 식각공정을 실시하여 상기 제1 폴리 실리콘막 및 상기 터널 산화막을 식각하는 단계를 포함하는 반도체 소자의 제조방법.
- 제 2 항에 있어서,상기 하드 마스크는 산화막, 질화막, 산화질화막 또는 이들이 적층된 적층막으로 형성하는 반도체 소자의 제조방법.
- 제 1 항에 있어서,상기 게이트 산화막은 상기 제1 영역보다 상기 제2 영역에서 더 두껍게 형성하는 반도체 소자의 제조방법.
- 제 5 항에 있어서,상기 게이트 산화막 중 상기 제2 영역에 증착된 게이트 산화막은 상기 제1 컨트롤 게이트와 상기 기판 사이에 형성하는 반도체 소자의 제조방법.
- 제 1 항에 있어서,상기 제1 및 제2 유전체막은 산화막/질화막/산화막 구조로 형성하는 반도체 소자의 제조방법.
- 제 1 항에 있어서,상기 제2 컨트롤 게이트 형성 후, 상기 게이트 전극, 상기 제1 컨트롤 게이트, 상기 제2 플로팅 게이트 및 상기 제2 컨트롤 게이트의 양측벽에 스페이서를 형성하는 단계를 더 포함하는 반도체 소자의 제조방법.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050034713A KR100603694B1 (ko) | 2005-04-26 | 2005-04-26 | 반도체 소자의 제조방법 |
TW094142755A TWI297932B (en) | 2005-04-26 | 2005-12-05 | Method for fabricating semiconductor device |
US11/296,117 US7378315B2 (en) | 2005-04-26 | 2005-12-06 | Method for fabricating semiconductor device |
JP2005354256A JP4873940B2 (ja) | 2005-04-26 | 2005-12-08 | 半導体素子の製造方法 |
CNB2005100975341A CN100403521C (zh) | 2005-04-26 | 2005-12-30 | 用于制造半导体装置的方法 |
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KR1020050034713A KR100603694B1 (ko) | 2005-04-26 | 2005-04-26 | 반도체 소자의 제조방법 |
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KR1020050034713A KR100603694B1 (ko) | 2005-04-26 | 2005-04-26 | 반도체 소자의 제조방법 |
Country Status (5)
Country | Link |
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US (1) | US7378315B2 (ko) |
JP (1) | JP4873940B2 (ko) |
KR (1) | KR100603694B1 (ko) |
CN (1) | CN100403521C (ko) |
TW (1) | TWI297932B (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7820509B2 (en) | 2006-08-31 | 2010-10-26 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing the same |
KR101098440B1 (ko) | 2005-11-16 | 2011-12-27 | 매그나칩 반도체 유한회사 | 반도체 소자 제조방법 |
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CN102130065B (zh) * | 2010-01-18 | 2013-09-11 | 上海华虹Nec电子有限公司 | Eeprom的栅极制造方法及其制造的栅极 |
US20140353729A1 (en) * | 2013-05-29 | 2014-12-04 | United Microelectronics Corp. | Semiconductor structure and method for forming the same |
CN104752177B (zh) * | 2013-12-27 | 2017-11-10 | 中芯国际集成电路制造(上海)有限公司 | 一种制作嵌入式闪存栅极的方法 |
CN104752361B (zh) * | 2013-12-30 | 2019-02-12 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN104835791B (zh) * | 2014-02-10 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | 一种eeprom存储器件以及制备方法 |
CN105374753B (zh) * | 2014-07-07 | 2019-07-05 | 中芯国际集成电路制造(上海)有限公司 | 一种存储器的制造方法 |
CN105336698B (zh) * | 2014-07-10 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制造方法 |
CN105355600A (zh) * | 2014-08-20 | 2016-02-24 | 中芯国际集成电路制造(上海)有限公司 | 闪存的制作方法 |
CN105931992A (zh) * | 2016-05-17 | 2016-09-07 | 上海华力微电子有限公司 | 在不同区域形成两种不同结构侧墙的工艺方法 |
CN106941104B (zh) * | 2017-04-24 | 2019-09-17 | 上海华力微电子有限公司 | 一种结合耐高压晶体管的电荷捕获型非易失存储器制作方法 |
CN111834370B (zh) * | 2019-04-19 | 2024-03-15 | 华邦电子股份有限公司 | 集成电路及其制造方法 |
KR102274881B1 (ko) | 2019-07-05 | 2021-07-07 | 주식회사 키 파운드리 | 비휘발성 메모리 소자 |
KR102212751B1 (ko) | 2019-07-26 | 2021-02-04 | 주식회사 키 파운드리 | 비휘발성 메모리 소자 및 그 제조방법 |
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2005
- 2005-04-26 KR KR1020050034713A patent/KR100603694B1/ko active IP Right Grant
- 2005-12-05 TW TW094142755A patent/TWI297932B/zh active
- 2005-12-06 US US11/296,117 patent/US7378315B2/en active Active
- 2005-12-08 JP JP2005354256A patent/JP4873940B2/ja active Active
- 2005-12-30 CN CNB2005100975341A patent/CN100403521C/zh active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101098440B1 (ko) | 2005-11-16 | 2011-12-27 | 매그나칩 반도체 유한회사 | 반도체 소자 제조방법 |
US7820509B2 (en) | 2006-08-31 | 2010-10-26 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing the same |
US8324678B2 (en) | 2006-08-31 | 2012-12-04 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing the same |
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Publication number | Publication date |
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US7378315B2 (en) | 2008-05-27 |
JP2006310747A (ja) | 2006-11-09 |
TWI297932B (en) | 2008-06-11 |
US20060246659A1 (en) | 2006-11-02 |
JP4873940B2 (ja) | 2012-02-08 |
CN1855425A (zh) | 2006-11-01 |
TW200638517A (en) | 2006-11-01 |
CN100403521C (zh) | 2008-07-16 |
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