KR100297302B1 - 가변지연회로및반도체집적회로장치 - Google Patents

가변지연회로및반도체집적회로장치 Download PDF

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Publication number
KR100297302B1
KR100297302B1 KR1019970053891A KR19970053891A KR100297302B1 KR 100297302 B1 KR100297302 B1 KR 100297302B1 KR 1019970053891 A KR1019970053891 A KR 1019970053891A KR 19970053891 A KR19970053891 A KR 19970053891A KR 100297302 B1 KR100297302 B1 KR 100297302B1
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KR
South Korea
Prior art keywords
circuit
delay
gate
signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019970053891A
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English (en)
Korean (ko)
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KR19980063529A (ko
Inventor
사토시 에토
마사토 마츠미야
도시카즈 나카무라
마사토 다키타
도루 고가
히데키 가노
마사오 다구치
미츠히로 히가시호
아야코 기타모토
구니노리 가와바타
고이치 니시무라
요시노리 오카지마
Original Assignee
아끼구사 나오유끼
후지쯔 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of KR19980063529A publication Critical patent/KR19980063529A/ko
Application granted granted Critical
Publication of KR100297302B1 publication Critical patent/KR100297302B1/ko
Assigned to 후지쯔 세미컨덕터 가부시키가이샤 reassignment 후지쯔 세미컨덕터 가부시키가이샤 권리의 전부이전등록 Assignors: 후지쯔 가부시끼가이샤
Assigned to 가부시키가이샤 소시오넥스트 reassignment 가부시키가이샤 소시오넥스트 권리의 전부이전등록 Assignors: 후지쯔 세미컨덕터 가부시키가이샤
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
KR1019970053891A 1996-12-27 1997-10-21 가변지연회로및반도체집적회로장치 Expired - Fee Related KR100297302B1 (ko)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP96-349286 1996-12-27
JP34928696 1996-12-27
JP801297 1997-01-20
JP97-008012 1997-01-20
JP1921397 1997-01-31
JP97-019213 1997-01-31
JP97-127586 1997-05-16
JP12758697A JP3739525B2 (ja) 1996-12-27 1997-05-16 可変遅延回路及び半導体集積回路装置

Publications (2)

Publication Number Publication Date
KR19980063529A KR19980063529A (ko) 1998-10-07
KR100297302B1 true KR100297302B1 (ko) 2001-09-07

Family

ID=27454844

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970053891A Expired - Fee Related KR100297302B1 (ko) 1996-12-27 1997-10-21 가변지연회로및반도체집적회로장치

Country Status (3)

Country Link
US (2) US6049239A (https=)
JP (1) JP3739525B2 (https=)
KR (1) KR100297302B1 (https=)

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US6247138B1 (en) * 1997-06-12 2001-06-12 Fujitsu Limited Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system
JP3560780B2 (ja) * 1997-07-29 2004-09-02 富士通株式会社 可変遅延回路及び半導体集積回路装置
US6426985B1 (en) 1998-04-03 2002-07-30 Matsushita Electric Industrial Co., Ltd. Variable delay circuit and phase adjustment circuit
JP3320651B2 (ja) * 1998-05-06 2002-09-03 富士通株式会社 半導体装置
JP3439670B2 (ja) 1998-10-15 2003-08-25 富士通株式会社 階層型ｄｌｌ回路を利用したタイミングクロック発生回路
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JP3380206B2 (ja) * 1999-03-31 2003-02-24 沖電気工業株式会社 内部クロック発生回路
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KR100366618B1 (ko) 2000-03-31 2003-01-09 삼성전자 주식회사 클럭 신호의 듀티 사이클을 보정하는 지연 동기 루프 회로및 지연 동기 방법
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Also Published As

Publication number Publication date
US6049239A (en) 2000-04-11
JP3739525B2 (ja) 2006-01-25
US6377101B1 (en) 2002-04-23
JPH10276074A (ja) 1998-10-13
KR19980063529A (ko) 1998-10-07
US20020021157A1 (en) 2002-02-21

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