WO2003098414A1 - Apparatus for adjusting the phase of a digital signal - Google Patents
Apparatus for adjusting the phase of a digital signal Download PDFInfo
- Publication number
- WO2003098414A1 WO2003098414A1 PCT/SG2002/000098 SG0200098W WO03098414A1 WO 2003098414 A1 WO2003098414 A1 WO 2003098414A1 SG 0200098 W SG0200098 W SG 0200098W WO 03098414 A1 WO03098414 A1 WO 03098414A1
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- WO
- WIPO (PCT)
- Prior art keywords
- digital signal
- signal
- counting
- counting means
- delay
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
Definitions
- the invention relates to apparatus for adjusting the phase of a digital signal, and in particular, a timing signal for an integrated circuit.
- Distribution of a clock signal in an integrated circuit on a semiconductor chip suffers from delay (i.e. the time taken for the clock signal to reach a particular device on a chip) and skew (i.e. the difference in the delay of the clock signal between different devices on the chip). Both these parameters vary with temperature, voltage and the process parameters of the chip and so create an uncertainty in the timing performance of the integrated circuit.
- analog digital locked loop receives the clock signal and adjusts the phase of the clock signal in response to a feedback clock signal.
- Such analog digital locked loops operate by introducing more delay to the clock signal to ensure that the clock signal received by a particular device is in phase with the clock signal generated by the clock.
- analog digital locked loops require an analog macro which is dependent on the particular chip technology being used and has to be custom designed for a specific chip.
- a conventional analog digital locked loop is prone to suffering from jitter from the feedback loop.
- the DLL does not know exactly how much to compensate for the feedback, there is a tendency to always over or under compensate and this can generate a low frequency signal which is superimposed onto the clock output.
- apparatus for adjusting the phase of a digital signal comprising phase detection means, counting means and delay means, the phase detection means sending a counting start signal to the counting means to instruct the counting means to start counting when an edge of one of the input digital signal and the feedback digital signal is detected and sending a counting stop signal to the counting means to stop the counting means when the corresponding edge of the other of the input digital signal and the feedback reference digital signal is detected, the counting means outputting the count to the delay means, and the delay means delaying the input digital signal by an amount corresponding to the count of the counting means and outputting the delayed digital signal.
- the phase detection means comprises a first and second phase detection means
- the counting means comprises first and second counting means, the output from both the first and the second counting means being coupled to the delay means, the second phase detection means receiving the reference digital signal and an estimated delay signal, the first phase detection means receiving the input digital signal and the estimated delayed digital signal, and the second counting means outputting a signal indicative of the phase difference between the estimated signal and the reference signal to the delay means to generate a further estimated digital signal which is input to the first phase detecting means so that the first counting means generates an output indicative of the phase difference between the input digital signal and the further estimated digital signal to the delay means to generate the delayed digital signal.
- the counting means is a bi-directional counting means and most
- the apparatus further comprises a pulse forming circuit which receives the output from the phase detection means and generates an output which is
- an integrated circuit comprising apparatus in accordance with the first aspect of
- the input digital signal is a timing signal, such as a clock signal.
- FIG. 1 is a systematic block diagram of an all digital delay locked loop (ADLL).
- Figure 2 demonstrates an application of the ADLL digital delay lock loop.
- FIG 1 shows an all digital delay locked loop (ADLL) 1 which includes two
- the phase detector 2 takes as it inputs a digital clock signal 20 and an estimated clock signal clock tree signal 21.
- the phase detector 2 outputs a signal 22 if the phase of the clock signal 20 leads an estimated clock tree signal 21 , and outputs a signal 23 if the clock signal 20 lags the estimated clock tree signal 21.
- the signal 22 or 23 is received by the pulse forming circuit 4.
- the pulse forming circuit 4 generates a count up signal 24 to the counter 6 if it receives a signal 22, and generates a count down signal 25 if it receives a signal 23.
- the pulse forming circuit 4 generates an invert signal 26.
- the invert signal is useful in the case that, to save unnecessary buffers, the delay chain 14 is only designed to be capable of generating a maximum delay of half a clock period; in this case the pulse forming circuit 4 may identify that the delay to be produced by the delay chain 14 is more than this maximum delay, and pass the invert signal 26 via the counter 6 to the inversion logic 8 to instruct the delay chain 14 to invert the clock output signal, so as to effectively produce a longer delay.
- the counter 6 When the signal 24 or 25 stops, the counter 6 generates an output signal 27 representation of the result of the counting to the filtering logic 10.
- the filtering logic 10 filters the output signal 27 for jitter and outputs the filtered signal to the decoder 12.
- the decoder generates an output 28 to the delay chain 14 to instruct the delay chain 14 to add or subtract a delay to the phase of the clock input signal 20 to generate the clock output signal 30.
- phase detector 3 pulse forming circuit 5, synchronous up/down gray counter 7, inversion logic 9 and decoder 13 operating a similar manner to the phase detector 2, the pulse forming circuit 4, the synchronous up/down gray counter 6, the inversion logic 8, the filtering logic 10 and the decoder 12 apart from two significance differences.
- the filtering logic is not present between the counter 7 and the decoder 13 and secondly, the inputs to the phase detector 3 are the estimated clock tree signal 21 and a feedback signal 35. This section of the ADLL 1 is used to generate the estimated clock tree signal 21.
- FIG. 2 shows an example of the ADLL 1 in use in an integrated circuit, which includes a clock 40 and three devices 41 , 42, 43. Located between the ADLL 1 and each of the devices 41 , 42, 43 are a number of buffers 45 which are used to control the delay and skew of the clock signal 30 to the devices 41 , 42, 43. It will be noted that the ADLL 1 is used in a similar manner to a conventional analog/digital delay locked loop used in an integrated circuit.
- the invention has the advantages that it can be implemented using standard digital design with standard digital component units.
- the only non- digital section of the ADLL 1 is the delay chain 14 but this can be composed of standard delay cells (or buffers). Therefore, the technology used to implement the ADLL 1 is independent of the technology being used in the integrated circuit 50 and does not require to be custom made for a specific application.
Abstract
Apparatus (1) for adjusting the phase of a digital signal (20). The apparatus (1) includes phase detection means (2, 3), counting means (6, 7) and delay means (14). The phase detection means (2, 3) sends a counting start signal to the counting means (6, 7) to instruct the counting means (6, 7) to start counting when an edge of one of the input digital signal (20) and the feedback digital signal (21) is detected and sending a counting stop signal to the counting means (6, 7) to stop the counting means (6, 7) when the corresponding edge of the other of the input digital signal (20) and the feedback reference digital signal (21) is detected. The delay means (14) receives the input digital signal (20) and the count from the counting means (6, 7) and introduces a delay, corresponding to the count, to the input digital signal (20) to generate a delayed digital signal (30) and outputting the delayed digital signal (30).
Description
APPARATUS FOR ADJUSTING THE PHASE OF A DIGITAL SIGNAL
The invention relates to apparatus for adjusting the phase of a digital signal, and in particular, a timing signal for an integrated circuit.
Distribution of a clock signal in an integrated circuit on a semiconductor chip suffers from delay (i.e. the time taken for the clock signal to reach a particular device on a chip) and skew (i.e. the difference in the delay of the clock signal between different devices on the chip). Both these parameters vary with temperature, voltage and the process parameters of the chip and so create an uncertainty in the timing performance of the integrated circuit.
Therefore, it is desirable to design a chip so that the phase delay of the clock signal is zero. This can be done by introducing a delay into the clock signal path, for example by using buffers. However, if it is necessary to have predetermined skew between certain devices, it is necessary to introduce more buffers for one device which exacerbates the problem of changes in the delay and skew with changes temperature and voltage. In addition, more buffers also has the undesirable effect of increasing the size of chip required.
As the delay and skew vary with temperature and voltage, to cope with big temperature and voltage variations it is necessary to run a relatively slow clock speed to cope with the corresponding changes in delay and skew. If a faster
clock speed is desired, then it is necessary to more closely control the temperature of the chip and the voltages within the chips.
Conventionally, the problems of delay and skew have been addressed by incorporating an analog digital locked loop into the integrated circuit. The analog digital locked loop receives the clock signal and adjusts the phase of the clock signal in response to a feedback clock signal. Such analog digital locked loops operate by introducing more delay to the clock signal to ensure that the clock signal received by a particular device is in phase with the clock signal generated by the clock.
However, a problem with analog digital locked loops is that they require an analog macro which is dependent on the particular chip technology being used and has to be custom designed for a specific chip.
In addition, a conventional analog digital locked loop is prone to suffering from jitter from the feedback loop. As the DLL does not know exactly how much to compensate for the feedback, there is a tendency to always over or under compensate and this can generate a low frequency signal which is superimposed onto the clock output.
In accordance with the present invention, there is provided apparatus for adjusting the phase of a digital signal, the apparatus comprising phase detection means, counting means and delay means, the phase detection means
sending a counting start signal to the counting means to instruct the counting means to start counting when an edge of one of the input digital signal and the feedback digital signal is detected and sending a counting stop signal to the counting means to stop the counting means when the corresponding edge of the other of the input digital signal and the feedback reference digital signal is detected, the counting means outputting the count to the delay means, and the delay means delaying the input digital signal by an amount corresponding to the count of the counting means and outputting the delayed digital signal.
Preferably, the phase detection means comprises a first and second phase detection means, and the counting means comprises first and second counting means, the output from both the first and the second counting means being coupled to the delay means, the second phase detection means receiving the reference digital signal and an estimated delay signal, the first phase detection means receiving the input digital signal and the estimated delayed digital signal, and the second counting means outputting a signal indicative of the phase difference between the estimated signal and the reference signal to the delay means to generate a further estimated digital signal which is input to the first phase detecting means so that the first counting means generates an output indicative of the phase difference between the input digital signal and the further estimated digital signal to the delay means to generate the delayed digital signal.
Typically, the counting means is a bi-directional counting means and most
preferably is a synchronous up/ down gray counter.
Typically, the apparatus further comprises a pulse forming circuit which receives the output from the phase detection means and generates an output which is
coupled to the counting means.
In accordance with a second aspect of the present invention, there is provided an integrated circuit comprising apparatus in accordance with the first aspect of
the invention.
Typically, the input digital signal is a timing signal, such as a clock signal.
An example of apparatus for adjusting the phase of a digital signal in
accordance with the invention will now be described with reference to the accompanying drawings, in which
Figure 1 is a systematic block diagram of an all digital delay locked loop (ADLL); and
Figure 2 demonstrates an application of the ADLL digital delay lock loop.
Figure 1 shows an all digital delay locked loop (ADLL) 1 which includes two
phase detectors 2, 3, two pulse forming circuits 4, 5, two synchronous up/down
gray counters 6, 7, two inversion logics 8, 9, a filtering logic 10 and two decoders 12, 13 and a delay chain 14.
The phase detector 2 takes as it inputs a digital clock signal 20 and an estimated clock signal clock tree signal 21. The phase detector 2 outputs a signal 22 if the phase of the clock signal 20 leads an estimated clock tree signal 21 , and outputs a signal 23 if the clock signal 20 lags the estimated clock tree signal 21. The signal 22 or 23 is received by the pulse forming circuit 4. The pulse forming circuit 4 generates a count up signal 24 to the counter 6 if it receives a signal 22, and generates a count down signal 25 if it receives a signal 23. In addition, the pulse forming circuit 4 generates an invert signal 26. The invert signal is useful in the case that, to save unnecessary buffers, the delay chain 14 is only designed to be capable of generating a maximum delay of half a clock period; in this case the pulse forming circuit 4 may identify that the delay to be produced by the delay chain 14 is more than this maximum delay, and pass the invert signal 26 via the counter 6 to the inversion logic 8 to instruct the delay chain 14 to invert the clock output signal, so as to effectively produce a longer delay.
When the signal 24 or 25 stops, the counter 6 generates an output signal 27 representation of the result of the counting to the filtering logic 10. The filtering logic 10 filters the output signal 27 for jitter and outputs the filtered signal to the decoder 12. The decoder generates an output 28 to the delay chain 14 to
instruct the delay chain 14 to add or subtract a delay to the phase of the clock input signal 20 to generate the clock output signal 30.
The phase detector 3, pulse forming circuit 5, synchronous up/down gray counter 7, inversion logic 9 and decoder 13 operating a similar manner to the phase detector 2, the pulse forming circuit 4, the synchronous up/down gray counter 6, the inversion logic 8, the filtering logic 10 and the decoder 12 apart from two significance differences. Firstly, the filtering logic is not present between the counter 7 and the decoder 13 and secondly, the inputs to the phase detector 3 are the estimated clock tree signal 21 and a feedback signal 35. This section of the ADLL 1 is used to generate the estimated clock tree signal 21.
Figure 2 shows an example of the ADLL 1 in use in an integrated circuit, which includes a clock 40 and three devices 41 , 42, 43. Located between the ADLL 1 and each of the devices 41 , 42, 43 are a number of buffers 45 which are used to control the delay and skew of the clock signal 30 to the devices 41 , 42, 43. It will be noted that the ADLL 1 is used in a similar manner to a conventional analog/digital delay locked loop used in an integrated circuit.
However, the invention has the advantages that it can be implemented using standard digital design with standard digital component units. The only non- digital section of the ADLL 1 is the delay chain 14 but this can be composed of standard delay cells (or buffers). Therefore, the technology used to implement
the ADLL 1 is independent of the technology being used in the integrated circuit 50 and does not require to be custom made for a specific application.
Claims
1. Apparatus for adjusting the phase of a digital signal, the apparatus comprising phase detection means, counting means and delay means, the phase detection means sending a counting start signal to the counting means to instruct the counting means to start counting when an edge of one of the input digital signal and the feedback digital signal is detected and sending a counting stop signal to the counting means to stop the counting means when the corresponding edge of the other of the input digital signal and the feedback reference digital signal is detected, the delay means receiving the input digital signal and the count from the counting means, and introducing a delay, corresponding to the count, to the input digital signal to generate a delayed digital signal and outputting the delayed digital signal.
2. Apparatus according to claim 1 , wherein the phase detection means comprises a first and second phase detection means, and the counting means comprises first and second counting means, the output from both the first and the second counting means being coupled to the delay means, the second phase detection means receiving the reference digital signal and an estimated delay signal, the first phase detection means receiving the input digital signal and the estimated delayed digital signal, and the second counting means outputting a signal indicative of the phase difference between the estimated signal and the reference signal to the delay means to generate a further estimated digital signal which is input to the first phase detecting means so that the first counting means generates an output indicative of the phase difference between the input digital signal and the further estimated digital signal to the delay means to generate the delayed digital signal.
3. Apparatus according to claim 1 or claim 2, wherein the counting means is a bi-directional counting means.
4. Apparatus according to claim 3, wherein the bi-directional counting means is a synchronous up/ down gray counter.
5. Apparatus according to any of the preceding claims, further comprising a pulse forming circuit which receives the output from the phase detection means and generates an output, which is coupled to the counting means.
6. Apparatus according to any of the preceding claims, wherein the input digital signal is a timing signal for an integrated circuit.
7. Apparatus according to claim 6, wherein the timing signal is a clock signal.
8. An integrated circuit comprising apparatus in accordance with any of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/SG2002/000098 WO2003098414A1 (en) | 2002-05-16 | 2002-05-16 | Apparatus for adjusting the phase of a digital signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/SG2002/000098 WO2003098414A1 (en) | 2002-05-16 | 2002-05-16 | Apparatus for adjusting the phase of a digital signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2003098414A1 true WO2003098414A1 (en) | 2003-11-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/SG2002/000098 WO2003098414A1 (en) | 2002-05-16 | 2002-05-16 | Apparatus for adjusting the phase of a digital signal |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5249206A (en) * | 1989-08-11 | 1993-09-28 | International Business Machines Corporation | Fault-tolerant clock for multicomputer complex |
| US5471165A (en) * | 1993-02-24 | 1995-11-28 | Telefonaktiebolaget Lm Ericsson | Signal processing circuit and a method of delaying a binary periodic input signal |
| US5812835A (en) * | 1994-07-13 | 1998-09-22 | Nokia Telecommunications Oy | Method and system for automatic compensation of line delay in a clock distribution system |
| US6181175B1 (en) * | 1998-07-07 | 2001-01-30 | Alcatel | Clock generator and synchronizing method |
| WO2002029975A2 (en) * | 2000-10-06 | 2002-04-11 | Xilinx, Inc. | Digital phase shifter |
| US6377101B1 (en) * | 1996-12-27 | 2002-04-23 | Fujitsu Limited | Variable delay circuit and semiconductor integrated circuit device |
-
2002
- 2002-05-16 WO PCT/SG2002/000098 patent/WO2003098414A1/en not_active Application Discontinuation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5249206A (en) * | 1989-08-11 | 1993-09-28 | International Business Machines Corporation | Fault-tolerant clock for multicomputer complex |
| US5471165A (en) * | 1993-02-24 | 1995-11-28 | Telefonaktiebolaget Lm Ericsson | Signal processing circuit and a method of delaying a binary periodic input signal |
| US5812835A (en) * | 1994-07-13 | 1998-09-22 | Nokia Telecommunications Oy | Method and system for automatic compensation of line delay in a clock distribution system |
| US6377101B1 (en) * | 1996-12-27 | 2002-04-23 | Fujitsu Limited | Variable delay circuit and semiconductor integrated circuit device |
| US6181175B1 (en) * | 1998-07-07 | 2001-01-30 | Alcatel | Clock generator and synchronizing method |
| WO2002029975A2 (en) * | 2000-10-06 | 2002-04-11 | Xilinx, Inc. | Digital phase shifter |
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