KR100253696B1 - 반도체 집적회로 장치 및 그 제조방법 - Google Patents

반도체 집적회로 장치 및 그 제조방법 Download PDF

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Publication number
KR100253696B1
KR100253696B1 KR1019930701632A KR930701632A KR100253696B1 KR 100253696 B1 KR100253696 B1 KR 100253696B1 KR 1019930701632 A KR1019930701632 A KR 1019930701632A KR 930701632 A KR930701632 A KR 930701632A KR 100253696 B1 KR100253696 B1 KR 100253696B1
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KR
South Korea
Prior art keywords
region
element region
oxide film
peripheral
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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KR1019930701632A
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English (en)
Korean (ko)
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KR930702784A (ko
Inventor
나오타카 하시모토
도시아키 야마나카
다카시 하시모토
아키히로 시미즈
나가토시 오오키
히로시 이시다
Original Assignee
스즈키 진이치로
히타치 쪼오 엘.에스.아이.엔지니아링 가부시키가이샤
가나이 쓰도무
가부시끼가이샤 히다치 세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 스즈키 진이치로, 히타치 쪼오 엘.에스.아이.엔지니아링 가부시키가이샤, 가나이 쓰도무, 가부시끼가이샤 히다치 세이사꾸쇼 filed Critical 스즈키 진이치로
Publication of KR930702784A publication Critical patent/KR930702784A/ko
Application granted granted Critical
Publication of KR100253696B1 publication Critical patent/KR100253696B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
KR1019930701632A 1991-10-01 1993-05-31 반도체 집적회로 장치 및 그 제조방법 Expired - Fee Related KR100253696B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP25347291 1991-10-01
JP91-253472 1991-10-01
PCT/JP1992/001209 WO1993007641A1 (fr) 1991-10-01 1992-09-22 Dispositif a circuits integres a semi-conducteur et fabrication de ce dispositif

Publications (2)

Publication Number Publication Date
KR930702784A KR930702784A (ko) 1993-09-09
KR100253696B1 true KR100253696B1 (ko) 2000-04-15

Family

ID=17251862

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930701632A Expired - Fee Related KR100253696B1 (ko) 1991-10-01 1993-05-31 반도체 집적회로 장치 및 그 제조방법

Country Status (5)

Country Link
US (1) US5455438A (enExample)
EP (1) EP0560985A1 (enExample)
KR (1) KR100253696B1 (enExample)
TW (1) TW205112B (enExample)
WO (1) WO1993007641A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990008496A (ko) * 1997-07-01 1999-02-05 윤종용 복합 반도체 장치의 비대칭 게이트 산화막 제조 방법

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08111462A (ja) * 1994-10-12 1996-04-30 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
US5815433A (en) * 1994-12-27 1998-09-29 Nkk Corporation Mask ROM device with gate insulation film based in pad oxide film and/or nitride film
JPH08316223A (ja) * 1995-05-16 1996-11-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5576573A (en) * 1995-05-31 1996-11-19 United Microelectronics Corporation Stacked CVD oxide architecture multi-state memory cell for mask read-only memories
US5680345A (en) * 1995-06-06 1997-10-21 Advanced Micro Devices, Inc. Nonvolatile memory cell with vertical gate overlap and zero birds beaks
KR100214068B1 (ko) * 1995-11-21 1999-08-02 김영환 반도체 장치의 소자분리막 형성방법
KR100214469B1 (ko) * 1995-12-29 1999-08-02 구본준 반도체소자의 격리막 형성방법
KR100232197B1 (ko) * 1996-12-26 1999-12-01 김영환 반도체 소자의 제조 방법
KR19980057003A (ko) * 1996-12-30 1998-09-25 김영환 반도체 메모리 디바이스 및 그 제조방법
JPH10233392A (ja) * 1997-02-20 1998-09-02 Mitsubishi Electric Corp 半導体装置の製造方法
US5858830A (en) * 1997-06-12 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making dual isolation regions for logic and embedded memory devices
JP3583583B2 (ja) * 1997-07-08 2004-11-04 株式会社東芝 半導体装置及びその製造方法
JPH11145397A (ja) * 1997-11-11 1999-05-28 Mitsubishi Electric Corp 半導体集積回路装置
US6440819B1 (en) 1998-03-03 2002-08-27 Advanced Micro Devices, Inc. Method for differential trenching in conjunction with differential fieldox growth
JP4030198B2 (ja) * 1998-08-11 2008-01-09 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6674134B2 (en) * 1998-10-15 2004-01-06 International Business Machines Corporation Structure and method for dual gate oxidation for CMOS technology
JP3733252B2 (ja) * 1998-11-02 2006-01-11 セイコーエプソン株式会社 半導体記憶装置及びその製造方法
JP2001068564A (ja) * 1999-08-30 2001-03-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2001203347A (ja) 2000-01-18 2001-07-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4592193B2 (ja) * 2001-02-06 2010-12-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4738840B2 (ja) * 2004-03-16 2011-08-03 キヤノン株式会社 電子写真感光体
KR100591184B1 (ko) * 2004-12-30 2006-06-19 동부일렉트로닉스 주식회사 듀얼 버즈 비크 로코스 소자 분리 형성 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6379371A (ja) * 1986-09-24 1988-04-09 Hitachi Vlsi Eng Corp 半導体集積回路装置の製造方法
JPS63140567A (ja) * 1986-12-01 1988-06-13 Mitsubishi Electric Corp 半導体記憶装置
US5196910A (en) * 1987-04-24 1993-03-23 Hitachi, Ltd. Semiconductor memory device with recessed array region
JPS6411343A (en) * 1987-07-03 1989-01-13 Matsushita Electric Industrial Co Ltd Manufacture of semiconductor device
JPH0237158A (ja) * 1988-07-27 1990-02-07 Walbro Far East Inc ダイヤフラム型気化器
JPH02303049A (ja) * 1989-05-17 1990-12-17 Toshiba Corp 半導体装置およびその製造方法
JPH0346345A (ja) * 1989-07-14 1991-02-27 Nec Kyushu Ltd 半導体装置
JP2512216B2 (ja) * 1989-08-01 1996-07-03 松下電器産業株式会社 半導体装置の製造方法
JP2689004B2 (ja) * 1989-12-15 1997-12-10 三菱電機株式会社 半導体装置
US5057449A (en) * 1990-03-26 1991-10-15 Micron Technology, Inc. Process for creating two thicknesses of gate oxide within a dynamic random access memory
JPH1011343A (ja) * 1996-06-19 1998-01-16 Canon Inc 情報処理装置及び方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990008496A (ko) * 1997-07-01 1999-02-05 윤종용 복합 반도체 장치의 비대칭 게이트 산화막 제조 방법

Also Published As

Publication number Publication date
KR930702784A (ko) 1993-09-09
US5455438A (en) 1995-10-03
TW205112B (enExample) 1993-05-01
EP0560985A1 (en) 1993-09-22
EP0560985A4 (enExample) 1994-02-02
WO1993007641A1 (fr) 1993-04-15

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