JPWO2020157553A1 - - Google Patents
Info
- Publication number
- JPWO2020157553A1 JPWO2020157553A1 JP2020568866A JP2020568866A JPWO2020157553A1 JP WO2020157553 A1 JPWO2020157553 A1 JP WO2020157553A1 JP 2020568866 A JP2020568866 A JP 2020568866A JP 2020568866 A JP2020568866 A JP 2020568866A JP WO2020157553 A1 JPWO2020157553 A1 JP WO2020157553A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6733—Multi-gate TFTs
- H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
- H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
- Dram (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023171998A JP2023181189A (ja) | 2019-01-29 | 2023-10-03 | 記憶装置 |
Applications Claiming Priority (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019013607 | 2019-01-29 | ||
| JP2019012887 | 2019-01-29 | ||
| JP2019012887 | 2019-01-29 | ||
| JP2019013607 | 2019-01-29 | ||
| JP2019021404 | 2019-02-08 | ||
| JP2019021404 | 2019-02-08 | ||
| JP2019091842 | 2019-05-15 | ||
| JP2019091842 | 2019-05-15 | ||
| PCT/IB2019/059859 WO2020157553A1 (ja) | 2019-01-29 | 2019-11-18 | 記憶装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023171998A Division JP2023181189A (ja) | 2019-01-29 | 2023-10-03 | 記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2020157553A1 true JPWO2020157553A1 (enExample) | 2020-08-06 |
| JPWO2020157553A5 JPWO2020157553A5 (enExample) | 2022-11-04 |
| JP7361730B2 JP7361730B2 (ja) | 2023-10-16 |
Family
ID=71841365
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020568866A Active JP7361730B2 (ja) | 2019-01-29 | 2019-11-18 | 記憶装置 |
| JP2023171998A Withdrawn JP2023181189A (ja) | 2019-01-29 | 2023-10-03 | 記憶装置 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023171998A Withdrawn JP2023181189A (ja) | 2019-01-29 | 2023-10-03 | 記憶装置 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US12069846B2 (enExample) |
| JP (2) | JP7361730B2 (enExample) |
| CN (1) | CN113330554B (enExample) |
| TW (1) | TWI846763B (enExample) |
| WO (1) | WO2020157553A1 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11908947B2 (en) * | 2019-08-08 | 2024-02-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN114258586A (zh) | 2019-08-22 | 2022-03-29 | 株式会社半导体能源研究所 | 存储单元及存储装置 |
| KR20240093546A (ko) | 2021-10-27 | 2024-06-24 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 표시 장치 |
| WO2023144652A1 (ja) * | 2022-01-28 | 2023-08-03 | 株式会社半導体エネルギー研究所 | 記憶装置 |
| WO2023144653A1 (ja) * | 2022-01-28 | 2023-08-03 | 株式会社半導体エネルギー研究所 | 記憶装置 |
| WO2023152586A1 (ja) * | 2022-02-10 | 2023-08-17 | 株式会社半導体エネルギー研究所 | 半導体装置、及び半導体装置の作製方法 |
| KR20240152314A (ko) * | 2022-02-18 | 2024-10-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 제작 방법 |
| CN116209245B (zh) * | 2022-04-25 | 2024-06-18 | 北京超弦存储器研究院 | 一种动态存储器及其制作方法、存储装置 |
| US20250287612A1 (en) * | 2022-05-16 | 2025-09-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US11984165B2 (en) * | 2022-05-24 | 2024-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device with reduced area |
| US20250098187A1 (en) * | 2023-09-18 | 2025-03-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor memory cell structure including a hydrogen absorption layer |
Citations (5)
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|---|---|---|---|---|
| JP2009071313A (ja) * | 2007-09-12 | 2009-04-02 | Samsung Electronics Co Ltd | 積層メモリ装置 |
| JP2014082357A (ja) * | 2012-10-17 | 2014-05-08 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
| JP2015181159A (ja) * | 2014-03-07 | 2015-10-15 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| JP2018097907A (ja) * | 2016-11-17 | 2018-06-21 | 株式会社半導体エネルギー研究所 | 記憶装置 |
| JP2018195794A (ja) * | 2017-05-19 | 2018-12-06 | 株式会社半導体エネルギー研究所 | 記憶装置 |
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| US7606066B2 (en) * | 2005-09-07 | 2009-10-20 | Innovative Silicon Isi Sa | Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same |
| US7606098B2 (en) * | 2006-04-18 | 2009-10-20 | Innovative Silicon Isi Sa | Semiconductor memory array architecture with grouped memory cells, and method of controlling same |
| US7542340B2 (en) * | 2006-07-11 | 2009-06-02 | Innovative Silicon Isi Sa | Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same |
| JP2009211735A (ja) * | 2008-02-29 | 2009-09-17 | Toshiba Corp | 不揮発性記憶装置 |
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| JP7297683B2 (ja) | 2018-01-25 | 2023-06-26 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| JPWO2019202440A1 (ja) * | 2018-04-20 | 2021-05-13 | 株式会社半導体エネルギー研究所 | 記憶装置および電子機器 |
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| JP7577671B2 (ja) * | 2019-09-20 | 2024-11-05 | 株式会社半導体エネルギー研究所 | 半導体装置 |
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-
2019
- 2019-11-18 US US17/424,621 patent/US12069846B2/en active Active
- 2019-11-18 WO PCT/IB2019/059859 patent/WO2020157553A1/ja not_active Ceased
- 2019-11-18 JP JP2020568866A patent/JP7361730B2/ja active Active
- 2019-11-18 CN CN201980089912.1A patent/CN113330554B/zh active Active
- 2019-11-25 TW TW108142818A patent/TWI846763B/zh active
-
2023
- 2023-10-03 JP JP2023171998A patent/JP2023181189A/ja not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009071313A (ja) * | 2007-09-12 | 2009-04-02 | Samsung Electronics Co Ltd | 積層メモリ装置 |
| JP2014082357A (ja) * | 2012-10-17 | 2014-05-08 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
| JP2015181159A (ja) * | 2014-03-07 | 2015-10-15 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| JP2018097907A (ja) * | 2016-11-17 | 2018-06-21 | 株式会社半導体エネルギー研究所 | 記憶装置 |
| JP2018195794A (ja) * | 2017-05-19 | 2018-12-06 | 株式会社半導体エネルギー研究所 | 記憶装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP7361730B2 (ja) | 2023-10-16 |
| JP2023181189A (ja) | 2023-12-21 |
| TWI846763B (zh) | 2024-07-01 |
| TW202030730A (zh) | 2020-08-16 |
| US20220085020A1 (en) | 2022-03-17 |
| WO2020157553A1 (ja) | 2020-08-06 |
| CN113330554A (zh) | 2021-08-31 |
| KR20210121143A (ko) | 2021-10-07 |
| CN113330554B (zh) | 2025-06-06 |
| US12069846B2 (en) | 2024-08-20 |
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Legal Events
| Date | Code | Title | Description |
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| A80 | Written request to apply exceptions to lack of novelty of invention |
Free format text: JAPANESE INTERMEDIATE CODE: A801 Effective date: 20210618 |
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| A80 | Written request to apply exceptions to lack of novelty of invention |
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