JPWO2018220491A1 - 半導体装置、電子部品及び電子機器 - Google Patents
半導体装置、電子部品及び電子機器 Download PDFInfo
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- JPWO2018220491A1 JPWO2018220491A1 JP2019521526A JP2019521526A JPWO2018220491A1 JP WO2018220491 A1 JPWO2018220491 A1 JP WO2018220491A1 JP 2019521526 A JP2019521526 A JP 2019521526A JP 2019521526 A JP2019521526 A JP 2019521526A JP WO2018220491 A1 JPWO2018220491 A1 JP WO2018220491A1
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- oxide
- insulator
- transistor
- conductor
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Abstract
Description
本実施の形態では、本発明の一態様に係る半導体装置について説明する。本発明の一態様に係る半導体装置は、OSトランジスタを用いて形成された記憶回路を有する。
まず、本発明の一態様に係る半導体装置が有する記憶回路の構成例について説明する。図1(A−1)に、記憶回路MEMの構成例を示す。
図2に、半導体装置10の構成例を示す。半導体装置10は、OSトランジスタを用いて構成された単極性回路を備えた層20を有する。層20には、図1(A−1)に示す記憶回路MEMを設けることができる。
図2には、記憶回路MEMを有する層20が1層設けられた半導体装置10の構成例を示しているが、2層以上の層20を積層することもできる。図4に、N層(Nは2以上の整数)の層20(層20_1乃至20_N)が積層された構成を示す。層20_1乃至20_Nはそれぞれ、記憶回路MEM_1乃至記MEM_Nを有する。なお、記憶回路MEM_1乃至記MEM_Nの構成及び機能は、図2における記憶回路MEMと同様である。
図2には、層20に記憶回路MEMが設けられた構成例を示しているが、層20に設けられる回路は記憶回路MEMに限定されない。また、層20には機能の異なる複数の回路が設けられていてもよい。図5に、層20が記憶回路MEM、FPGA、及びアナログ演算回路を有する構成例を示す。
半導体装置10は、撮像装置としての機能を有していてもよい。図6に、撮像装置としての機能を有する半導体装置10の構成例を示す。図6に示す半導体装置10は、記憶回路MEMを有する層20(図2参照)の上方に、層40が積層された構造を有する。
本実施の形態では、上記実施の形態で説明した記憶回路の具体的な構成例について説明する。
本実施の形態では、上記実施の形態で説明した半導体装置の具体的な構成例について、図9乃至図27を用いて説明する。
図9乃至図14は、本発明の一態様に係る、トランジスタ700、メモリセル600a、およびメモリセル600bを有する半導体装置の上面図および断面図である。なお、以下において、メモリセル600aとメモリセル600bをまとめてメモリセル600という場合がある。
以下では、半導体装置に用いることができる構成材料について説明する。以下において、特段の記載を行わない場合、トランジスタ200に用いることができる構成材料は、トランジスタ700に用いることができるものとする。
トランジスタ200およびトランジスタ700を形成する基板としては、例えば、絶縁体基板、半導体基板または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えばSOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を1種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
酸化物230として、酸化物半導体として機能する金属酸化物(以下、酸化物半導体ともいう。)を用いることが好ましい。以下では、本発明に係る酸化物230に適用可能な金属酸化物について説明する。
以下では、本発明の一態様で開示されるトランジスタに用いることができるCAC(Cloud−Aligned Composite)−OSの構成について説明する。
酸化物半導体(金属酸化物)は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC−OS(c−axis aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc−OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)および非晶質酸化物半導体などがある。
続いて、上記金属酸化物をトランジスタのチャネル形成領域に用いる場合について説明する。
ここで、金属酸化物中における各不純物の影響について説明する。
以下では、図24乃至図27を用いて、本発明の一態様に係る半導体装置の一例について説明する。
本実施の形態では、本発明の一態様の半導体装置10を電子部品に適用する例について説明する。なお、電子部品は、半導体パッケージ、またはICパッケージともいう。半導体パッケージの一つに、複数の半導体チップ(集積回路)を1つのパッケージに実装したMCM(Multi Chip Module)が知られている。
本実施の形態では、上記実施の形態で説明した半導体装置および/または電子部品が搭載された電子機器の例について説明する。
Claims (8)
- セルアレイと、第1の駆動回路と、第2の駆動回路と、を有し、
前記セルアレイは、第1のメモリセル及び第2のメモリセルを有し、
前記第1の駆動回路は、選択信号を供給する機能を有し、
前記第2の駆動回路は、データの書き込み又は読み出しを行う機能を有し、
前記第1のメモリセルは、第1のトランジスタと、第1の容量素子と、を有し、
前記第2のメモリセルは、第2のトランジスタと、第2の容量素子と、を有し、
前記第1のトランジスタのソース又はドレインの一方は、前記第1の容量素子と電気的に接続され、
前記第2のトランジスタのソース又はドレインの一方は、前記第2の容量素子と電気的に接続され、
前記第1の駆動回路は、第3のトランジスタを有し、
前記第2の駆動回路は、第4のトランジスタを有し、
前記第1のトランジスタ、前記第2のトランジスタ、前記第3のトランジスタ、及び前記第4のトランジスタは、チャネル形成領域に金属酸化物を有し、
前記第1のトランジスタ、前記第2のトランジスタ、前記第3のトランジスタ、及び前記第4のトランジスタの極性は同一であり、
前記第1のトランジスタのチャネル形成領域及び前記第2のトランジスタのチャネル形成領域は、同一の半導体層に形成される半導体装置。 - 請求項1において、
制御回路を有し、
前記制御回路は、前記第1の駆動回路及び前記第2の駆動回路の動作を制御する機能を有し、
前記制御回路は、第5のトランジスタを有し、
前記第5のトランジスタは、チャネル形成領域に金属酸化物を有し、
前記第5のトランジスタの極性は、前記第1のトランジスタ、前記第2のトランジスタ、前記第3のトランジスタ、及び前記第4のトランジスタの極性と同一である半導体装置。 - 請求項1において、
前記第1のトランジスタは、第1のゲート電極と、第1の絶縁層と、を有し、
前記第2のトランジスタは、第2のゲート電極と、第2の絶縁層と、を有し、
前記第1の絶縁層は、前記第1のゲート電極の側面と接する領域を有し、
前記第2の絶縁層は、前記第2のゲート電極の側面と接する領域を有し、
前記半導体層は、前記第1の絶縁層又は前記第2の絶縁層の側面と接する領域を有する導電層と、電気的に接続されている半導体装置。 - 請求項3において、
前記第1のトランジスタ及び前記第2のトランジスタは、バックゲートを有し、
前記第1のトランジスタのバックゲート及び前記第2のトランジスタのバックゲートは、同一の導電層によって構成されている半導体装置。 - 請求項3又は4において、
前記半導体層は、表面に金属を含む層を有し、
前記金属を含む層は、前記第1のゲート電極、前記第2のゲート電極、第1の絶縁層、及び第2の絶縁層と重ならない領域に形成され、
前記金属は、前記半導体層の主成分とは異なる半導体装置。 - 請求項5において、
前記金属は、アルミニウム、ルテニウム、チタン、タンタル、タングステン、又はクロムである半導体装置。 - パッケージ基板と、インターポーザと、集積回路と、
請求項1に記載の半導体装置と、を有し、
前記集積回路および前記半導体装置は前記インターポーザ上に設けられ、
前記集積回路は前記インターポーザに設けられた配線を介して前記半導体装置と電気的に接続され、
前記集積回路または前記半導体装置の少なくとも一方は、
前記インターポーザを介して前記パッケージ基板と電気的に接続する電子部品。 - 請求項7に記載の電子部品と、
マイクロフォン、スピーカ、またはカメラと、
を有する電子機器。
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JP2012178555A (ja) * | 2011-02-02 | 2012-09-13 | Semiconductor Energy Lab Co Ltd | 半導体メモリ装置 |
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JP2017034249A (ja) * | 2015-07-29 | 2017-02-09 | 株式会社半導体エネルギー研究所 | 半導体装置、回路基板及び電子機器 |
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JP7191820B2 (ja) | 2022-12-19 |
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WO2018220491A1 (ja) | 2018-12-06 |
CN110678974B (zh) | 2023-11-28 |
CN110678974A (zh) | 2020-01-10 |
US11114470B2 (en) | 2021-09-07 |
KR20240015740A (ko) | 2024-02-05 |
CN117560925A (zh) | 2024-02-13 |
US20210384228A1 (en) | 2021-12-09 |
US20240088162A1 (en) | 2024-03-14 |
KR20200014801A (ko) | 2020-02-11 |
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