JPWO2013008543A1 - 高耐圧半導体装置 - Google Patents
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Abstract
Description
実施の形態1にかかる高耐圧半導体装置について、超接合(スーパージャンクション:SJ)構造を有する縦型MOSFET(以下、SJ−MOSFETとする)を例に説明する。図1は、本発明の実施の形態1にかかるSJ−MOSFETの構成を示す平面図である。図2は、図1のABCDを頂点にもつ矩形で囲まれた部分を拡大して示す平面図である。図1,2には、SJ構造の平面構造を明確に示すために、SJ構造の平面レイアウトのみを示す。
図5は、本発明の実施の形態2にかかるSJ−MOSFETの一部を拡大して示す平面図である。図6は、図5の切断線G−Hにおける断面構造を示す断面図である。図5には、図1の矩形ABCDで囲む部分の別の一例を示す。実施の形態2にかかるSJ−MOSFETが実施の形態1にかかるSJ−MOSFETと異なる点は、次の2点である。1つ目の相違点は、素子活性部1内で繰り返しパターン配置される並列pn層(メインSJセル12)が、ストライプ状の平面レイアウトではなく、nドリフト領域12a内にp仕切り領域12bがマトリクス状に配置された平面レイアウトとなっている点である。
2 耐圧構造部
3 n-領域(低濃度第1導電型半導体領域)
4 フィールド絶縁膜
5 ゲート絶縁膜
6 ゲート電極
7 ソース電極
8 ドレイン電極
9 層間絶縁膜
11 n+型半導体基板(n+ドレイン領域)
12 第1並列pn層(メインSJセル)
12a メインSJセルのnドリフト領域(第1導電型半導体領域)
12b メインSJセルのp仕切り領域(第2導電型半導体領域)
12E 第2並列pn層(微細SJセル)
12c 微細SJセルのnドリフト領域(第1導電型半導体領域)
12d 微細SJセルのp仕切り領域(第2導電型半導体領域)
13a pベース領域
13b p+コンタクト領域
14 n+ソース領域
15 ストッパー電極
実施の形態1にかかる高耐圧半導体装置について、超接合(スーパージャンクション:SJ)構造を有する縦型MOSFET(以下、SJ−MOSFETとする)を例に説明する。図1は、本発明の実施の形態1にかかるSJ−MOSFETの構成を示す平面図である。図2は、図1のABCDを頂点にもつ矩形で囲まれた部分を拡大して示す平面図である。図1,2には、SJ構造の平面構造を明確に示すために、SJ構造の平面レイアウトのみを示す。
図5は、本発明の実施の形態2にかかるSJ−MOSFETの一部を拡大して示す平面図である。図6は、図5の切断線G−Hにおける断面構造を示す断面図である。図5には、図1の矩形ABCDで囲む部分の別の一例を示す。実施の形態2にかかるSJ−MOSFETが実施の形態1にかかるSJ−MOSFETと異なる点は、次の2点である。1つ目の相違点は、素子活性部1内で繰り返しパターン配置される並列pn層(メインSJセル12)が、ストライプ状の平面レイアウトではなく、nドリフト領域12a内にp仕切り領域12bがマトリクス状に配置された平面レイアウトとなっている点である。
2 耐圧構造部
3 n-領域(低濃度第1導電型半導体領域)
4 フィールド絶縁膜
5 ゲート絶縁膜
6 ゲート電極
7 ソース電極
8 ドレイン電極
9 層間絶縁膜
11 n+型半導体基板(n+ドレイン領域)
12 第1並列pn層(メインSJセル)
12a メインSJセルのnドリフト領域(第1導電型半導体領域)
12b メインSJセルのp仕切り領域(第2導電型半導体領域)
12E 第2並列pn層(微細SJセル)
12c 微細SJセルのnドリフト領域(第1導電型半導体領域)
12d 微細SJセルのp仕切り領域(第2導電型半導体領域)
13a pベース領域
13b p+コンタクト領域
14 n+ソース領域
15 ストッパー電極
Claims (6)
- 第1導電型高不純物濃度の半導体基板の一方の主面に垂直な方向に長手形状を有する第1導電型半導体領域と第2導電型半導体領域とが前記半導体基板の主面に平行な方向に交互に隣接する並列pn層をドリフト層として備え、前記並列pn層がオン状態で電流が流れ、オフ状態で空乏化して電圧を阻止する構成を有する高耐圧半導体装置であって、
前記並列pn層のうち、主電流経路となる素子活性部内の第1並列pn層と、
前記並列pn層のうち、前記素子活性部を取り巻く耐圧構造部内の第2並列pn層と、
を備え、
前記並列pn層内の隣接数が偶数であり、
前記第2並列pn層内の前記第1導電型半導体領域と前記第2導電型半導体領域との隣接ピッチが、前記第1並列pn層内の前記第1導電型半導体領域と前記第2導電型半導体領域との隣接ピッチの2/3であり、
矩形状の平面形状を有する前記半導体基板の四隅のコーナー部の前記第1並列pn層と前記第2並列pn層との境界が、前記第1並列pn層の隣接する2つの端部と前記第2並列pn層の隣接する3つの端部とが対向することを特徴とする高耐圧半導体装置。 - 前記第2並列pn層の表面に、前記第1並列pn層の前記第1導電型半導体領域よりも不純物濃度の低い低濃度第1導電型半導体領域をさらに備えることを特徴とする請求項1に記載の高耐圧半導体装置。
- 前記第1並列pn層は、前記第1導電型半導体領域と前記第2導電型半導体領域とが交互に繰り返し並ぶ方向に直交する方向に延びるストライプ状の平面レイアウトを有することを特徴とする請求項2に記載の高耐圧半導体装置。
- 前記半導体基板の四隅のコーナー部に位置する前記第1並列pn層の端部の長さを偶数ピッチ毎に変えることにより、前記素子活性部の外周の、前記耐圧構造部の四隅のコーナー部付近の部分に曲率部を構成し、
前記第2並列pn層の最内側端部が前記曲率部に対応する長さで前記半導体基板の主面に平行に前記半導体基板の内側に向かって延びていることを特徴とする請求項1に記載の高耐圧半導体装置。 - 前記第1並列pn層は、前記第1導電型半導体領域内に前記第2導電型半導体領域がマトリクス状に配置された平面レイアウトを有することを特徴とする請求項4に記載の高耐圧半導体装置。
- 前記並列pn層内の半導体領域がチャージバランスをとるための遷移部を備えていないことを特徴とする請求項1〜5のいずれか一つに記載の高耐圧半導体装置。
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CN103493207B (zh) | 2011-07-14 | 2016-03-09 | 富士电机株式会社 | 高击穿电压半导体器件 |
US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
KR102098983B1 (ko) * | 2013-03-13 | 2020-04-08 | 우베 고산 가부시키가이샤 | 절연 피복층의 제조 방법 |
US9806147B2 (en) * | 2014-01-27 | 2017-10-31 | Renesas Electronics Corporation | Semiconductor device |
US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
JP6477174B2 (ja) | 2015-04-02 | 2019-03-06 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US9881997B2 (en) | 2015-04-02 | 2018-01-30 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
DE102015106707A1 (de) | 2015-04-30 | 2016-11-03 | Infineon Technologies Austria Ag | Halbleiterbauelemente und Verfahren zum Bilden eines Halbleiterbauelements |
CN104916700B (zh) * | 2015-06-18 | 2018-05-25 | 中航(重庆)微电子有限公司 | 超级结布局结构 |
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CN105206674A (zh) * | 2015-08-11 | 2015-12-30 | 张家港意发功率半导体有限公司 | 一种超结终端的vdmos结构 |
JP6747195B2 (ja) | 2016-09-08 | 2020-08-26 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN106571394B (zh) * | 2016-11-01 | 2018-05-11 | 杭州士兰微电子股份有限公司 | 功率器件及其制造方法 |
CN111370494B (zh) * | 2018-12-26 | 2023-07-14 | 深圳尚阳通科技股份有限公司 | 超结器件 |
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JP2003224273A (ja) * | 2002-01-30 | 2003-08-08 | Fuji Electric Co Ltd | 半導体装置 |
JP2005051190A (ja) * | 2003-07-16 | 2005-02-24 | Fuji Electric Holdings Co Ltd | 半導体素子およびその製造方法 |
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