JPS61239650A - 高速集積回路パツケ−ジ - Google Patents

高速集積回路パツケ−ジ

Info

Publication number
JPS61239650A
JPS61239650A JP60077550A JP7755085A JPS61239650A JP S61239650 A JPS61239650 A JP S61239650A JP 60077550 A JP60077550 A JP 60077550A JP 7755085 A JP7755085 A JP 7755085A JP S61239650 A JPS61239650 A JP S61239650A
Authority
JP
Japan
Prior art keywords
wiring
width
integrated circuit
characteristic impedance
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60077550A
Other languages
English (en)
Other versions
JPH0812887B2 (ja
Inventor
Akira Miyauchi
彰 宮内
Hiroshi Nishimoto
央 西本
Tadashi Okiyama
沖山　正
Hiroo Kitasagami
北相模　博夫
Masahiro Sugimoto
杉本　正浩
Haruo Tamada
玉田　春男
Shinji Emori
江森　伸二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60077550A priority Critical patent/JPH0812887B2/ja
Priority to CA000506182A priority patent/CA1246170A/en
Priority to AT86302753T priority patent/ATE68915T1/de
Priority to DE8686302753T priority patent/DE3682101D1/de
Priority to EP86302753A priority patent/EP0198698B1/en
Publication of JPS61239650A publication Critical patent/JPS61239650A/ja
Priority to US07/222,303 priority patent/US4875087A/en
Priority to SG589/92A priority patent/SG58992G/en
Priority to HK565/92A priority patent/HK56592A/xx
Publication of JPH0812887B2 publication Critical patent/JPH0812887B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔概要〕 半導体集積回路チップを気密封止する部分に於ける配線
の幅を狭くして、その配線のマイクロストリップライン
構造となる部分と平衡型ストリップライン構造となる部
分の特性インピーダンスを整合させて、高速信号の伝搬
特性を改善したものである。
〔産業上の利用分野〕
本発明は、数Ｇ　ｂ　／　ｓ程度の高速動作を可能とし
た半導体集積回路チップを気密封止し、高速動作特性を
改善した高速集積回路パッケージに関するものである。
半導体技術の進歩により、数Ｇ　ｂ　／　ｓ程度の高速
伝送信号の処理用の半導体集積回路が実現している。こ
のような高速半導体集積回路に於いても、信頼性向上の
為に半導体集積回路チップはパッケージにより気密封止
され、半導体集積回路チップと接続された外部端子が導
出されて、外部装置との接続を行う必要がある。
〔従来の技術〕
Ｓｔ（シリコン）又はＧａＡｓ　　（ガリウム砒素）等
の半導体チップに複数のトランジスタ等を形成した高速
動作可能の半導体集積回路チップを気密封止するパッケ
ージは、例えば、第３図の要部断面図及び第４図の要部
平面図に示す構成を有するものであった。即ち、下面に
金属膜１４が形成されたセラミック等の絶縁基板１２上
に半導体集積回路チップ１６が搭載され、その半導体集
積回路チップ１６と配＆’１ｌｌｌとがアルミニウム或
いは金の接続線１７で接続され、金属のキャップ１５に
より半導体集積回路チップ１６の気密封止が行われるも
のである。この場合、キャップ１５と配線１１との間に
は絶縁体１３が介在されている。
又配線１１が気密封止部分から延長されて外部端子とな
る。
この外部端子は、プリント基板１Ｂの配線１９と半田等
により接続され、所望の信号処理装置が構成されるもの
である。
〔発明が解決しようとする問題点〕
半導体集積回路チップ１Ｇが気密封止された内部に於け
る配線１１は、絶縁基板１２の下面に金属　　　　　　
　　属膜１４が形成されており、上部が空間であるかト らマイクロストリップライン構造となり、又気密封止部
分では、絶縁基板Ｉ２と絶縁体Ｉ３とにより挟まれて、
それらの厚さや誘電率を同一とすることにより平衡型ス
トリップライン構造となる。
従って、この平衡型ストリップライン構造となる配線１
１部分に於いては、絶縁体１３の誘電率に対応して特性
インピーダンスが低下することになる。その為、配＆１
ｌｌｌを伝搬する信号に対して特性インピーダンスの不
整合による反射損失等が生じる欠点があった。
本発明は、このような特性インピーダンスの不整合をな
くすことを目的とするものである。
〔問題点を解決するための手段〕
本発明の高速集積回路パッケージは、第１図を参照して
説明すると、下面に金属膜を形成したセラミック等の絶
縁基板２上に半導体集積回路チップ６を搭載し、その半
導体集積回路チップ６と配線１とを接続線７で接続し、
その配線１を延長して外部端子１ｃとし、キャップによ
って半導体集積回路チップ６を気密封止し、その気密封
止の配線部分１ｂとキャップとの間に絶縁体３を介在さ
せて、平衡型ストリップライン構造とし、この平衡型ス
トリップライン構造となる配線部分１ｂの幅を、他のマ
イクロストリップライン構造となる配線部分１ａの幅よ
り狭くしたものである。
〔作用〕
配線の幅を狭くすることにより特性インピーダンスは大
きくなり、又平衡型ストリップラインは誘電体によって
配線が挟まれるので、特性インピーダンスが小さくなる
傾向を有するものであり、気密封止部分の配線は、平衡
型ストリップライン構造であるから、特性インピーダン
スが小さくなるが、その配線１ｂの幅を狭くすることに
より特性インピーダンスを大きくし、結果として他のマ
イクロストリップライン構造の配線部分と同じ特性イン
ピーダンスとすることが可能となり、特性インピーダン
スの整合をとることができる。
〔実施例〕
以下図面を参照して本発明の実施例について詳細に説明
する。
第１図は本発明の実施例の要部平面図、第２図は要部断
面図であり、下面に金属膜４が形成されたセラミック等
の絶縁基板２上に、半導体集積回路チップ６を搭載し、
配線１と接続線７で接続する。又金属のキャップ５と絶
縁基板２の周辺とを絶縁体３を介して接合し、半導体集
積回路チップ６を気密封止する。配線１は、内部配線部
分１ａと気密封止配線部分１ｂと外部端子ＩＣとからな
り、気密封止配線部分１ｂは、絶縁基板２と絶縁体３と
に挟まれて平衡型ストリップラインを構成し、内部配線
部分１ａは上部が空間のマイクロストリップラインを構
成している。なお、気密封止手段は半導体集積回路パッ
ケージに於番ｆる公知の手段を採用することができるも
のである。
配線１に於いて、平衡型ストリップライン構造の気密封
止配線部分１ｂの輻Ｗｂを、マイクロストリップライン
構造の内部配線部分１ａの幅Ｗａより狭くするものであ
る。この幅Ｗａ、Ｗｂの関係は、絶縁基板２と絶縁体３
との誘電率や厚さに対応して特性インピーダンスが整合
するように選定されるものである。
例えば、絶縁基板２と絶縁体３とのそれぞれの誘電率ε
−１０、それぞれの厚さｔ＝３３０μｍ、配線１の厚さ
ｄ−１５μｍとし、内部配線部分１ａの幅Ｗａを３００
μｍとして、特性インピーダンスＺＱ＝５０Ωとした場
合に、気密封止配線部分１ｂの幅ｗｂを３００μｍとす
ると、その気密封止配線部分１ｂの特性インピーダンス
ば３３Ωとなり、特性インピーダンスの不整合が生じる
ことになる。しかし、気密封止配線部分１ｂの幅ｗｂを
１１００ｘ１とすると、その部分に於ける特性インピー
ダンスはほぼ５０Ωとなり、特性インピーダンスの不整
合は生じないことになる。
又内部配線部分１ａと気密封止配線部分１ｂとの境界部
分の幅の変化は、気密封止部分の構成に対応して連続的
となるようにすることもできる。
〔発明の効果〕
以」二説明したように、本発明は、半導体集積回路子ツ
ブ６と接続した配′ｆＬＩＡ１を延長して外部端子１ｃ
とし、気密封止される配線部分１ｂの幅ｗｂを内部配線
部分１ａの幅Ｗａより狭くしたことにより、内部配線部
分１ａと気密封止配線部分１ｂとの特性インピーダンス
を整合させることができる。又外部端子ＩＣの特性イン
ピーダンスとの整合をとることもできる。従って、高速
信号の伝搬特性を改善することができる利点がある。
【図面の簡単な説明】
第１図は本発明の実施例の要部平面図、第２図は本発明
の実施例の要部断面図、第３図は従来例の要部断面図、
第４図は従来例の要部平面図である。 １は配線、１ａは内部配線部分、１ｂは気密封止配線部
分、ＩＣは外部端子、２は絶縁基板、３は絶縁体、４は
金属膜、５はキャップ、６は半導体集積回路チップ、７
は接続線である。

Claims (1)

  1. 【特許請求の範囲】 　下面に金属膜（４）を有する絶縁基板（２）上に搭載
    した半導体集積回路チップ（６）と、該半導体集積回路
    チップ（６）と接続して外部端子とする配線（１）と、 前記絶縁基板（２）の周辺と接合させて前記半導体集積
    回路チップ（６）を気密封止するキャップ（５）とを備
    えた高速集積回路パッケージに於いて、 前記絶縁基板（２）と前記キャップ（５）との間の平衡
    型ストリップライン構造となる気密封止配線部分（１ｂ
    ）の幅を、他のマイクロストリップライン構造となる配
    線部分（１ａ）の幅より狭くした ことを特徴とする高速集積回路パッケージ。
JP60077550A 1985-04-13 1985-04-13 高速集積回路パツケ−ジ Expired - Lifetime JPH0812887B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP60077550A JPH0812887B2 (ja) 1985-04-13 1985-04-13 高速集積回路パツケ−ジ
CA000506182A CA1246170A (en) 1985-04-13 1986-04-09 Integrated circuit device having strip line structure therein
AT86302753T ATE68915T1 (de) 1985-04-13 1986-04-14 Integrierte schaltung mit eingebauter streifenleiterstruktur.
DE8686302753T DE3682101D1 (de) 1985-04-13 1986-04-14 Integrierte schaltung mit eingebauter streifenleiterstruktur.
EP86302753A EP0198698B1 (en) 1985-04-13 1986-04-14 Integrated circuit device having strip line structure therein
US07/222,303 US4875087A (en) 1985-04-13 1988-07-22 Integrated circuit device having strip line structure therein
SG589/92A SG58992G (en) 1985-04-13 1992-06-03 Integrated circuit device having strip line structure therein
HK565/92A HK56592A (en) 1985-04-13 1992-07-30 Gain controlled electronic ballast system integrated circuit device having strip line structure therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60077550A JPH0812887B2 (ja) 1985-04-13 1985-04-13 高速集積回路パツケ−ジ

Publications (2)

Publication Number Publication Date
JPS61239650A true JPS61239650A (ja) 1986-10-24
JPH0812887B2 JPH0812887B2 (ja) 1996-02-07

Family

ID=13637119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60077550A Expired - Lifetime JPH0812887B2 (ja) 1985-04-13 1985-04-13 高速集積回路パツケ−ジ

Country Status (8)

Country Link
US (1) US4875087A (ja)
EP (1) EP0198698B1 (ja)
JP (1) JPH0812887B2 (ja)
AT (1) ATE68915T1 (ja)
CA (1) CA1246170A (ja)
DE (1) DE3682101D1 (ja)
HK (1) HK56592A (ja)
SG (1) SG58992G (ja)

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US5218230A (en) * 1990-09-28 1993-06-08 Fujitsu Limited Ic package with electric conductor lines in dielectric package body
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EP0732745A3 (en) * 1995-03-16 1998-07-29 Oxley Developments Company Limited Microstrip microwave package
JP2012060533A (ja) * 2010-09-10 2012-03-22 Fujitsu Ltd 高周波回路用パッケージ及び高周波回路装置

Also Published As

Publication number Publication date
EP0198698A2 (en) 1986-10-22
US4875087A (en) 1989-10-17
CA1246170A (en) 1988-12-06
DE3682101D1 (de) 1991-11-28
SG58992G (en) 1992-09-04
HK56592A (en) 1992-08-07
EP0198698B1 (en) 1991-10-23
JPH0812887B2 (ja) 1996-02-07
EP0198698A3 (en) 1988-08-03
ATE68915T1 (de) 1991-11-15

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