JPS6118164A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6118164A
JPS6118164A JP59139820A JP13982084A JPS6118164A JP S6118164 A JPS6118164 A JP S6118164A JP 59139820 A JP59139820 A JP 59139820A JP 13982084 A JP13982084 A JP 13982084A JP S6118164 A JPS6118164 A JP S6118164A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
active region
numeral
shows
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59139820A
Other languages
English (en)
Inventor
Kazushi Nagata
一志 永田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59139820A priority Critical patent/JPS6118164A/ja
Publication of JPS6118164A publication Critical patent/JPS6118164A/ja
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、ＩＣ，）ランジスタワサイリスク等の放熱
効果および基板の重ね合わせにおける集積度の向上をも
友ら丁りめｋ、ポンディングバンド部７側面に設けた半
導体装置に関するものである。
〔従来技術〕
従来のＩＣやトランジスタな第１図に示す。
第１図において、１は半導体基板、２はＰＮ接合領域お
よびその上に形成された配線部を含む能動領域、３は前
記能動領域２より外部に電気信号を出入するＬめの接続
部である。通常、この接続部３はポンディングパッドと
呼ばハ、アルミニワム管で形成さｎ１第１図の部分斜視
図である第２図に示すよ５Ｋ、アルミ線や金線等の接続
線４を接続部３に圧着して基板外部と電気的に接続して
いる。通常、ＩＣの場合、第３図に示すように半導体基
板１を外の雰囲気から保護するためにパッケージＳＶｃ
入れ、ビン６と接続線４ｙ通じて電気的に外部と接続す
る。７は前記パッケージ５の蓋である。
従来の半導体装置の大部分は第３図のように構成さｎて
いるので、半導体基板１の能動領域２を含む面と接続部
３が同一表面であり、ビン６等との接続のための間隙８
が必要である。パッケージ５がプラスチックの場合、こ
の間隙８はプラスチック充填剤で埋めらｎている。
半導体装置の集積度を上げるために基板を重ね合わせよ
うとした時、このような間隙８があるとスペースの点で
重ね合わせることが困難性であるという欠点がある。ま
た、この半導体基板１が、動作中に多量の熱ン放出てる
場合、通常、能動領域２を含む面に熱が発生するが１間
隙８が存在するためＫｉＴを通じて外部との熱交換が容
−易にできない欠点がある。
〔発明の概要〕
この発明は、上記のような従来のものの欠点を除去する
ためＫなさｔｔｙ、−もので、能動領域を含む主面の側
面に接続部Ｙ形成することにより間隙を除き、半導体基
板の重ね合わせ、または外部放熱−’に容易にする半導
体装置を提供するものである。
以下、この発明ン図面について説明する。
〔発明の実施例〕
第４図はこの発明の一実施例を示すもので、この図にお
いて、１，２．３は第１図と同様の部分である。この実
施例では接続部３ン能動領域２を含む主面の側面に形成
している。このように形成することにより、第５図に示
すように半導体基板１を複数枚重ね合わせることができ
る。第５図におい工、９は各半導体基板１間の放熱およ
び接着のｋめの充填材である。
一！た、第６図にこの発明の他の実施例を示す。
第６図では、放熱を良好忙するπめに間隙をつくらずに
、接続部３の外周面をパッケージ５で覆っている。この
ような構１；ＶＣよって、上面の蓋７と、側面および底
面を形成するパッケージ５と匠よって外部との熱接触を
容易托し、放熱効果ｔあげている。
また、第７図に示すように側面の各接続部３間を接続線
４で接続し、最終的に能動領域２を含む面の接続部３よ
り外部に接続することもできる。
なお、上記各実施例ではＩＣへの適用例を示し友が、ト
ランジスタやその他の半導体素子にも適用することがで
きる。また、接続部３を能動領域２からの配線部として
示したが、通常の半導体基板では、この能動領域２ン含
む面の反対側からも電気的に接続をもつものも多く、こ
の場合にも上記各実施例を適用することができる。
〔発明の、効果〕
以上説明したように、この発明は、半導体基板の一表面
上ＫＰＮ接合領域と、このＰＮ接合領域忙電気的接続を
する配線部とからなる能動領域ン有する半導体装置忙お
いて、前記配線部の前記半導体基板外部との接続部を、
前記半導体基板の側面に設けることＫより、より集積度
の高いＩＣや、放熱性の良好なＩＣｖ含む半導体装置が
得られるという効果がある。
【図面の簡単な説明】
第１図は従来の半導体装置を説明するための斜視図、第
２図は第１図の部分斜視図、第３図は第１図の断面側面
図、第４図はこの発明の一実施例の半導体装置の斜視図
、第５図は第４図の半導体装置を複数個積重ねた斜視図
、第６図はこの発明の他の実施例の側断面図、第７図は
この発明の他の実施例の半導体装置の斜視図である。 図中、１は半導体基板、２は能動領域、３は接続部、４
は接続線、５はパッケージ、６はビン、７は蓋、９は充
填材である。 なお、図中の同一符号は同一または相当部分を示す。 代理人　大岩増雄　　　（外２名） 第１図 第２図 ム 第３図 第４図 第５図 第６図 Ｉ　　　　　　　Ｊ　　　　ｂ 第７図

Claims (1)

    【特許請求の範囲】
  1. 半導体基板の一表面上にＰＮ接合領域と、このＰＮ接合
    領域に電気的接続をする配線部とからなる能動領域を有
    する半導体装置において、前記配線部の前記半導体基板
    外部との接続部を、前記半導体基板の側面に設けたこと
    を特徴とする半導体装置。
JP59139820A 1984-07-04 1984-07-04 半導体装置 Pending JPS6118164A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59139820A JPS6118164A (ja) 1984-07-04 1984-07-04 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59139820A JPS6118164A (ja) 1984-07-04 1984-07-04 半導体装置

Publications (1)

Publication Number Publication Date
JPS6118164A true JPS6118164A (ja) 1986-01-27

Family

ID=15254222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59139820A Pending JPS6118164A (ja) 1984-07-04 1984-07-04 半導体装置

Country Status (1)

Country Link
JP (1) JPS6118164A (ja)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63110740A (ja) * 1986-10-29 1988-05-16 Nec Corp 半導体装置
JPH01168041A (ja) * 1987-11-18 1989-07-03 Grumman Aerospace Corp 集積回路チップの製造方法
US5051865A (en) * 1985-06-17 1991-09-24 Fujitsu Limited Multi-layer semiconductor device
FR2666452A1 (fr) * 1990-09-03 1992-03-06 Mitsubishi Electric Corp Module de circuit a semiconducteurs multicouche.
EP0522518A2 (en) * 1991-07-09 1993-01-13 Hughes Aircraft Company Stacked chip assembly and manufacturing method therefor
EP0593666A1 (en) * 1991-06-24 1994-04-27 Irvine Sensors Corporation Fabricating electronic circuitry unit containing stacked ic layers having lead rerouting
WO2009025974A2 (en) * 2007-08-16 2009-02-26 Micron Technology, Inc. Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
US7692931B2 (en) 2006-07-17 2010-04-06 Micron Technology, Inc. Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
US7843050B2 (en) 2007-07-24 2010-11-30 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
CN107994001A (zh) * 2017-11-28 2018-05-04 信利光电股份有限公司 一种芯片封装和终端设备
JP2022047488A (ja) * 2020-09-11 2022-03-24 ウェスタン デジタル テクノロジーズ インコーポレーテッド シリコンダイのストレートワイヤボンディング

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5655067A (en) * 1979-10-11 1981-05-15 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device
JPS5839030A (ja) * 1981-08-31 1983-03-07 Matsushita Electric Ind Co Ltd 半導体装置
JPS5856455A (ja) * 1981-09-30 1983-04-04 Toshiba Corp 半導体装置およびその製造方法
JPS5895862A (ja) * 1981-11-30 1983-06-07 Mitsubishi Electric Corp 積層構造半導体装置
JPS58103149A (ja) * 1981-12-15 1983-06-20 Matsushita Electric Works Ltd 半導体装置
JPS60121755A (ja) * 1983-12-05 1985-06-29 Toshiba Corp 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5655067A (en) * 1979-10-11 1981-05-15 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device
JPS5839030A (ja) * 1981-08-31 1983-03-07 Matsushita Electric Ind Co Ltd 半導体装置
JPS5856455A (ja) * 1981-09-30 1983-04-04 Toshiba Corp 半導体装置およびその製造方法
JPS5895862A (ja) * 1981-11-30 1983-06-07 Mitsubishi Electric Corp 積層構造半導体装置
JPS58103149A (ja) * 1981-12-15 1983-06-20 Matsushita Electric Works Ltd 半導体装置
JPS60121755A (ja) * 1983-12-05 1985-06-29 Toshiba Corp 半導体装置

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051865A (en) * 1985-06-17 1991-09-24 Fujitsu Limited Multi-layer semiconductor device
JPS63110740A (ja) * 1986-10-29 1988-05-16 Nec Corp 半導体装置
JPH01168041A (ja) * 1987-11-18 1989-07-03 Grumman Aerospace Corp 集積回路チップの製造方法
FR2666452A1 (fr) * 1990-09-03 1992-03-06 Mitsubishi Electric Corp Module de circuit a semiconducteurs multicouche.
EP0593666A1 (en) * 1991-06-24 1994-04-27 Irvine Sensors Corporation Fabricating electronic circuitry unit containing stacked ic layers having lead rerouting
EP0593666A4 (en) * 1991-06-24 1994-07-27 Irvine Sensors Corp Fabricating electronic circuitry unit containing stacked ic layers having lead rerouting
EP0522518A2 (en) * 1991-07-09 1993-01-13 Hughes Aircraft Company Stacked chip assembly and manufacturing method therefor
EP0522518A3 (en) * 1991-07-09 1994-11-30 Hughes Aircraft Co Stacked chip assembly and manufacturing method therefor
US7692931B2 (en) 2006-07-17 2010-04-06 Micron Technology, Inc. Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
US8869387B2 (en) 2006-07-17 2014-10-28 Micron Technology, Inc. Methods for making microelectronic die systems
US9653444B2 (en) 2007-07-24 2017-05-16 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US10396059B2 (en) 2007-07-24 2019-08-27 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US7843050B2 (en) 2007-07-24 2010-11-30 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US10056359B2 (en) 2007-07-24 2018-08-21 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US8198720B2 (en) 2007-07-24 2012-06-12 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US8906744B2 (en) 2007-07-24 2014-12-09 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US9165910B2 (en) 2007-07-24 2015-10-20 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US7947529B2 (en) 2007-08-16 2011-05-24 Micron Technology, Inc. Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
WO2009025974A3 (en) * 2007-08-16 2009-05-07 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
WO2009025974A2 (en) * 2007-08-16 2009-02-26 Micron Technology, Inc. Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
CN107994001A (zh) * 2017-11-28 2018-05-04 信利光电股份有限公司 一种芯片封装和终端设备
JP2022047488A (ja) * 2020-09-11 2022-03-24 ウェスタン デジタル テクノロジーズ インコーポレーテッド シリコンダイのストレートワイヤボンディング
US11456272B2 (en) 2020-09-11 2022-09-27 Western Digital Technologies, Inc. Straight wirebonding of silicon dies

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